hfi_venus_io.h (5063B)
1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Copyright (c) 2012-2016, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2017 Linaro Ltd. 5 */ 6#ifndef __VENUS_HFI_VENUS_IO_H__ 7#define __VENUS_HFI_VENUS_IO_H__ 8 9#define VBIF_BASE 0x80000 10 11#define VBIF_AXI_HALT_CTRL0 0x208 12#define VBIF_AXI_HALT_CTRL1 0x20c 13 14#define VBIF_AXI_HALT_CTRL0_HALT_REQ BIT(0) 15#define VBIF_AXI_HALT_CTRL1_HALT_ACK BIT(0) 16#define VBIF_AXI_HALT_ACK_TIMEOUT_US 500000 17 18#define CPU_BASE 0xc0000 19 20#define CPU_CS_BASE (CPU_BASE + 0x12000) 21#define CPU_IC_BASE (CPU_BASE + 0x1f000) 22#define CPU_BASE_V6 0xa0000 23#define CPU_CS_BASE_V6 CPU_BASE_V6 24#define CPU_IC_BASE_V6 (CPU_BASE_V6 + 0x138) 25 26#define CPU_CS_A2HSOFTINTCLR 0x1c 27 28#define VIDC_CTRL_INIT 0x48 29#define VIDC_CTRL_INIT_RESERVED_BITS31_1_MASK 0xfffffffe 30#define VIDC_CTRL_INIT_RESERVED_BITS31_1_SHIFT 1 31#define VIDC_CTRL_INIT_CTRL_MASK 0x1 32#define VIDC_CTRL_INIT_CTRL_SHIFT 0 33 34/* HFI control status */ 35#define CPU_CS_SCIACMDARG0 0x4c 36#define CPU_CS_SCIACMDARG0_MASK 0xff 37#define CPU_CS_SCIACMDARG0_SHIFT 0x0 38#define CPU_CS_SCIACMDARG0_ERROR_STATUS_MASK 0xfe 39#define CPU_CS_SCIACMDARG0_ERROR_STATUS_SHIFT 0x1 40#define CPU_CS_SCIACMDARG0_INIT_STATUS_MASK 0x1 41#define CPU_CS_SCIACMDARG0_INIT_STATUS_SHIFT 0x0 42#define CPU_CS_SCIACMDARG0_PC_READY BIT(8) 43#define CPU_CS_SCIACMDARG0_INIT_IDLE_MSG_MASK BIT(30) 44 45/* HFI queue table info */ 46#define CPU_CS_SCIACMDARG1 0x50 47 48/* HFI queue table address */ 49#define CPU_CS_SCIACMDARG2 0x54 50 51/* Venus cpu */ 52#define CPU_CS_SCIACMDARG3 0x58 53 54#define SFR_ADDR 0x5c 55#define MMAP_ADDR 0x60 56#define UC_REGION_ADDR 0x64 57#define UC_REGION_SIZE 0x68 58 59#define CPU_CS_H2XSOFTINTEN_V6 0x148 60 61#define CPU_CS_X2RPMH_V6 0x168 62#define CPU_CS_X2RPMH_MASK0_BMSK_V6 0x1 63#define CPU_CS_X2RPMH_MASK0_SHFT_V6 0x0 64#define CPU_CS_X2RPMH_MASK1_BMSK_V6 0x2 65#define CPU_CS_X2RPMH_MASK1_SHFT_V6 0x1 66#define CPU_CS_X2RPMH_SWOVERRIDE_BMSK_V6 0x4 67#define CPU_CS_X2RPMH_SWOVERRIDE_SHFT_V6 0x3 68 69/* Relative to CPU_IC_BASE */ 70#define CPU_IC_SOFTINT 0x18 71#define CPU_IC_SOFTINT_V6 0x150 72#define CPU_IC_SOFTINT_H2A_MASK 0x8000 73#define CPU_IC_SOFTINT_H2A_SHIFT 0xf 74#define CPU_IC_SOFTINT_H2A_SHIFT_V6 0x0 75 76/* Venus wrapper */ 77#define WRAPPER_BASE_V6 0x000b0000 78#define WRAPPER_BASE 0x000e0000 79 80#define WRAPPER_HW_VERSION 0x00 81#define WRAPPER_HW_VERSION_MAJOR_VERSION_MASK 0x78000000 82#define WRAPPER_HW_VERSION_MAJOR_VERSION_SHIFT 28 83#define WRAPPER_HW_VERSION_MINOR_VERSION_MASK 0xfff0000 84#define WRAPPER_HW_VERSION_MINOR_VERSION_SHIFT 16 85#define WRAPPER_HW_VERSION_STEP_VERSION_MASK 0xffff 86 87#define WRAPPER_CLOCK_CONFIG 0x04 88 89#define WRAPPER_INTR_STATUS 0x0c 90#define WRAPPER_INTR_STATUS_A2HWD_MASK 0x10 91#define WRAPPER_INTR_STATUS_A2HWD_SHIFT 0x4 92#define WRAPPER_INTR_STATUS_A2H_MASK 0x4 93#define WRAPPER_INTR_STATUS_A2H_SHIFT 0x2 94 95#define WRAPPER_INTR_MASK 0x10 96#define WRAPPER_INTR_MASK_A2HWD_BASK 0x10 97#define WRAPPER_INTR_MASK_A2HWD_SHIFT 0x4 98#define WRAPPER_INTR_MASK_A2HVCODEC_MASK 0x8 99#define WRAPPER_INTR_MASK_A2HVCODEC_SHIFT 0x3 100#define WRAPPER_INTR_MASK_A2HCPU_MASK 0x4 101#define WRAPPER_INTR_MASK_A2HCPU_SHIFT 0x2 102 103#define WRAPPER_INTR_STATUS_A2HWD_MASK_V6 0x8 104#define WRAPPER_INTR_MASK_A2HWD_BASK_V6 0x8 105 106#define WRAPPER_INTR_CLEAR 0x14 107#define WRAPPER_INTR_CLEAR_A2HWD_MASK 0x10 108#define WRAPPER_INTR_CLEAR_A2HWD_SHIFT 0x4 109#define WRAPPER_INTR_CLEAR_A2H_MASK 0x4 110#define WRAPPER_INTR_CLEAR_A2H_SHIFT 0x2 111 112#define WRAPPER_POWER_STATUS 0x44 113#define WRAPPER_VDEC_VCODEC_POWER_CONTROL 0x48 114#define WRAPPER_VENC_VCODEC_POWER_CONTROL 0x4c 115#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL_V6 0x54 116#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS_V6 0x58 117#define WRAPPER_VDEC_VENC_AHB_BRIDGE_SYNC_RESET 0x64 118 119#define WRAPPER_CPU_CLOCK_CONFIG 0x2000 120#define WRAPPER_CPU_AXI_HALT 0x2008 121#define WRAPPER_CPU_AXI_HALT_HALT BIT(16) 122#define WRAPPER_CPU_AXI_HALT_STATUS 0x200c 123#define WRAPPER_CPU_AXI_HALT_STATUS_IDLE BIT(24) 124 125#define WRAPPER_CPU_CGC_DIS 0x2010 126#define WRAPPER_CPU_STATUS 0x2014 127#define WRAPPER_CPU_STATUS_WFI BIT(0) 128#define WRAPPER_SW_RESET 0x3000 129#define WRAPPER_CPA_START_ADDR 0x1020 130#define WRAPPER_CPA_END_ADDR 0x1024 131#define WRAPPER_FW_START_ADDR 0x1028 132#define WRAPPER_FW_END_ADDR 0x102C 133#define WRAPPER_NONPIX_START_ADDR 0x1030 134#define WRAPPER_NONPIX_END_ADDR 0x1034 135#define WRAPPER_A9SS_SW_RESET 0x3000 136#define WRAPPER_A9SS_SW_RESET_BIT BIT(4) 137 138/* Venus 4xx */ 139#define WRAPPER_VCODEC0_MMCC_POWER_STATUS 0x90 140#define WRAPPER_VCODEC0_MMCC_POWER_CONTROL 0x94 141 142#define WRAPPER_VCODEC1_MMCC_POWER_STATUS 0x110 143#define WRAPPER_VCODEC1_MMCC_POWER_CONTROL 0x114 144 145/* Venus 6xx */ 146#define WRAPPER_CORE_POWER_STATUS_V6 0x80 147#define WRAPPER_CORE_POWER_CONTROL_V6 0x84 148 149/* Wrapper TZ 6xx */ 150#define WRAPPER_TZ_BASE_V6 0x000c0000 151#define WRAPPER_TZ_CPU_STATUS_V6 0x10 152#define WRAPPER_TZ_XTSS_SW_RESET 0x1000 153#define WRAPPER_XTSS_SW_RESET_BIT BIT(0) 154 155/* Venus AON */ 156#define AON_BASE_V6 0x000e0000 157#define AON_WRAPPER_MVP_NOC_LPI_CONTROL 0x00 158#define AON_WRAPPER_MVP_NOC_LPI_STATUS 0x04 159 160#endif