cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

regs-mfc-v10.h (2951B)


      1/* SPDX-License-Identifier: GPL-2.0 */
      2/*
      3 *
      4 * Copyright (c) 2017 Samsung Electronics Co., Ltd.
      5 *     http://www.samsung.com/
      6 *
      7 * Register definition file for Samsung MFC V10.x Interface (FIMV) driver
      8 *
      9 */
     10
     11#ifndef _REGS_MFC_V10_H
     12#define _REGS_MFC_V10_H
     13
     14#include <linux/sizes.h>
     15#include "regs-mfc-v8.h"
     16
     17/* MFCv10 register definitions*/
     18#define S5P_FIMV_MFC_CLOCK_OFF_V10			0x7120
     19#define S5P_FIMV_MFC_STATE_V10				0x7124
     20#define S5P_FIMV_D_STATIC_BUFFER_ADDR_V10		0xF570
     21#define S5P_FIMV_D_STATIC_BUFFER_SIZE_V10		0xF574
     22#define S5P_FIMV_E_NUM_T_LAYER_V10			0xFBAC
     23#define S5P_FIMV_E_HIERARCHICAL_QP_LAYER0_V10		0xFBB0
     24#define S5P_FIMV_E_HIERARCHICAL_QP_LAYER1_V10		0xFBB4
     25#define S5P_FIMV_E_HIERARCHICAL_QP_LAYER2_V10		0xFBB8
     26#define S5P_FIMV_E_HIERARCHICAL_QP_LAYER3_V10		0xFBBC
     27#define S5P_FIMV_E_HIERARCHICAL_QP_LAYER4_V10		0xFBC0
     28#define S5P_FIMV_E_HIERARCHICAL_QP_LAYER5_V10		0xFBC4
     29#define S5P_FIMV_E_HIERARCHICAL_QP_LAYER6_V10		0xFBC8
     30#define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER0_V10	0xFD18
     31#define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER1_V10	0xFD1C
     32#define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER2_V10	0xFD20
     33#define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER3_V10	0xFD24
     34#define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER4_V10	0xFD28
     35#define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER5_V10	0xFD2C
     36#define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER6_V10	0xFD30
     37#define S5P_FIMV_E_HEVC_OPTIONS_V10			0xFDD4
     38#define S5P_FIMV_E_HEVC_REFRESH_PERIOD_V10		0xFDD8
     39#define S5P_FIMV_E_HEVC_CHROMA_QP_OFFSET_V10		0xFDDC
     40#define S5P_FIMV_E_HEVC_LF_BETA_OFFSET_DIV2_V10		0xFDE0
     41#define S5P_FIMV_E_HEVC_LF_TC_OFFSET_DIV2_V10		0xFDE4
     42#define S5P_FIMV_E_HEVC_NAL_CONTROL_V10			0xFDE8
     43
     44/* MFCv10 Context buffer sizes */
     45#define MFC_CTX_BUF_SIZE_V10		(30 * SZ_1K)
     46#define MFC_H264_DEC_CTX_BUF_SIZE_V10	(2 * SZ_1M)
     47#define MFC_OTHER_DEC_CTX_BUF_SIZE_V10	(20 * SZ_1K)
     48#define MFC_H264_ENC_CTX_BUF_SIZE_V10	(100 * SZ_1K)
     49#define MFC_HEVC_ENC_CTX_BUF_SIZE_V10	(30 * SZ_1K)
     50#define MFC_OTHER_ENC_CTX_BUF_SIZE_V10  (15 * SZ_1K)
     51
     52/* MFCv10 variant defines */
     53#define MAX_FW_SIZE_V10		(SZ_1M)
     54#define MAX_CPB_SIZE_V10	(3 * SZ_1M)
     55#define MFC_VERSION_V10		0xA0
     56#define MFC_NUM_PORTS_V10	1
     57
     58/* MFCv10 codec defines*/
     59#define S5P_FIMV_CODEC_HEVC_DEC		17
     60#define S5P_FIMV_CODEC_VP9_DEC		18
     61#define S5P_FIMV_CODEC_HEVC_ENC         26
     62
     63/* Decoder buffer size for MFC v10 */
     64#define DEC_VP9_STATIC_BUFFER_SIZE	20480
     65
     66/* Encoder buffer size for MFC v10.0 */
     67#define ENC_V100_BASE_SIZE(x, y) \
     68	(((x + 3) * (y + 3) * 8) \
     69	+  ((y * 64) + 1280) * DIV_ROUND_UP(x, 8))
     70
     71#define ENC_V100_H264_ME_SIZE(x, y) \
     72	(ENC_V100_BASE_SIZE(x, y) \
     73	+ (DIV_ROUND_UP(x * y, 64) * 32))
     74
     75#define ENC_V100_MPEG4_ME_SIZE(x, y) \
     76	(ENC_V100_BASE_SIZE(x, y) \
     77	+ (DIV_ROUND_UP(x * y, 128) * 16))
     78
     79#define ENC_V100_VP8_ME_SIZE(x, y) \
     80	ENC_V100_BASE_SIZE(x, y)
     81
     82#define ENC_V100_HEVC_ME_SIZE(x, y)	\
     83	(((x + 3) * (y + 3) * 32)	\
     84	 + ((y * 128) + 1280) * DIV_ROUND_UP(x, 4))
     85
     86#endif /*_REGS_MFC_V10_H*/
     87