cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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s5p_mfc_opr_v5.h (2795B)

      1/* SPDX-License-Identifier: GPL-2.0-only */
      2/*
      3 * drivers/media/platform/samsung/mfc5/s5p_mfc_opr_v5.h
      4 *
      5 * Header file for Samsung MFC (Multi Function Codec - FIMV) driver
      6 * Contains declarations of hw related functions.
      7 *
      8 * Kamil Debski, Copyright (C) 2011 Samsung Electronics
      9 * http://www.samsung.com/
     10 */
     11
     12#ifndef S5P_MFC_OPR_V5_H_
     13#define S5P_MFC_OPR_V5_H_
     14
     15#include "s5p_mfc_common.h"
     16#include "s5p_mfc_opr.h"
     17
     18enum MFC_SHM_OFS {
     19	EXTENEDED_DECODE_STATUS	= 0x00,	/* D */
     20	SET_FRAME_TAG		= 0x04, /* D */
     21	GET_FRAME_TAG_TOP	= 0x08, /* D */
     22	GET_FRAME_TAG_BOT	= 0x0C, /* D */
     23	PIC_TIME_TOP		= 0x10, /* D */
     24	PIC_TIME_BOT		= 0x14, /* D */
     25	START_BYTE_NUM		= 0x18, /* D */
     26
     27	CROP_INFO_H		= 0x20, /* D */
     28	CROP_INFO_V		= 0x24, /* D */
     29	EXT_ENC_CONTROL		= 0x28,	/* E */
     30	ENC_PARAM_CHANGE	= 0x2C,	/* E */
     31	RC_VOP_TIMING		= 0x30,	/* E, MPEG4 */
     32	HEC_PERIOD		= 0x34,	/* E, MPEG4 */
     33	METADATA_ENABLE		= 0x38, /* C */
     34	METADATA_STATUS		= 0x3C, /* C */
     35	METADATA_DISPLAY_INDEX	= 0x40,	/* C */
     36	EXT_METADATA_START_ADDR	= 0x44, /* C */
     37	PUT_EXTRADATA		= 0x48, /* C */
     38	EXTRADATA_ADDR		= 0x4C, /* C */
     39
     40	ALLOC_LUMA_DPB_SIZE	= 0x64,	/* D */
     41	ALLOC_CHROMA_DPB_SIZE	= 0x68,	/* D */
     42	ALLOC_MV_SIZE		= 0x6C,	/* D */
     43	P_B_FRAME_QP		= 0x70,	/* E */
     44	SAMPLE_ASPECT_RATIO_IDC	= 0x74, /* E, H.264, depend on
     45				ASPECT_RATIO_VUI_ENABLE in EXT_ENC_CONTROL */
     46	EXTENDED_SAR		= 0x78, /* E, H.264, depned on
     47				ASPECT_RATIO_VUI_ENABLE in EXT_ENC_CONTROL */
     48	DISP_PIC_PROFILE	= 0x7C, /* D */
     49	FLUSH_CMD_TYPE		= 0x80, /* C */
     50	FLUSH_CMD_INBUF1	= 0x84, /* C */
     51	FLUSH_CMD_INBUF2	= 0x88, /* C */
     52	FLUSH_CMD_OUTBUF	= 0x8C, /* E */
     53	NEW_RC_BIT_RATE		= 0x90, /* E, format as RC_BIT_RATE(0xC5A8)
     54			depend on RC_BIT_RATE_CHANGE in ENC_PARAM_CHANGE */
     55	NEW_RC_FRAME_RATE	= 0x94, /* E, format as RC_FRAME_RATE(0xD0D0)
     56			depend on RC_FRAME_RATE_CHANGE in ENC_PARAM_CHANGE */
     57	NEW_I_PERIOD		= 0x98, /* E, format as I_FRM_CTRL(0xC504)
     58			depend on I_PERIOD_CHANGE in ENC_PARAM_CHANGE */
     59	H264_I_PERIOD		= 0x9C, /* E, H.264, open GOP */
     60	RC_CONTROL_CONFIG	= 0xA0, /* E */
     61	BATCH_INPUT_ADDR	= 0xA4, /* E */
     62	BATCH_OUTPUT_ADDR	= 0xA8, /* E */
     63	BATCH_OUTPUT_SIZE	= 0xAC, /* E */
     64	MIN_LUMA_DPB_SIZE	= 0xB0, /* D */
     65	DEVICE_FORMAT_ID	= 0xB4, /* C */
     66	H264_POC_TYPE		= 0xB8, /* D */
     67	MIN_CHROMA_DPB_SIZE	= 0xBC, /* D */
     68	DISP_PIC_FRAME_TYPE	= 0xC0, /* D */
     69	FREE_LUMA_DPB		= 0xC4, /* D, VC1 MPEG4 */
     70	ASPECT_RATIO_INFO	= 0xC8, /* D, MPEG4 */
     71	EXTENDED_PAR		= 0xCC, /* D, MPEG4 */
     72	DBG_HISTORY_INPUT0	= 0xD0, /* C */
     73	DBG_HISTORY_INPUT1	= 0xD4,	/* C */
     74	DBG_HISTORY_OUTPUT	= 0xD8,	/* C */
     75	HIERARCHICAL_P_QP	= 0xE0, /* E, H.264 */
     76	FRAME_PACK_SEI_ENABLE	= 0x168, /* C */
     77	FRAME_PACK_SEI_AVAIL	= 0x16c, /* D */
     78	FRAME_PACK_SEI_INFO	= 0x17c, /* E */
     79};
     80
     81struct s5p_mfc_hw_ops *s5p_mfc_init_hw_ops_v5(void);
     82#endif /* S5P_MFC_OPR_H_ */