dma2d-regs.h (2949B)
1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * ST stm32 Chrom-Art - 2D Graphics Accelerator Driver 4 * 5 * Copyright (c) 2021 Dillon Min 6 * Dillon Min, <dillon.minfei@gmail.com> 7 * 8 * based on s5p-g2d 9 * 10 * Copyright (c) 2011 Samsung Electronics Co., Ltd. 11 * Kamil Debski, <k.debski@samsung.com> 12 */ 13 14#ifndef __DMA2D_REGS_H__ 15#define __DMA2D_REGS_H__ 16 17#define DMA2D_CR_REG 0x0000 18#define CR_MODE_MASK GENMASK(17, 16) 19#define CR_MODE_SHIFT 16 20#define CR_M2M 0x0000 21#define CR_M2M_PFC BIT(16) 22#define CR_M2M_BLEND BIT(17) 23#define CR_R2M (BIT(17) | BIT(16)) 24#define CR_CEIE BIT(13) 25#define CR_CTCIE BIT(12) 26#define CR_CAEIE BIT(11) 27#define CR_TWIE BIT(10) 28#define CR_TCIE BIT(9) 29#define CR_TEIE BIT(8) 30#define CR_ABORT BIT(2) 31#define CR_SUSP BIT(1) 32#define CR_START BIT(0) 33 34#define DMA2D_ISR_REG 0x0004 35#define ISR_CEIF BIT(5) 36#define ISR_CTCIF BIT(4) 37#define ISR_CAEIF BIT(3) 38#define ISR_TWIF BIT(2) 39#define ISR_TCIF BIT(1) 40#define ISR_TEIF BIT(0) 41 42#define DMA2D_IFCR_REG 0x0008 43#define IFCR_CCEIF BIT(5) 44#define IFCR_CCTCIF BIT(4) 45#define IFCR_CAECIF BIT(3) 46#define IFCR_CTWIF BIT(2) 47#define IFCR_CTCIF BIT(1) 48#define IFCR_CTEIF BIT(0) 49 50#define DMA2D_FGMAR_REG 0x000c 51#define DMA2D_FGOR_REG 0x0010 52#define FGOR_LO_MASK GENMASK(13, 0) 53 54#define DMA2D_BGMAR_REG 0x0014 55#define DMA2D_BGOR_REG 0x0018 56#define BGOR_LO_MASK GENMASK(13, 0) 57 58#define DMA2D_FGPFCCR_REG 0x001c 59#define FGPFCCR_ALPHA_MASK GENMASK(31, 24) 60#define FGPFCCR_AM_MASK GENMASK(17, 16) 61#define FGPFCCR_CS_MASK GENMASK(15, 8) 62#define FGPFCCR_START BIT(5) 63#define FGPFCCR_CCM_RGB888 BIT(4) 64#define FGPFCCR_CM_MASK GENMASK(3, 0) 65 66#define DMA2D_FGCOLR_REG 0x0020 67#define FGCOLR_REG_MASK GENMASK(23, 16) 68#define FGCOLR_GREEN_MASK GENMASK(15, 8) 69#define FGCOLR_BLUE_MASK GENMASK(7, 0) 70 71#define DMA2D_BGPFCCR_REG 0x0024 72#define BGPFCCR_ALPHA_MASK GENMASK(31, 24) 73#define BGPFCCR_AM_MASK GENMASK(17, 16) 74#define BGPFCCR_CS_MASK GENMASK(15, 8) 75#define BGPFCCR_START BIT(5) 76#define BGPFCCR_CCM_RGB888 BIT(4) 77#define BGPFCCR_CM_MASK GENMASK(3, 0) 78 79#define DMA2D_BGCOLR_REG 0x0028 80#define BGCOLR_REG_MASK GENMASK(23, 16) 81#define BGCOLR_GREEN_MASK GENMASK(15, 8) 82#define BGCOLR_BLUE_MASK GENMASK(7, 0) 83 84#define DMA2D_OPFCCR_REG 0x0034 85#define OPFCCR_CM_MASK GENMASK(2, 0) 86 87#define DMA2D_OCOLR_REG 0x0038 88#define OCOLR_ALPHA_MASK GENMASK(31, 24) 89#define OCOLR_RED_MASK GENMASK(23, 16) 90#define OCOLR_GREEN_MASK GENMASK(15, 8) 91#define OCOLR_BLUE_MASK GENMASK(7, 0) 92 93#define DMA2D_OMAR_REG 0x003c 94 95#define DMA2D_OOR_REG 0x0040 96#define OOR_LO_MASK GENMASK(13, 0) 97 98#define DMA2D_NLR_REG 0x0044 99#define NLR_PL_MASK GENMASK(29, 16) 100#define NLR_NL_MASK GENMASK(15, 0) 101 102/* Hardware limits */ 103#define MAX_WIDTH 2592 104#define MAX_HEIGHT 2592 105 106#define DEFAULT_WIDTH 240 107#define DEFAULT_HEIGHT 320 108#define DEFAULT_SIZE 307200 109 110#define CM_MODE_ARGB8888 0x00 111#define CM_MODE_ARGB4444 0x04 112#define CM_MODE_A4 0x0a 113#endif /* __DMA2D_REGS_H__ */