em28xx-reg.h (9769B)
1/* SPDX-License-Identifier: GPL-2.0 */ 2 3/* 4 * em28xx-reg.h - Register definitions for em28xx driver 5 */ 6 7#define EM_GPIO_0 ((unsigned char)BIT(0)) 8#define EM_GPIO_1 ((unsigned char)BIT(1)) 9#define EM_GPIO_2 ((unsigned char)BIT(2)) 10#define EM_GPIO_3 ((unsigned char)BIT(3)) 11#define EM_GPIO_4 ((unsigned char)BIT(4)) 12#define EM_GPIO_5 ((unsigned char)BIT(5)) 13#define EM_GPIO_6 ((unsigned char)BIT(6)) 14#define EM_GPIO_7 ((unsigned char)BIT(7)) 15 16#define EM_GPO_0 ((unsigned char)BIT(0)) 17#define EM_GPO_1 ((unsigned char)BIT(1)) 18#define EM_GPO_2 ((unsigned char)BIT(2)) 19#define EM_GPO_3 ((unsigned char)BIT(3)) 20 21/* em28xx endpoints */ 22/* 0x82: (always ?) analog */ 23#define EM28XX_EP_AUDIO 0x83 24/* 0x84: digital or analog */ 25 26/* em2800 registers */ 27#define EM2800_R08_AUDIOSRC 0x08 28 29/* em28xx registers */ 30 31#define EM28XX_R00_CHIPCFG 0x00 32 33/* em28xx Chip Configuration 0x00 */ 34#define EM2860_CHIPCFG_VENDOR_AUDIO 0x80 35#define EM2860_CHIPCFG_I2S_VOLUME_CAPABLE 0x40 36#define EM2820_CHIPCFG_I2S_3_SAMPRATES 0x30 37#define EM2860_CHIPCFG_I2S_5_SAMPRATES 0x30 38#define EM2820_CHIPCFG_I2S_1_SAMPRATE 0x20 39#define EM2860_CHIPCFG_I2S_3_SAMPRATES 0x20 40#define EM28XX_CHIPCFG_AC97 0x10 41#define EM28XX_CHIPCFG_AUDIOMASK 0x30 42 43#define EM28XX_R01_CHIPCFG2 0x01 44 45/* em28xx Chip Configuration 2 0x01 */ 46#define EM28XX_CHIPCFG2_TS_PRESENT 0x10 47#define EM28XX_CHIPCFG2_TS_REQ_INTERVAL_MASK 0x0c /* bits 3-2 */ 48#define EM28XX_CHIPCFG2_TS_REQ_INTERVAL_1MF 0x00 49#define EM28XX_CHIPCFG2_TS_REQ_INTERVAL_2MF 0x04 50#define EM28XX_CHIPCFG2_TS_REQ_INTERVAL_4MF 0x08 51#define EM28XX_CHIPCFG2_TS_REQ_INTERVAL_8MF 0x0c 52#define EM28XX_CHIPCFG2_TS_PACKETSIZE_MASK 0x03 /* bits 0-1 */ 53#define EM28XX_CHIPCFG2_TS_PACKETSIZE_188 0x00 54#define EM28XX_CHIPCFG2_TS_PACKETSIZE_376 0x01 55#define EM28XX_CHIPCFG2_TS_PACKETSIZE_564 0x02 56#define EM28XX_CHIPCFG2_TS_PACKETSIZE_752 0x03 57 58/* GPIO/GPO registers */ 59#define EM2880_R04_GPO 0x04 /* em2880-em2883 only */ 60#define EM2820_R08_GPIO_CTRL 0x08 /* em2820-em2873/83 only */ 61#define EM2820_R09_GPIO_STATE 0x09 /* em2820-em2873/83 only */ 62 63#define EM28XX_R06_I2C_CLK 0x06 64 65/* em28xx I2C Clock Register (0x06) */ 66#define EM28XX_I2C_CLK_ACK_LAST_READ 0x80 67#define EM28XX_I2C_CLK_WAIT_ENABLE 0x40 68#define EM28XX_I2C_EEPROM_ON_BOARD 0x08 69#define EM28XX_I2C_EEPROM_KEY_VALID 0x04 70#define EM2874_I2C_SECONDARY_BUS_SELECT 0x04 /* em2874 has two i2c buses */ 71#define EM28XX_I2C_FREQ_1_5_MHZ 0x03 /* bus frequency (bits [1-0]) */ 72#define EM28XX_I2C_FREQ_25_KHZ 0x02 73#define EM28XX_I2C_FREQ_400_KHZ 0x01 74#define EM28XX_I2C_FREQ_100_KHZ 0x00 75 76#define EM28XX_R0A_CHIPID 0x0a 77#define EM28XX_R0C_USBSUSP 0x0c 78#define EM28XX_R0C_USBSUSP_SNAPSHOT 0x20 /* 1=button pressed, needs reset */ 79 80#define EM28XX_R0E_AUDIOSRC 0x0e 81#define EM28XX_R0F_XCLK 0x0f 82 83/* em28xx XCLK Register (0x0f) */ 84#define EM28XX_XCLK_AUDIO_UNMUTE 0x80 /* otherwise audio muted */ 85#define EM28XX_XCLK_I2S_MSB_TIMING 0x40 /* otherwise standard timing */ 86#define EM28XX_XCLK_IR_RC5_MODE 0x20 /* otherwise NEC mode */ 87#define EM28XX_XCLK_IR_NEC_CHK_PARITY 0x10 88#define EM28XX_XCLK_FREQUENCY_30MHZ 0x00 /* Freq. select (bits [3-0]) */ 89#define EM28XX_XCLK_FREQUENCY_15MHZ 0x01 90#define EM28XX_XCLK_FREQUENCY_10MHZ 0x02 91#define EM28XX_XCLK_FREQUENCY_7_5MHZ 0x03 92#define EM28XX_XCLK_FREQUENCY_6MHZ 0x04 93#define EM28XX_XCLK_FREQUENCY_5MHZ 0x05 94#define EM28XX_XCLK_FREQUENCY_4_3MHZ 0x06 95#define EM28XX_XCLK_FREQUENCY_12MHZ 0x07 96#define EM28XX_XCLK_FREQUENCY_20MHZ 0x08 97#define EM28XX_XCLK_FREQUENCY_20MHZ_2 0x09 98#define EM28XX_XCLK_FREQUENCY_48MHZ 0x0a 99#define EM28XX_XCLK_FREQUENCY_24MHZ 0x0b 100 101#define EM28XX_R10_VINMODE 0x10 102 /* used by all non-camera devices: */ 103#define EM28XX_VINMODE_YUV422_CbYCrY 0x10 104 /* used by camera devices: */ 105#define EM28XX_VINMODE_YUV422_YUYV 0x08 106#define EM28XX_VINMODE_YUV422_YVYU 0x09 107#define EM28XX_VINMODE_YUV422_UYVY 0x0a 108#define EM28XX_VINMODE_YUV422_VYUY 0x0b 109#define EM28XX_VINMODE_RGB8_BGGR 0x0c 110#define EM28XX_VINMODE_RGB8_GRBG 0x0d 111#define EM28XX_VINMODE_RGB8_GBRG 0x0e 112#define EM28XX_VINMODE_RGB8_RGGB 0x0f 113 /* 114 * apparently: 115 * bit 0: swap component 1+2 with 3+4 116 * => e.g.: YUYV => YVYU, BGGR => GRBG 117 * bit 1: swap component 1 with 2 and 3 with 4 118 * => e.g.: YUYV => UYVY, BGGR => GBRG 119 */ 120 121#define EM28XX_R11_VINCTRL 0x11 122 123/* em28xx Video Input Control Register 0x11 */ 124#define EM28XX_VINCTRL_VBI_SLICED 0x80 125#define EM28XX_VINCTRL_VBI_RAW 0x40 126#define EM28XX_VINCTRL_VOUT_MODE_IN 0x20 /* HREF,VREF,VACT in output */ 127#define EM28XX_VINCTRL_CCIR656_ENABLE 0x10 128#define EM28XX_VINCTRL_VBI_16BIT_RAW 0x08 /* otherwise 8-bit raw */ 129#define EM28XX_VINCTRL_FID_ON_HREF 0x04 130#define EM28XX_VINCTRL_DUAL_EDGE_STROBE 0x02 131#define EM28XX_VINCTRL_INTERLACED 0x01 132 133#define EM28XX_R12_VINENABLE 0x12 /* */ 134 135#define EM28XX_R14_GAMMA 0x14 136#define EM28XX_R15_RGAIN 0x15 137#define EM28XX_R16_GGAIN 0x16 138#define EM28XX_R17_BGAIN 0x17 139#define EM28XX_R18_ROFFSET 0x18 140#define EM28XX_R19_GOFFSET 0x19 141#define EM28XX_R1A_BOFFSET 0x1a 142 143#define EM28XX_R1B_OFLOW 0x1b 144#define EM28XX_R1C_HSTART 0x1c 145#define EM28XX_R1D_VSTART 0x1d 146#define EM28XX_R1E_CWIDTH 0x1e 147#define EM28XX_R1F_CHEIGHT 0x1f 148 149#define EM28XX_R20_YGAIN 0x20 /* contrast [0:4] */ 150#define CONTRAST_DEFAULT 0x10 151 152#define EM28XX_R21_YOFFSET 0x21 /* brightness */ /* signed */ 153#define BRIGHTNESS_DEFAULT 0x00 154 155#define EM28XX_R22_UVGAIN 0x22 /* saturation [0:4] */ 156#define SATURATION_DEFAULT 0x10 157 158#define EM28XX_R23_UOFFSET 0x23 /* blue balance */ /* signed */ 159#define BLUE_BALANCE_DEFAULT 0x00 160 161#define EM28XX_R24_VOFFSET 0x24 /* red balance */ /* signed */ 162#define RED_BALANCE_DEFAULT 0x00 163 164#define EM28XX_R25_SHARPNESS 0x25 /* sharpness [0:4] */ 165#define SHARPNESS_DEFAULT 0x00 166 167#define EM28XX_R26_COMPR 0x26 168#define EM28XX_R27_OUTFMT 0x27 169 170/* em28xx Output Format Register (0x27) */ 171#define EM28XX_OUTFMT_RGB_8_RGRG 0x00 172#define EM28XX_OUTFMT_RGB_8_GRGR 0x01 173#define EM28XX_OUTFMT_RGB_8_GBGB 0x02 174#define EM28XX_OUTFMT_RGB_8_BGBG 0x03 175#define EM28XX_OUTFMT_RGB_16_656 0x04 176#define EM28XX_OUTFMT_RGB_8_BAYER 0x08 /* Pattern in Reg 0x10[1-0] */ 177#define EM28XX_OUTFMT_YUV211 0x10 178#define EM28XX_OUTFMT_YUV422_Y0UY1V 0x14 179#define EM28XX_OUTFMT_YUV422_Y1UY0V 0x15 180#define EM28XX_OUTFMT_YUV411 0x18 181 182#define EM28XX_R28_XMIN 0x28 183#define EM28XX_R29_XMAX 0x29 184#define EM28XX_R2A_YMIN 0x2a 185#define EM28XX_R2B_YMAX 0x2b 186 187#define EM28XX_R30_HSCALELOW 0x30 188#define EM28XX_R31_HSCALEHIGH 0x31 189#define EM28XX_R32_VSCALELOW 0x32 190#define EM28XX_R33_VSCALEHIGH 0x33 191#define EM28XX_HVSCALE_MAX 0x3fff /* => 20% */ 192 193#define EM28XX_R34_VBI_START_H 0x34 194#define EM28XX_R35_VBI_START_V 0x35 195/* 196 * NOTE: the EM276x (and EM25xx, EM277x/8x ?) (camera bridges) use these 197 * registers for a different unknown purpose. 198 * => register 0x34 is set to capture width / 16 199 * => register 0x35 is set to capture height / 16 200 */ 201 202#define EM28XX_R36_VBI_WIDTH 0x36 203#define EM28XX_R37_VBI_HEIGHT 0x37 204 205#define EM28XX_R40_AC97LSB 0x40 206#define EM28XX_R41_AC97MSB 0x41 207#define EM28XX_R42_AC97ADDR 0x42 208#define EM28XX_R43_AC97BUSY 0x43 209 210#define EM28XX_R45_IR 0x45 211 /* 212 * 0x45 bit 7 - parity bit 213 * bits 6-0 - count 214 * 0x46 IR brand 215 * 0x47 IR data 216 */ 217 218/* em2874 registers */ 219#define EM2874_R50_IR_CONFIG 0x50 220#define EM2874_R51_IR 0x51 221#define EM2874_R5D_TS1_PKT_SIZE 0x5d 222#define EM2874_R5E_TS2_PKT_SIZE 0x5e 223 /* 224 * For both TS1 and TS2, In isochronous mode: 225 * 0x01 188 bytes 226 * 0x02 376 bytes 227 * 0x03 564 bytes 228 * 0x04 752 bytes 229 * 0x05 940 bytes 230 * In bulk mode: 231 * 0x01..0xff total packet count in 188-byte 232 */ 233 234#define EM2874_R5F_TS_ENABLE 0x5f 235 236/* em2874/174/84, em25xx, em276x/7x/8x GPIO registers */ 237/* 238 * NOTE: not all ports are bonded out; 239 * Some ports are multiplexed with special function I/O 240 */ 241#define EM2874_R80_GPIO_P0_CTRL 0x80 242#define EM2874_R81_GPIO_P1_CTRL 0x81 243#define EM2874_R82_GPIO_P2_CTRL 0x82 244#define EM2874_R83_GPIO_P3_CTRL 0x83 245#define EM2874_R84_GPIO_P0_STATE 0x84 246#define EM2874_R85_GPIO_P1_STATE 0x85 247#define EM2874_R86_GPIO_P2_STATE 0x86 248#define EM2874_R87_GPIO_P3_STATE 0x87 249 250/* em2874 IR config register (0x50) */ 251#define EM2874_IR_NEC 0x00 252#define EM2874_IR_NEC_NO_PARITY 0x01 253#define EM2874_IR_RC5 0x04 254#define EM2874_IR_RC6_MODE_0 0x08 255#define EM2874_IR_RC6_MODE_6A 0x0b 256 257/* em2874 Transport Stream Enable Register (0x5f) */ 258#define EM2874_TS1_CAPTURE_ENABLE ((unsigned char)BIT(0)) 259#define EM2874_TS1_FILTER_ENABLE ((unsigned char)BIT(1)) 260#define EM2874_TS1_NULL_DISCARD ((unsigned char)BIT(2)) 261#define EM2874_TS2_CAPTURE_ENABLE ((unsigned char)BIT(4)) 262#define EM2874_TS2_FILTER_ENABLE ((unsigned char)BIT(5)) 263#define EM2874_TS2_NULL_DISCARD ((unsigned char)BIT(6)) 264 265/* register settings */ 266#define EM2800_AUDIO_SRC_TUNER 0x0d 267#define EM2800_AUDIO_SRC_LINE 0x0c 268#define EM28XX_AUDIO_SRC_TUNER 0xc0 269#define EM28XX_AUDIO_SRC_LINE 0x80 270 271/* FIXME: Need to be populated with the other chip ID's */ 272enum em28xx_chip_id { 273 CHIP_ID_EM2800 = 7, 274 CHIP_ID_EM2710 = 17, 275 CHIP_ID_EM2820 = 18, /* Also used by some em2710 */ 276 CHIP_ID_EM2840 = 20, 277 CHIP_ID_EM2750 = 33, 278 CHIP_ID_EM2860 = 34, 279 CHIP_ID_EM2870 = 35, 280 CHIP_ID_EM2883 = 36, 281 CHIP_ID_EM2765 = 54, 282 CHIP_ID_EM2874 = 65, 283 CHIP_ID_EM2884 = 68, 284 CHIP_ID_EM28174 = 113, 285 CHIP_ID_EM28178 = 114, 286}; 287 288/* 289 * Registers used by em202 290 */ 291 292/* EMP202 vendor registers */ 293#define EM202_EXT_MODEM_CTRL 0x3e 294#define EM202_GPIO_CONF 0x4c 295#define EM202_GPIO_POLARITY 0x4e 296#define EM202_GPIO_STICKY 0x50 297#define EM202_GPIO_MASK 0x52 298#define EM202_GPIO_STATUS 0x54 299#define EM202_SPDIF_OUT_SEL 0x6a 300#define EM202_ANTIPOP 0x72 301#define EM202_EAPD_GPIO_ACCESS 0x74