cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

tegra194.c (24225B)

      1// SPDX-License-Identifier: GPL-2.0-only
      2/*
      3 * Copyright (C) 2017-2021 NVIDIA CORPORATION.  All rights reserved.
      4 */
      5
      6#include <soc/tegra/mc.h>
      7
      8#include <dt-bindings/memory/tegra194-mc.h>
      9
     10#include "mc.h"
     11
     12static const struct tegra_mc_client tegra194_mc_clients[] = {
     13	{
     14		.id = TEGRA194_MEMORY_CLIENT_PTCR,
     15		.name = "ptcr",
     16		.sid = TEGRA194_SID_PASSTHROUGH,
     17		.regs = {
     18			.sid = {
     19				.override = 0x000,
     20				.security = 0x004,
     21			},
     22		},
     23	}, {
     24		.id = TEGRA194_MEMORY_CLIENT_MIU7R,
     25		.name = "miu7r",
     26		.sid = TEGRA194_SID_MIU,
     27		.regs = {
     28			.sid = {
     29				.override = 0x008,
     30				.security = 0x00c,
     31			},
     32		},
     33	}, {
     34		.id = TEGRA194_MEMORY_CLIENT_MIU7W,
     35		.name = "miu7w",
     36		.sid = TEGRA194_SID_MIU,
     37		.regs = {
     38			.sid = {
     39				.override = 0x010,
     40				.security = 0x014,
     41			},
     42		},
     43	}, {
     44		.id = TEGRA194_MEMORY_CLIENT_HDAR,
     45		.name = "hdar",
     46		.sid = TEGRA194_SID_HDA,
     47		.regs = {
     48			.sid = {
     49				.override = 0x0a8,
     50				.security = 0x0ac,
     51			},
     52		},
     53	}, {
     54		.id = TEGRA194_MEMORY_CLIENT_HOST1XDMAR,
     55		.name = "host1xdmar",
     56		.sid = TEGRA194_SID_HOST1X,
     57		.regs = {
     58			.sid = {
     59				.override = 0x0b0,
     60				.security = 0x0b4,
     61			},
     62		},
     63	}, {
     64		.id = TEGRA194_MEMORY_CLIENT_NVENCSRD,
     65		.name = "nvencsrd",
     66		.sid = TEGRA194_SID_NVENC,
     67		.regs = {
     68			.sid = {
     69				.override = 0x0e0,
     70				.security = 0x0e4,
     71			},
     72		},
     73	}, {
     74		.id = TEGRA194_MEMORY_CLIENT_SATAR,
     75		.name = "satar",
     76		.sid = TEGRA194_SID_SATA,
     77		.regs = {
     78			.sid = {
     79				.override = 0x0f8,
     80				.security = 0x0fc,
     81			},
     82		},
     83	}, {
     84		.id = TEGRA194_MEMORY_CLIENT_MPCORER,
     85		.name = "mpcorer",
     86		.sid = TEGRA194_SID_PASSTHROUGH,
     87		.regs = {
     88			.sid = {
     89				.override = 0x138,
     90				.security = 0x13c,
     91			},
     92		},
     93	}, {
     94		.id = TEGRA194_MEMORY_CLIENT_NVENCSWR,
     95		.name = "nvencswr",
     96		.sid = TEGRA194_SID_NVENC,
     97		.regs = {
     98			.sid = {
     99				.override = 0x158,
    100				.security = 0x15c,
    101			},
    102		},
    103	}, {
    104		.id = TEGRA194_MEMORY_CLIENT_HDAW,
    105		.name = "hdaw",
    106		.sid = TEGRA194_SID_HDA,
    107		.regs = {
    108			.sid = {
    109				.override = 0x1a8,
    110				.security = 0x1ac,
    111			},
    112		},
    113	}, {
    114		.id = TEGRA194_MEMORY_CLIENT_MPCOREW,
    115		.name = "mpcorew",
    116		.sid = TEGRA194_SID_PASSTHROUGH,
    117		.regs = {
    118			.sid = {
    119				.override = 0x1c8,
    120				.security = 0x1cc,
    121			},
    122		},
    123	}, {
    124		.id = TEGRA194_MEMORY_CLIENT_SATAW,
    125		.name = "sataw",
    126		.sid = TEGRA194_SID_SATA,
    127		.regs = {
    128			.sid = {
    129				.override = 0x1e8,
    130				.security = 0x1ec,
    131			},
    132		},
    133	}, {
    134		.id = TEGRA194_MEMORY_CLIENT_ISPRA,
    135		.name = "ispra",
    136		.sid = TEGRA194_SID_ISP,
    137		.regs = {
    138			.sid = {
    139				.override = 0x220,
    140				.security = 0x224,
    141			},
    142		},
    143	}, {
    144		.id = TEGRA194_MEMORY_CLIENT_ISPFALR,
    145		.name = "ispfalr",
    146		.sid = TEGRA194_SID_ISP_FALCON,
    147		.regs = {
    148			.sid = {
    149				.override = 0x228,
    150				.security = 0x22c,
    151			},
    152		},
    153	}, {
    154		.id = TEGRA194_MEMORY_CLIENT_ISPWA,
    155		.name = "ispwa",
    156		.sid = TEGRA194_SID_ISP,
    157		.regs = {
    158			.sid = {
    159				.override = 0x230,
    160				.security = 0x234,
    161			},
    162		},
    163	}, {
    164		.id = TEGRA194_MEMORY_CLIENT_ISPWB,
    165		.name = "ispwb",
    166		.sid = TEGRA194_SID_ISP,
    167		.regs = {
    168			.sid = {
    169				.override = 0x238,
    170				.security = 0x23c,
    171			},
    172		},
    173	}, {
    174		.id = TEGRA194_MEMORY_CLIENT_XUSB_HOSTR,
    175		.name = "xusb_hostr",
    176		.sid = TEGRA194_SID_XUSB_HOST,
    177		.regs = {
    178			.sid = {
    179				.override = 0x250,
    180				.security = 0x254,
    181			},
    182		},
    183	}, {
    184		.id = TEGRA194_MEMORY_CLIENT_XUSB_HOSTW,
    185		.name = "xusb_hostw",
    186		.sid = TEGRA194_SID_XUSB_HOST,
    187		.regs = {
    188			.sid = {
    189				.override = 0x258,
    190				.security = 0x25c,
    191			},
    192		},
    193	}, {
    194		.id = TEGRA194_MEMORY_CLIENT_XUSB_DEVR,
    195		.name = "xusb_devr",
    196		.sid = TEGRA194_SID_XUSB_DEV,
    197		.regs = {
    198			.sid = {
    199				.override = 0x260,
    200				.security = 0x264,
    201			},
    202		},
    203	}, {
    204		.id = TEGRA194_MEMORY_CLIENT_XUSB_DEVW,
    205		.name = "xusb_devw",
    206		.sid = TEGRA194_SID_XUSB_DEV,
    207		.regs = {
    208			.sid = {
    209				.override = 0x268,
    210				.security = 0x26c,
    211			},
    212		},
    213	}, {
    214		.id = TEGRA194_MEMORY_CLIENT_SDMMCRA,
    215		.name = "sdmmcra",
    216		.sid = TEGRA194_SID_SDMMC1,
    217		.regs = {
    218			.sid = {
    219				.override = 0x300,
    220				.security = 0x304,
    221			},
    222		},
    223	}, {
    224		.id = TEGRA194_MEMORY_CLIENT_SDMMCR,
    225		.name = "sdmmcr",
    226		.sid = TEGRA194_SID_SDMMC3,
    227		.regs = {
    228			.sid = {
    229				.override = 0x310,
    230				.security = 0x314,
    231			},
    232		},
    233	}, {
    234		.id = TEGRA194_MEMORY_CLIENT_SDMMCRAB,
    235		.name = "sdmmcrab",
    236		.sid = TEGRA194_SID_SDMMC4,
    237		.regs = {
    238			.sid = {
    239				.override = 0x318,
    240				.security = 0x31c,
    241			},
    242		},
    243	}, {
    244		.id = TEGRA194_MEMORY_CLIENT_SDMMCWA,
    245		.name = "sdmmcwa",
    246		.sid = TEGRA194_SID_SDMMC1,
    247		.regs = {
    248			.sid = {
    249				.override = 0x320,
    250				.security = 0x324,
    251			},
    252		},
    253	}, {
    254		.id = TEGRA194_MEMORY_CLIENT_SDMMCW,
    255		.name = "sdmmcw",
    256		.sid = TEGRA194_SID_SDMMC3,
    257		.regs = {
    258			.sid = {
    259				.override = 0x330,
    260				.security = 0x334,
    261			},
    262		},
    263	}, {
    264		.id = TEGRA194_MEMORY_CLIENT_SDMMCWAB,
    265		.name = "sdmmcwab",
    266		.sid = TEGRA194_SID_SDMMC4,
    267		.regs = {
    268			.sid = {
    269				.override = 0x338,
    270				.security = 0x33c,
    271			},
    272		},
    273	}, {
    274		.id = TEGRA194_MEMORY_CLIENT_VICSRD,
    275		.name = "vicsrd",
    276		.sid = TEGRA194_SID_VIC,
    277		.regs = {
    278			.sid = {
    279				.override = 0x360,
    280				.security = 0x364,
    281			},
    282		},
    283	}, {
    284		.id = TEGRA194_MEMORY_CLIENT_VICSWR,
    285		.name = "vicswr",
    286		.sid = TEGRA194_SID_VIC,
    287		.regs = {
    288			.sid = {
    289				.override = 0x368,
    290				.security = 0x36c,
    291			},
    292		},
    293	}, {
    294		.id = TEGRA194_MEMORY_CLIENT_VIW,
    295		.name = "viw",
    296		.sid = TEGRA194_SID_VI,
    297		.regs = {
    298			.sid = {
    299				.override = 0x390,
    300				.security = 0x394,
    301			},
    302		},
    303	}, {
    304		.id = TEGRA194_MEMORY_CLIENT_NVDECSRD,
    305		.name = "nvdecsrd",
    306		.sid = TEGRA194_SID_NVDEC,
    307		.regs = {
    308			.sid = {
    309				.override = 0x3c0,
    310				.security = 0x3c4,
    311			},
    312		},
    313	}, {
    314		.id = TEGRA194_MEMORY_CLIENT_NVDECSWR,
    315		.name = "nvdecswr",
    316		.sid = TEGRA194_SID_NVDEC,
    317		.regs = {
    318			.sid = {
    319				.override = 0x3c8,
    320				.security = 0x3cc,
    321			},
    322		},
    323	}, {
    324		.id = TEGRA194_MEMORY_CLIENT_APER,
    325		.name = "aper",
    326		.sid = TEGRA194_SID_APE,
    327		.regs = {
    328			.sid = {
    329				.override = 0x3c0,
    330				.security = 0x3c4,
    331			},
    332		},
    333	}, {
    334		.id = TEGRA194_MEMORY_CLIENT_APEW,
    335		.name = "apew",
    336		.sid = TEGRA194_SID_APE,
    337		.regs = {
    338			.sid = {
    339				.override = 0x3d0,
    340				.security = 0x3d4,
    341			},
    342		},
    343	}, {
    344		.id = TEGRA194_MEMORY_CLIENT_NVJPGSRD,
    345		.name = "nvjpgsrd",
    346		.sid = TEGRA194_SID_NVJPG,
    347		.regs = {
    348			.sid = {
    349				.override = 0x3f0,
    350				.security = 0x3f4,
    351			},
    352		},
    353	}, {
    354		.id = TEGRA194_MEMORY_CLIENT_NVJPGSWR,
    355		.name = "nvjpgswr",
    356		.sid = TEGRA194_SID_NVJPG,
    357		.regs = {
    358			.sid = {
    359				.override = 0x3f0,
    360				.security = 0x3f4,
    361			},
    362		},
    363	}, {
    364		.name = "axiapr",
    365		.id = TEGRA194_MEMORY_CLIENT_AXIAPR,
    366		.sid = TEGRA194_SID_PASSTHROUGH,
    367		.regs = {
    368			.sid = {
    369				.override = 0x410,
    370				.security = 0x414,
    371			},
    372		},
    373	}, {
    374		.id = TEGRA194_MEMORY_CLIENT_AXIAPW,
    375		.name = "axiapw",
    376		.sid = TEGRA194_SID_PASSTHROUGH,
    377		.regs = {
    378			.sid = {
    379				.override = 0x418,
    380				.security = 0x41c,
    381			},
    382		},
    383	}, {
    384		.id = TEGRA194_MEMORY_CLIENT_ETRR,
    385		.name = "etrr",
    386		.sid = TEGRA194_SID_ETR,
    387		.regs = {
    388			.sid = {
    389				.override = 0x420,
    390				.security = 0x424,
    391			},
    392		},
    393	}, {
    394		.id = TEGRA194_MEMORY_CLIENT_ETRW,
    395		.name = "etrw",
    396		.sid = TEGRA194_SID_ETR,
    397		.regs = {
    398			.sid = {
    399				.override = 0x428,
    400				.security = 0x42c,
    401			},
    402		},
    403	}, {
    404		.id = TEGRA194_MEMORY_CLIENT_AXISR,
    405		.name = "axisr",
    406		.sid = TEGRA194_SID_PASSTHROUGH,
    407		.regs = {
    408			.sid = {
    409				.override = 0x460,
    410				.security = 0x464,
    411			},
    412		},
    413	}, {
    414		.id = TEGRA194_MEMORY_CLIENT_AXISW,
    415		.name = "axisw",
    416		.sid = TEGRA194_SID_PASSTHROUGH,
    417		.regs = {
    418			.sid = {
    419				.override = 0x468,
    420				.security = 0x46c,
    421			},
    422		},
    423	}, {
    424		.id = TEGRA194_MEMORY_CLIENT_EQOSR,
    425		.name = "eqosr",
    426		.sid = TEGRA194_SID_EQOS,
    427		.regs = {
    428			.sid = {
    429				.override = 0x470,
    430				.security = 0x474,
    431			},
    432		},
    433	}, {
    434		.name = "eqosw",
    435		.id = TEGRA194_MEMORY_CLIENT_EQOSW,
    436		.sid = TEGRA194_SID_EQOS,
    437		.regs = {
    438			.sid = {
    439				.override = 0x478,
    440				.security = 0x47c,
    441			},
    442		},
    443	}, {
    444		.id = TEGRA194_MEMORY_CLIENT_UFSHCR,
    445		.name = "ufshcr",
    446		.sid = TEGRA194_SID_UFSHC,
    447		.regs = {
    448			.sid = {
    449				.override = 0x480,
    450				.security = 0x484,
    451			},
    452		},
    453	}, {
    454		.id = TEGRA194_MEMORY_CLIENT_UFSHCW,
    455		.name = "ufshcw",
    456		.sid = TEGRA194_SID_UFSHC,
    457		.regs = {
    458			.sid = {
    459				.override = 0x488,
    460				.security = 0x48c,
    461			},
    462		},
    463	}, {
    464		.id = TEGRA194_MEMORY_CLIENT_NVDISPLAYR,
    465		.name = "nvdisplayr",
    466		.sid = TEGRA194_SID_NVDISPLAY,
    467		.regs = {
    468			.sid = {
    469				.override = 0x490,
    470				.security = 0x494,
    471			},
    472		},
    473	}, {
    474		.id = TEGRA194_MEMORY_CLIENT_BPMPR,
    475		.name = "bpmpr",
    476		.sid = TEGRA194_SID_BPMP,
    477		.regs = {
    478			.sid = {
    479				.override = 0x498,
    480				.security = 0x49c,
    481			},
    482		},
    483	}, {
    484		.id = TEGRA194_MEMORY_CLIENT_BPMPW,
    485		.name = "bpmpw",
    486		.sid = TEGRA194_SID_BPMP,
    487		.regs = {
    488			.sid = {
    489				.override = 0x4a0,
    490				.security = 0x4a4,
    491			},
    492		},
    493	}, {
    494		.id = TEGRA194_MEMORY_CLIENT_BPMPDMAR,
    495		.name = "bpmpdmar",
    496		.sid = TEGRA194_SID_BPMP,
    497		.regs = {
    498			.sid = {
    499				.override = 0x4a8,
    500				.security = 0x4ac,
    501			},
    502		},
    503	}, {
    504		.id = TEGRA194_MEMORY_CLIENT_BPMPDMAW,
    505		.name = "bpmpdmaw",
    506		.sid = TEGRA194_SID_BPMP,
    507		.regs = {
    508			.sid = {
    509				.override = 0x4b0,
    510				.security = 0x4b4,
    511			},
    512		},
    513	}, {
    514		.id = TEGRA194_MEMORY_CLIENT_AONR,
    515		.name = "aonr",
    516		.sid = TEGRA194_SID_AON,
    517		.regs = {
    518			.sid = {
    519				.override = 0x4b8,
    520				.security = 0x4bc,
    521			},
    522		},
    523	}, {
    524		.id = TEGRA194_MEMORY_CLIENT_AONW,
    525		.name = "aonw",
    526		.sid = TEGRA194_SID_AON,
    527		.regs = {
    528			.sid = {
    529				.override = 0x4c0,
    530				.security = 0x4c4,
    531			},
    532		},
    533	}, {
    534		.id = TEGRA194_MEMORY_CLIENT_AONDMAR,
    535		.name = "aondmar",
    536		.sid = TEGRA194_SID_AON,
    537		.regs = {
    538			.sid = {
    539				.override = 0x4c8,
    540				.security = 0x4cc,
    541			},
    542		},
    543	}, {
    544		.id = TEGRA194_MEMORY_CLIENT_AONDMAW,
    545		.name = "aondmaw",
    546		.sid = TEGRA194_SID_AON,
    547		.regs = {
    548			.sid = {
    549				.override = 0x4d0,
    550				.security = 0x4d4,
    551			},
    552		},
    553	}, {
    554		.id = TEGRA194_MEMORY_CLIENT_SCER,
    555		.name = "scer",
    556		.sid = TEGRA194_SID_SCE,
    557		.regs = {
    558			.sid = {
    559				.override = 0x4d8,
    560				.security = 0x4dc,
    561			},
    562		},
    563	}, {
    564		.id = TEGRA194_MEMORY_CLIENT_SCEW,
    565		.name = "scew",
    566		.sid = TEGRA194_SID_SCE,
    567		.regs = {
    568			.sid = {
    569				.override = 0x4e0,
    570				.security = 0x4e4,
    571			},
    572		},
    573	}, {
    574		.id = TEGRA194_MEMORY_CLIENT_SCEDMAR,
    575		.name = "scedmar",
    576		.sid = TEGRA194_SID_SCE,
    577		.regs = {
    578			.sid = {
    579				.override = 0x4e8,
    580				.security = 0x4ec,
    581			},
    582		},
    583	}, {
    584		.id = TEGRA194_MEMORY_CLIENT_SCEDMAW,
    585		.name = "scedmaw",
    586		.sid = TEGRA194_SID_SCE,
    587		.regs = {
    588			.sid = {
    589				.override = 0x4f0,
    590				.security = 0x4f4,
    591			},
    592		},
    593	}, {
    594		.id = TEGRA194_MEMORY_CLIENT_APEDMAR,
    595		.name = "apedmar",
    596		.sid = TEGRA194_SID_APE,
    597		.regs = {
    598			.sid = {
    599				.override = 0x4f8,
    600				.security = 0x4fc,
    601			},
    602		},
    603	}, {
    604		.id = TEGRA194_MEMORY_CLIENT_APEDMAW,
    605		.name = "apedmaw",
    606		.sid = TEGRA194_SID_APE,
    607		.regs = {
    608			.sid = {
    609				.override = 0x500,
    610				.security = 0x504,
    611			},
    612		},
    613	}, {
    614		.id = TEGRA194_MEMORY_CLIENT_NVDISPLAYR1,
    615		.name = "nvdisplayr1",
    616		.sid = TEGRA194_SID_NVDISPLAY,
    617		.regs = {
    618			.sid = {
    619				.override = 0x508,
    620				.security = 0x50c,
    621			},
    622		},
    623	}, {
    624		.id = TEGRA194_MEMORY_CLIENT_VICSRD1,
    625		.name = "vicsrd1",
    626		.sid = TEGRA194_SID_VIC,
    627		.regs = {
    628			.sid = {
    629				.override = 0x510,
    630				.security = 0x514,
    631			},
    632		},
    633	}, {
    634		.id = TEGRA194_MEMORY_CLIENT_NVDECSRD1,
    635		.name = "nvdecsrd1",
    636		.sid = TEGRA194_SID_NVDEC,
    637		.regs = {
    638			.sid = {
    639				.override = 0x518,
    640				.security = 0x51c,
    641			},
    642		},
    643	}, {
    644		.id = TEGRA194_MEMORY_CLIENT_MIU0R,
    645		.name = "miu0r",
    646		.sid = TEGRA194_SID_MIU,
    647		.regs = {
    648			.sid = {
    649				.override = 0x530,
    650				.security = 0x534,
    651			},
    652		},
    653	}, {
    654		.name = "miu0w",
    655		.id = TEGRA194_MEMORY_CLIENT_MIU0W,
    656		.sid = TEGRA194_SID_MIU,
    657		.regs = {
    658			.sid = {
    659				.override = 0x538,
    660				.security = 0x53c,
    661			},
    662		},
    663	}, {
    664		.id = TEGRA194_MEMORY_CLIENT_MIU1R,
    665		.name = "miu1r",
    666		.sid = TEGRA194_SID_MIU,
    667		.regs = {
    668			.sid = {
    669				.override = 0x540,
    670				.security = 0x544,
    671			},
    672		},
    673	}, {
    674		.id = TEGRA194_MEMORY_CLIENT_MIU1W,
    675		.name = "miu1w",
    676		.sid = TEGRA194_SID_MIU,
    677		.regs = {
    678			.sid = {
    679				.override = 0x548,
    680				.security = 0x54c,
    681			},
    682		},
    683	}, {
    684		.id = TEGRA194_MEMORY_CLIENT_MIU2R,
    685		.name = "miu2r",
    686		.sid = TEGRA194_SID_MIU,
    687		.regs = {
    688			.sid = {
    689				.override = 0x570,
    690				.security = 0x574,
    691			},
    692		},
    693	}, {
    694		.id = TEGRA194_MEMORY_CLIENT_MIU2W,
    695		.name = "miu2w",
    696		.sid = TEGRA194_SID_MIU,
    697		.regs = {
    698			.sid = {
    699				.override = 0x578,
    700				.security = 0x57c,
    701			},
    702		},
    703	}, {
    704		.id = TEGRA194_MEMORY_CLIENT_MIU3R,
    705		.name = "miu3r",
    706		.sid = TEGRA194_SID_MIU,
    707		.regs = {
    708			.sid = {
    709				.override = 0x580,
    710				.security = 0x584,
    711			},
    712		},
    713	}, {
    714		.id = TEGRA194_MEMORY_CLIENT_MIU3W,
    715		.name = "miu3w",
    716		.sid = TEGRA194_SID_MIU,
    717		.regs = {
    718			.sid = {
    719				.override = 0x588,
    720				.security = 0x58c,
    721			},
    722		},
    723	}, {
    724		.id = TEGRA194_MEMORY_CLIENT_MIU4R,
    725		.name = "miu4r",
    726		.sid = TEGRA194_SID_MIU,
    727		.regs = {
    728			.sid = {
    729				.override = 0x590,
    730				.security = 0x594,
    731			},
    732		},
    733	}, {
    734		.id = TEGRA194_MEMORY_CLIENT_MIU4W,
    735		.name = "miu4w",
    736		.sid = TEGRA194_SID_MIU,
    737		.regs = {
    738			.sid = {
    739				.override = 0x598,
    740				.security = 0x59c,
    741			},
    742		},
    743	}, {
    744		.id = TEGRA194_MEMORY_CLIENT_DPMUR,
    745		.name = "dpmur",
    746		.sid = TEGRA194_SID_PASSTHROUGH,
    747		.regs = {
    748			.sid = {
    749				.override = 0x598,
    750				.security = 0x59c,
    751			},
    752		},
    753	}, {
    754		.id = TEGRA194_MEMORY_CLIENT_VIFALR,
    755		.name = "vifalr",
    756		.sid = TEGRA194_SID_VI_FALCON,
    757		.regs = {
    758			.sid = {
    759				.override = 0x5e0,
    760				.security = 0x5e4,
    761			},
    762		},
    763	}, {
    764		.id = TEGRA194_MEMORY_CLIENT_VIFALW,
    765		.name = "vifalw",
    766		.sid = TEGRA194_SID_VI_FALCON,
    767		.regs = {
    768			.sid = {
    769				.override = 0x5e8,
    770				.security = 0x5ec,
    771			},
    772		},
    773	}, {
    774		.id = TEGRA194_MEMORY_CLIENT_DLA0RDA,
    775		.name = "dla0rda",
    776		.sid = TEGRA194_SID_NVDLA0,
    777		.regs = {
    778			.sid = {
    779				.override = 0x5f0,
    780				.security = 0x5f4,
    781			},
    782		},
    783	}, {
    784		.id = TEGRA194_MEMORY_CLIENT_DLA0FALRDB,
    785		.name = "dla0falrdb",
    786		.sid = TEGRA194_SID_NVDLA0,
    787		.regs = {
    788			.sid = {
    789				.override = 0x5f8,
    790				.security = 0x5fc,
    791			},
    792		},
    793	}, {
    794		.id = TEGRA194_MEMORY_CLIENT_DLA0WRA,
    795		.name = "dla0wra",
    796		.sid = TEGRA194_SID_NVDLA0,
    797		.regs = {
    798			.sid = {
    799				.override = 0x600,
    800				.security = 0x604,
    801			},
    802		},
    803	}, {
    804		.id = TEGRA194_MEMORY_CLIENT_DLA0FALWRB,
    805		.name = "dla0falwrb",
    806		.sid = TEGRA194_SID_NVDLA0,
    807		.regs = {
    808			.sid = {
    809				.override = 0x608,
    810				.security = 0x60c,
    811			},
    812		},
    813	}, {
    814		.id = TEGRA194_MEMORY_CLIENT_DLA1RDA,
    815		.name = "dla1rda",
    816		.sid = TEGRA194_SID_NVDLA1,
    817		.regs = {
    818			.sid = {
    819				.override = 0x610,
    820				.security = 0x614,
    821			},
    822		},
    823	}, {
    824		.id = TEGRA194_MEMORY_CLIENT_DLA1FALRDB,
    825		.name = "dla1falrdb",
    826		.sid = TEGRA194_SID_NVDLA1,
    827		.regs = {
    828			.sid = {
    829				.override = 0x618,
    830				.security = 0x61c,
    831			},
    832		},
    833	}, {
    834		.id = TEGRA194_MEMORY_CLIENT_DLA1WRA,
    835		.name = "dla1wra",
    836		.sid = TEGRA194_SID_NVDLA1,
    837		.regs = {
    838			.sid = {
    839				.override = 0x620,
    840				.security = 0x624,
    841			},
    842		},
    843	}, {
    844		.id = TEGRA194_MEMORY_CLIENT_DLA1FALWRB,
    845		.name = "dla1falwrb",
    846		.sid = TEGRA194_SID_NVDLA1,
    847		.regs = {
    848			.sid = {
    849				.override = 0x628,
    850				.security = 0x62c,
    851			},
    852		},
    853	}, {
    854		.id = TEGRA194_MEMORY_CLIENT_PVA0RDA,
    855		.name = "pva0rda",
    856		.sid = TEGRA194_SID_PVA0,
    857		.regs = {
    858			.sid = {
    859				.override = 0x630,
    860				.security = 0x634,
    861			},
    862		},
    863	}, {
    864		.id = TEGRA194_MEMORY_CLIENT_PVA0RDB,
    865		.name = "pva0rdb",
    866		.sid = TEGRA194_SID_PVA0,
    867		.regs = {
    868			.sid = {
    869				.override = 0x638,
    870				.security = 0x63c,
    871			},
    872		},
    873	}, {
    874		.id = TEGRA194_MEMORY_CLIENT_PVA0RDC,
    875		.name = "pva0rdc",
    876		.sid = TEGRA194_SID_PVA0,
    877		.regs = {
    878			.sid = {
    879				.override = 0x640,
    880				.security = 0x644,
    881			},
    882		},
    883	}, {
    884		.id = TEGRA194_MEMORY_CLIENT_PVA0WRA,
    885		.name = "pva0wra",
    886		.sid = TEGRA194_SID_PVA0,
    887		.regs = {
    888			.sid = {
    889				.override = 0x648,
    890				.security = 0x64c,
    891			},
    892		},
    893	}, {
    894		.id = TEGRA194_MEMORY_CLIENT_PVA0WRB,
    895		.name = "pva0wrb",
    896		.sid = TEGRA194_SID_PVA0,
    897		.regs = {
    898			.sid = {
    899				.override = 0x650,
    900				.security = 0x654,
    901			},
    902		},
    903	}, {
    904		.id = TEGRA194_MEMORY_CLIENT_PVA0WRC,
    905		.name = "pva0wrc",
    906		.sid = TEGRA194_SID_PVA0,
    907		.regs = {
    908			.sid = {
    909				.override = 0x658,
    910				.security = 0x65c,
    911			},
    912		},
    913	}, {
    914		.id = TEGRA194_MEMORY_CLIENT_PVA1RDA,
    915		.name = "pva1rda",
    916		.sid = TEGRA194_SID_PVA1,
    917		.regs = {
    918			.sid = {
    919				.override = 0x660,
    920				.security = 0x664,
    921			},
    922		},
    923	}, {
    924		.id = TEGRA194_MEMORY_CLIENT_PVA1RDB,
    925		.name = "pva1rdb",
    926		.sid = TEGRA194_SID_PVA1,
    927		.regs = {
    928			.sid = {
    929				.override = 0x668,
    930				.security = 0x66c,
    931			},
    932		},
    933	}, {
    934		.id = TEGRA194_MEMORY_CLIENT_PVA1RDC,
    935		.name = "pva1rdc",
    936		.sid = TEGRA194_SID_PVA1,
    937		.regs = {
    938			.sid = {
    939				.override = 0x670,
    940				.security = 0x674,
    941			},
    942		},
    943	}, {
    944		.id = TEGRA194_MEMORY_CLIENT_PVA1WRA,
    945		.name = "pva1wra",
    946		.sid = TEGRA194_SID_PVA1,
    947		.regs = {
    948			.sid = {
    949				.override = 0x678,
    950				.security = 0x67c,
    951			},
    952		},
    953	}, {
    954		.id = TEGRA194_MEMORY_CLIENT_PVA1WRB,
    955		.name = "pva1wrb",
    956		.sid = TEGRA194_SID_PVA1,
    957		.regs = {
    958			.sid = {
    959				.override = 0x680,
    960				.security = 0x684,
    961			},
    962		},
    963	}, {
    964		.id = TEGRA194_MEMORY_CLIENT_PVA1WRC,
    965		.name = "pva1wrc",
    966		.sid = TEGRA194_SID_PVA1,
    967		.regs = {
    968			.sid = {
    969				.override = 0x688,
    970				.security = 0x68c,
    971			},
    972		},
    973	}, {
    974		.id = TEGRA194_MEMORY_CLIENT_RCER,
    975		.name = "rcer",
    976		.sid = TEGRA194_SID_RCE,
    977		.regs = {
    978			.sid = {
    979				.override = 0x690,
    980				.security = 0x694,
    981			},
    982		},
    983	}, {
    984		.id = TEGRA194_MEMORY_CLIENT_RCEW,
    985		.name = "rcew",
    986		.sid = TEGRA194_SID_RCE,
    987		.regs = {
    988			.sid = {
    989				.override = 0x698,
    990				.security = 0x69c,
    991			},
    992		},
    993	}, {
    994		.id = TEGRA194_MEMORY_CLIENT_RCEDMAR,
    995		.name = "rcedmar",
    996		.sid = TEGRA194_SID_RCE,
    997		.regs = {
    998			.sid = {
    999				.override = 0x6a0,
   1000				.security = 0x6a4,
   1001			},
   1002		},
   1003	}, {
   1004		.id = TEGRA194_MEMORY_CLIENT_RCEDMAW,
   1005		.name = "rcedmaw",
   1006		.sid = TEGRA194_SID_RCE,
   1007		.regs = {
   1008			.sid = {
   1009				.override = 0x6a8,
   1010				.security = 0x6ac,
   1011			},
   1012		},
   1013	}, {
   1014		.id = TEGRA194_MEMORY_CLIENT_NVENC1SRD,
   1015		.name = "nvenc1srd",
   1016		.sid = TEGRA194_SID_NVENC1,
   1017		.regs = {
   1018			.sid = {
   1019				.override = 0x6b0,
   1020				.security = 0x6b4,
   1021			},
   1022		},
   1023	}, {
   1024		.id = TEGRA194_MEMORY_CLIENT_NVENC1SWR,
   1025		.name = "nvenc1swr",
   1026		.sid = TEGRA194_SID_NVENC1,
   1027		.regs = {
   1028			.sid = {
   1029				.override = 0x6b8,
   1030				.security = 0x6bc,
   1031			},
   1032		},
   1033	}, {
   1034		.id = TEGRA194_MEMORY_CLIENT_PCIE0R,
   1035		.name = "pcie0r",
   1036		.sid = TEGRA194_SID_PCIE0,
   1037		.regs = {
   1038			.sid = {
   1039				.override = 0x6c0,
   1040				.security = 0x6c4,
   1041			},
   1042		},
   1043	}, {
   1044		.id = TEGRA194_MEMORY_CLIENT_PCIE0W,
   1045		.name = "pcie0w",
   1046		.sid = TEGRA194_SID_PCIE0,
   1047		.regs = {
   1048			.sid = {
   1049				.override = 0x6c8,
   1050				.security = 0x6cc,
   1051			},
   1052		},
   1053	}, {
   1054		.id = TEGRA194_MEMORY_CLIENT_PCIE1R,
   1055		.name = "pcie1r",
   1056		.sid = TEGRA194_SID_PCIE1,
   1057		.regs = {
   1058			.sid = {
   1059				.override = 0x6d0,
   1060				.security = 0x6d4,
   1061			},
   1062		},
   1063	}, {
   1064		.id = TEGRA194_MEMORY_CLIENT_PCIE1W,
   1065		.name = "pcie1w",
   1066		.sid = TEGRA194_SID_PCIE1,
   1067		.regs = {
   1068			.sid = {
   1069				.override = 0x6d8,
   1070				.security = 0x6dc,
   1071			},
   1072		},
   1073	}, {
   1074		.id = TEGRA194_MEMORY_CLIENT_PCIE2AR,
   1075		.name = "pcie2ar",
   1076		.sid = TEGRA194_SID_PCIE2,
   1077		.regs = {
   1078			.sid = {
   1079				.override = 0x6e0,
   1080				.security = 0x6e4,
   1081			},
   1082		},
   1083	}, {
   1084		.id = TEGRA194_MEMORY_CLIENT_PCIE2AW,
   1085		.name = "pcie2aw",
   1086		.sid = TEGRA194_SID_PCIE2,
   1087		.regs = {
   1088			.sid = {
   1089				.override = 0x6e8,
   1090				.security = 0x6ec,
   1091			},
   1092		},
   1093	}, {
   1094		.id = TEGRA194_MEMORY_CLIENT_PCIE3R,
   1095		.name = "pcie3r",
   1096		.sid = TEGRA194_SID_PCIE3,
   1097		.regs = {
   1098			.sid = {
   1099				.override = 0x6f0,
   1100				.security = 0x6f4,
   1101			},
   1102		},
   1103	}, {
   1104		.id = TEGRA194_MEMORY_CLIENT_PCIE3W,
   1105		.name = "pcie3w",
   1106		.sid = TEGRA194_SID_PCIE3,
   1107		.regs = {
   1108			.sid = {
   1109				.override = 0x6f8,
   1110				.security = 0x6fc,
   1111			},
   1112		},
   1113	}, {
   1114		.id = TEGRA194_MEMORY_CLIENT_PCIE4R,
   1115		.name = "pcie4r",
   1116		.sid = TEGRA194_SID_PCIE4,
   1117		.regs = {
   1118			.sid = {
   1119				.override = 0x700,
   1120				.security = 0x704,
   1121			},
   1122		},
   1123	}, {
   1124		.id = TEGRA194_MEMORY_CLIENT_PCIE4W,
   1125		.name = "pcie4w",
   1126		.sid = TEGRA194_SID_PCIE4,
   1127		.regs = {
   1128			.sid = {
   1129				.override = 0x708,
   1130				.security = 0x70c,
   1131			},
   1132		},
   1133	}, {
   1134		.id = TEGRA194_MEMORY_CLIENT_PCIE5R,
   1135		.name = "pcie5r",
   1136		.sid = TEGRA194_SID_PCIE5,
   1137		.regs = {
   1138			.sid = {
   1139				.override = 0x710,
   1140				.security = 0x714,
   1141			},
   1142		},
   1143	}, {
   1144		.id = TEGRA194_MEMORY_CLIENT_PCIE5W,
   1145		.name = "pcie5w",
   1146		.sid = TEGRA194_SID_PCIE5,
   1147		.regs = {
   1148			.sid = {
   1149				.override = 0x718,
   1150				.security = 0x71c,
   1151			},
   1152		},
   1153	}, {
   1154		.id = TEGRA194_MEMORY_CLIENT_ISPFALW,
   1155		.name = "ispfalw",
   1156		.sid = TEGRA194_SID_ISP_FALCON,
   1157		.regs = {
   1158			.sid = {
   1159				.override = 0x720,
   1160				.security = 0x724,
   1161			},
   1162		},
   1163	}, {
   1164		.id = TEGRA194_MEMORY_CLIENT_DLA0RDA1,
   1165		.name = "dla0rda1",
   1166		.sid = TEGRA194_SID_NVDLA0,
   1167		.regs = {
   1168			.sid = {
   1169				.override = 0x748,
   1170				.security = 0x74c,
   1171			},
   1172		},
   1173	}, {
   1174		.id = TEGRA194_MEMORY_CLIENT_DLA1RDA1,
   1175		.name = "dla1rda1",
   1176		.sid = TEGRA194_SID_NVDLA1,
   1177		.regs = {
   1178			.sid = {
   1179				.override = 0x750,
   1180				.security = 0x754,
   1181			},
   1182		},
   1183	}, {
   1184		.id = TEGRA194_MEMORY_CLIENT_PVA0RDA1,
   1185		.name = "pva0rda1",
   1186		.sid = TEGRA194_SID_PVA0,
   1187		.regs = {
   1188			.sid = {
   1189				.override = 0x758,
   1190				.security = 0x75c,
   1191			},
   1192		},
   1193	}, {
   1194		.id = TEGRA194_MEMORY_CLIENT_PVA0RDB1,
   1195		.name = "pva0rdb1",
   1196		.sid = TEGRA194_SID_PVA0,
   1197		.regs = {
   1198			.sid = {
   1199				.override = 0x760,
   1200				.security = 0x764,
   1201			},
   1202		},
   1203	}, {
   1204		.id = TEGRA194_MEMORY_CLIENT_PVA1RDA1,
   1205		.name = "pva1rda1",
   1206		.sid = TEGRA194_SID_PVA1,
   1207		.regs = {
   1208			.sid = {
   1209				.override = 0x768,
   1210				.security = 0x76c,
   1211			},
   1212		},
   1213	}, {
   1214		.id = TEGRA194_MEMORY_CLIENT_PVA1RDB1,
   1215		.name = "pva1rdb1",
   1216		.sid = TEGRA194_SID_PVA1,
   1217		.regs = {
   1218			.sid = {
   1219				.override = 0x770,
   1220				.security = 0x774,
   1221			},
   1222		},
   1223	}, {
   1224		.id = TEGRA194_MEMORY_CLIENT_PCIE5R1,
   1225		.name = "pcie5r1",
   1226		.sid = TEGRA194_SID_PCIE5,
   1227		.regs = {
   1228			.sid = {
   1229				.override = 0x778,
   1230				.security = 0x77c,
   1231			},
   1232		},
   1233	}, {
   1234		.id = TEGRA194_MEMORY_CLIENT_NVENCSRD1,
   1235		.name = "nvencsrd1",
   1236		.sid = TEGRA194_SID_NVENC,
   1237		.regs = {
   1238			.sid = {
   1239				.override = 0x780,
   1240				.security = 0x784,
   1241			},
   1242		},
   1243	}, {
   1244		.id = TEGRA194_MEMORY_CLIENT_NVENC1SRD1,
   1245		.name = "nvenc1srd1",
   1246		.sid = TEGRA194_SID_NVENC1,
   1247		.regs = {
   1248			.sid = {
   1249				.override = 0x788,
   1250				.security = 0x78c,
   1251			},
   1252		},
   1253	}, {
   1254		.id = TEGRA194_MEMORY_CLIENT_ISPRA1,
   1255		.name = "ispra1",
   1256		.sid = TEGRA194_SID_ISP,
   1257		.regs = {
   1258			.sid = {
   1259				.override = 0x790,
   1260				.security = 0x794,
   1261			},
   1262		},
   1263	}, {
   1264		.id = TEGRA194_MEMORY_CLIENT_PCIE0R1,
   1265		.name = "pcie0r1",
   1266		.sid = TEGRA194_SID_PCIE0,
   1267		.regs = {
   1268			.sid = {
   1269				.override = 0x798,
   1270				.security = 0x79c,
   1271			},
   1272		},
   1273	}, {
   1274		.id = TEGRA194_MEMORY_CLIENT_NVDEC1SRD,
   1275		.name = "nvdec1srd",
   1276		.sid = TEGRA194_SID_NVDEC1,
   1277		.regs = {
   1278			.sid = {
   1279				.override = 0x7c8,
   1280				.security = 0x7cc,
   1281			},
   1282		},
   1283	}, {
   1284		.id = TEGRA194_MEMORY_CLIENT_NVDEC1SRD1,
   1285		.name = "nvdec1srd1",
   1286		.sid = TEGRA194_SID_NVDEC1,
   1287		.regs = {
   1288			.sid = {
   1289				.override = 0x7d0,
   1290				.security = 0x7d4,
   1291			},
   1292		},
   1293	}, {
   1294		.id = TEGRA194_MEMORY_CLIENT_NVDEC1SWR,
   1295		.name = "nvdec1swr",
   1296		.sid = TEGRA194_SID_NVDEC1,
   1297		.regs = {
   1298			.sid = {
   1299				.override = 0x7d8,
   1300				.security = 0x7dc,
   1301			},
   1302		},
   1303	}, {
   1304		.id = TEGRA194_MEMORY_CLIENT_MIU5R,
   1305		.name = "miu5r",
   1306		.sid = TEGRA194_SID_MIU,
   1307		.regs = {
   1308			.sid = {
   1309				.override = 0x7e0,
   1310				.security = 0x7e4,
   1311			},
   1312		},
   1313	}, {
   1314		.id = TEGRA194_MEMORY_CLIENT_MIU5W,
   1315		.name = "miu5w",
   1316		.sid = TEGRA194_SID_MIU,
   1317		.regs = {
   1318			.sid = {
   1319				.override = 0x7e8,
   1320				.security = 0x7ec,
   1321			},
   1322		},
   1323	}, {
   1324		.id = TEGRA194_MEMORY_CLIENT_MIU6R,
   1325		.name = "miu6r",
   1326		.sid = TEGRA194_SID_MIU,
   1327		.regs = {
   1328			.sid = {
   1329				.override = 0x7f0,
   1330				.security = 0x7f4,
   1331			},
   1332		},
   1333	}, {
   1334		.id = TEGRA194_MEMORY_CLIENT_MIU6W,
   1335		.name = "miu6w",
   1336		.sid = TEGRA194_SID_MIU,
   1337		.regs = {
   1338			.sid = {
   1339				.override = 0x7f8,
   1340				.security = 0x7fc,
   1341			},
   1342		},
   1343	},
   1344};
   1345
   1346const struct tegra_mc_soc tegra194_mc_soc = {
   1347	.num_clients = ARRAY_SIZE(tegra194_mc_clients),
   1348	.clients = tegra194_mc_clients,
   1349	.num_address_bits = 40,
   1350	.num_channels = 16,
   1351	.client_id_mask = 0xff,
   1352	.intmask = MC_INT_DECERR_ROUTE_SANITY |
   1353		   MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS |
   1354		   MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
   1355		   MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
   1356	.has_addr_hi_reg = true,
   1357	.ops = &tegra186_mc_ops,
   1358	.ch_intmask = 0x00000f00,
   1359	.global_intstatus_channel_shift = 8,
   1360};