exynos-lpass.c (5280B)
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2015 - 2016 Samsung Electronics Co., Ltd. 4 * 5 * Authors: Inha Song <ideal.song@samsung.com> 6 * Sylwester Nawrocki <s.nawrocki@samsung.com> 7 * 8 * Samsung Exynos SoC series Low Power Audio Subsystem driver. 9 * 10 * This module provides regmap for the Top SFR region and instantiates 11 * devices for IP blocks like DMAC, I2S, UART. 12 */ 13 14#include <linux/clk.h> 15#include <linux/delay.h> 16#include <linux/io.h> 17#include <linux/module.h> 18#include <linux/of.h> 19#include <linux/of_platform.h> 20#include <linux/platform_device.h> 21#include <linux/pm_runtime.h> 22#include <linux/regmap.h> 23#include <linux/soc/samsung/exynos-regs-pmu.h> 24#include <linux/types.h> 25 26/* LPASS Top register definitions */ 27#define SFR_LPASS_CORE_SW_RESET 0x08 28#define LPASS_SB_SW_RESET BIT(11) 29#define LPASS_UART_SW_RESET BIT(10) 30#define LPASS_PCM_SW_RESET BIT(9) 31#define LPASS_I2S_SW_RESET BIT(8) 32#define LPASS_WDT1_SW_RESET BIT(4) 33#define LPASS_WDT0_SW_RESET BIT(3) 34#define LPASS_TIMER_SW_RESET BIT(2) 35#define LPASS_MEM_SW_RESET BIT(1) 36#define LPASS_DMA_SW_RESET BIT(0) 37 38#define SFR_LPASS_INTR_CA5_MASK 0x48 39#define SFR_LPASS_INTR_CPU_MASK 0x58 40#define LPASS_INTR_APM BIT(9) 41#define LPASS_INTR_MIF BIT(8) 42#define LPASS_INTR_TIMER BIT(7) 43#define LPASS_INTR_DMA BIT(6) 44#define LPASS_INTR_GPIO BIT(5) 45#define LPASS_INTR_I2S BIT(4) 46#define LPASS_INTR_PCM BIT(3) 47#define LPASS_INTR_SLIMBUS BIT(2) 48#define LPASS_INTR_UART BIT(1) 49#define LPASS_INTR_SFR BIT(0) 50 51struct exynos_lpass { 52 /* pointer to the LPASS TOP regmap */ 53 struct regmap *top; 54 struct clk *sfr0_clk; 55}; 56 57static void exynos_lpass_core_sw_reset(struct exynos_lpass *lpass, int mask) 58{ 59 unsigned int val = 0; 60 61 regmap_read(lpass->top, SFR_LPASS_CORE_SW_RESET, &val); 62 63 val &= ~mask; 64 regmap_write(lpass->top, SFR_LPASS_CORE_SW_RESET, val); 65 66 usleep_range(100, 150); 67 68 val |= mask; 69 regmap_write(lpass->top, SFR_LPASS_CORE_SW_RESET, val); 70} 71 72static void exynos_lpass_enable(struct exynos_lpass *lpass) 73{ 74 clk_prepare_enable(lpass->sfr0_clk); 75 76 /* Unmask SFR, DMA and I2S interrupt */ 77 regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK, 78 LPASS_INTR_SFR | LPASS_INTR_DMA | LPASS_INTR_I2S); 79 80 regmap_write(lpass->top, SFR_LPASS_INTR_CPU_MASK, 81 LPASS_INTR_SFR | LPASS_INTR_DMA | LPASS_INTR_I2S | 82 LPASS_INTR_UART); 83 84 exynos_lpass_core_sw_reset(lpass, LPASS_I2S_SW_RESET); 85 exynos_lpass_core_sw_reset(lpass, LPASS_DMA_SW_RESET); 86 exynos_lpass_core_sw_reset(lpass, LPASS_MEM_SW_RESET); 87 exynos_lpass_core_sw_reset(lpass, LPASS_UART_SW_RESET); 88} 89 90static void exynos_lpass_disable(struct exynos_lpass *lpass) 91{ 92 /* Mask any unmasked IP interrupt sources */ 93 regmap_write(lpass->top, SFR_LPASS_INTR_CPU_MASK, 0); 94 regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK, 0); 95 96 clk_disable_unprepare(lpass->sfr0_clk); 97} 98 99static const struct regmap_config exynos_lpass_reg_conf = { 100 .reg_bits = 32, 101 .reg_stride = 4, 102 .val_bits = 32, 103 .max_register = 0xfc, 104 .fast_io = true, 105}; 106 107static int exynos_lpass_probe(struct platform_device *pdev) 108{ 109 struct device *dev = &pdev->dev; 110 struct exynos_lpass *lpass; 111 void __iomem *base_top; 112 struct resource *res; 113 114 lpass = devm_kzalloc(dev, sizeof(*lpass), GFP_KERNEL); 115 if (!lpass) 116 return -ENOMEM; 117 118 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 119 base_top = devm_ioremap_resource(dev, res); 120 if (IS_ERR(base_top)) 121 return PTR_ERR(base_top); 122 123 lpass->sfr0_clk = devm_clk_get(dev, "sfr0_ctrl"); 124 if (IS_ERR(lpass->sfr0_clk)) 125 return PTR_ERR(lpass->sfr0_clk); 126 127 lpass->top = regmap_init_mmio(dev, base_top, 128 &exynos_lpass_reg_conf); 129 if (IS_ERR(lpass->top)) { 130 dev_err(dev, "LPASS top regmap initialization failed\n"); 131 return PTR_ERR(lpass->top); 132 } 133 134 platform_set_drvdata(pdev, lpass); 135 pm_runtime_set_active(dev); 136 pm_runtime_enable(dev); 137 exynos_lpass_enable(lpass); 138 139 return devm_of_platform_populate(dev); 140} 141 142static int exynos_lpass_remove(struct platform_device *pdev) 143{ 144 struct exynos_lpass *lpass = platform_get_drvdata(pdev); 145 146 exynos_lpass_disable(lpass); 147 pm_runtime_disable(&pdev->dev); 148 if (!pm_runtime_status_suspended(&pdev->dev)) 149 exynos_lpass_disable(lpass); 150 regmap_exit(lpass->top); 151 152 return 0; 153} 154 155static int __maybe_unused exynos_lpass_suspend(struct device *dev) 156{ 157 struct exynos_lpass *lpass = dev_get_drvdata(dev); 158 159 exynos_lpass_disable(lpass); 160 161 return 0; 162} 163 164static int __maybe_unused exynos_lpass_resume(struct device *dev) 165{ 166 struct exynos_lpass *lpass = dev_get_drvdata(dev); 167 168 exynos_lpass_enable(lpass); 169 170 return 0; 171} 172 173static const struct dev_pm_ops lpass_pm_ops = { 174 SET_RUNTIME_PM_OPS(exynos_lpass_suspend, exynos_lpass_resume, NULL) 175 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 176 pm_runtime_force_resume) 177}; 178 179static const struct of_device_id exynos_lpass_of_match[] = { 180 { .compatible = "samsung,exynos5433-lpass" }, 181 { }, 182}; 183MODULE_DEVICE_TABLE(of, exynos_lpass_of_match); 184 185static struct platform_driver exynos_lpass_driver = { 186 .driver = { 187 .name = "exynos-lpass", 188 .pm = &lpass_pm_ops, 189 .of_match_table = exynos_lpass_of_match, 190 }, 191 .probe = exynos_lpass_probe, 192 .remove = exynos_lpass_remove, 193}; 194module_platform_driver(exynos_lpass_driver); 195 196MODULE_DESCRIPTION("Samsung Low Power Audio Subsystem driver"); 197MODULE_LICENSE("GPL v2");