cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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rts5261.c (23705B)


      1// SPDX-License-Identifier: GPL-2.0-or-later
      2/* Driver for Realtek PCI-Express card reader
      3 *
      4 * Copyright(c) 2018-2019 Realtek Semiconductor Corp. All rights reserved.
      5 *
      6 * Author:
      7 *   Rui FENG <rui_feng@realsil.com.cn>
      8 *   Wei WANG <wei_wang@realsil.com.cn>
      9 */
     10
     11#include <linux/module.h>
     12#include <linux/delay.h>
     13#include <linux/rtsx_pci.h>
     14
     15#include "rts5261.h"
     16#include "rtsx_pcr.h"
     17
     18static u8 rts5261_get_ic_version(struct rtsx_pcr *pcr)
     19{
     20	u8 val;
     21
     22	rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
     23	return val & IC_VERSION_MASK;
     24}
     25
     26static void rts5261_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
     27{
     28	u8 driving_3v3[4][3] = {
     29		{0x96, 0x96, 0x96},
     30		{0x96, 0x96, 0x96},
     31		{0x7F, 0x7F, 0x7F},
     32		{0x13, 0x13, 0x13},
     33	};
     34	u8 driving_1v8[4][3] = {
     35		{0xB3, 0xB3, 0xB3},
     36		{0x3A, 0x3A, 0x3A},
     37		{0xE6, 0xE6, 0xE6},
     38		{0x99, 0x99, 0x99},
     39	};
     40	u8 (*driving)[3], drive_sel;
     41
     42	if (voltage == OUTPUT_3V3) {
     43		driving = driving_3v3;
     44		drive_sel = pcr->sd30_drive_sel_3v3;
     45	} else {
     46		driving = driving_1v8;
     47		drive_sel = pcr->sd30_drive_sel_1v8;
     48	}
     49
     50	rtsx_pci_write_register(pcr, SD30_CLK_DRIVE_SEL,
     51			 0xFF, driving[drive_sel][0]);
     52
     53	rtsx_pci_write_register(pcr, SD30_CMD_DRIVE_SEL,
     54			 0xFF, driving[drive_sel][1]);
     55
     56	rtsx_pci_write_register(pcr, SD30_DAT_DRIVE_SEL,
     57			 0xFF, driving[drive_sel][2]);
     58}
     59
     60static void rts5261_force_power_down(struct rtsx_pcr *pcr, u8 pm_state, bool runtime)
     61{
     62	/* Set relink_time to 0 */
     63	rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0);
     64	rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0);
     65	rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3,
     66				RELINK_TIME_MASK, 0);
     67
     68	if (pm_state == HOST_ENTER_S3)
     69		rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3,
     70					D3_DELINK_MODE_EN, D3_DELINK_MODE_EN);
     71
     72	if (!runtime) {
     73		rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG1,
     74				CD_RESUME_EN_MASK, 0);
     75		rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x00);
     76		rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
     77				FORCE_PM_CONTROL | FORCE_PM_VALUE, FORCE_PM_CONTROL);
     78
     79	} else {
     80		rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
     81				FORCE_PM_CONTROL | FORCE_PM_VALUE, 0);
     82
     83		rtsx_pci_write_register(pcr, RTS5261_FW_CTL,
     84				RTS5261_INFORM_RTD3_COLD, RTS5261_INFORM_RTD3_COLD);
     85		rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG4,
     86				RTS5261_FORCE_PRSNT_LOW, RTS5261_FORCE_PRSNT_LOW);
     87
     88	}
     89
     90	rtsx_pci_write_register(pcr, RTS5261_REG_FPDCTL,
     91		SSC_POWER_DOWN, SSC_POWER_DOWN);
     92}
     93
     94static int rts5261_enable_auto_blink(struct rtsx_pcr *pcr)
     95{
     96	return rtsx_pci_write_register(pcr, OLT_LED_CTL,
     97		LED_SHINE_MASK, LED_SHINE_EN);
     98}
     99
    100static int rts5261_disable_auto_blink(struct rtsx_pcr *pcr)
    101{
    102	return rtsx_pci_write_register(pcr, OLT_LED_CTL,
    103		LED_SHINE_MASK, LED_SHINE_DISABLE);
    104}
    105
    106static int rts5261_turn_on_led(struct rtsx_pcr *pcr)
    107{
    108	return rtsx_pci_write_register(pcr, GPIO_CTL,
    109		0x02, 0x02);
    110}
    111
    112static int rts5261_turn_off_led(struct rtsx_pcr *pcr)
    113{
    114	return rtsx_pci_write_register(pcr, GPIO_CTL,
    115		0x02, 0x00);
    116}
    117
    118/* SD Pull Control Enable:
    119 *     SD_DAT[3:0] ==> pull up
    120 *     SD_CD       ==> pull up
    121 *     SD_WP       ==> pull up
    122 *     SD_CMD      ==> pull up
    123 *     SD_CLK      ==> pull down
    124 */
    125static const u32 rts5261_sd_pull_ctl_enable_tbl[] = {
    126	RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
    127	RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
    128	0,
    129};
    130
    131/* SD Pull Control Disable:
    132 *     SD_DAT[3:0] ==> pull down
    133 *     SD_CD       ==> pull up
    134 *     SD_WP       ==> pull down
    135 *     SD_CMD      ==> pull down
    136 *     SD_CLK      ==> pull down
    137 */
    138static const u32 rts5261_sd_pull_ctl_disable_tbl[] = {
    139	RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
    140	RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
    141	0,
    142};
    143
    144static int rts5261_sd_set_sample_push_timing_sd30(struct rtsx_pcr *pcr)
    145{
    146	rtsx_pci_write_register(pcr, SD_CFG1, SD_MODE_SELECT_MASK
    147		| SD_ASYNC_FIFO_NOT_RST, SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
    148	rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ);
    149	rtsx_pci_write_register(pcr, CARD_CLK_SOURCE, 0xFF,
    150			CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
    151	rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
    152
    153	return 0;
    154}
    155
    156static int rts5261_card_power_on(struct rtsx_pcr *pcr, int card)
    157{
    158	struct rtsx_cr_option *option = &pcr->option;
    159
    160	if (option->ocp_en)
    161		rtsx_pci_enable_ocp(pcr);
    162
    163	rtsx_pci_write_register(pcr, REG_CRC_DUMMY_0,
    164		CFG_SD_POW_AUTO_PD, CFG_SD_POW_AUTO_PD);
    165
    166	rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG1,
    167			RTS5261_LDO1_TUNE_MASK, RTS5261_LDO1_33);
    168	rtsx_pci_write_register(pcr, RTS5261_LDO1233318_POW_CTL,
    169			RTS5261_LDO1_POWERON, RTS5261_LDO1_POWERON);
    170
    171	rtsx_pci_write_register(pcr, RTS5261_LDO1233318_POW_CTL,
    172			RTS5261_LDO3318_POWERON, RTS5261_LDO3318_POWERON);
    173
    174	msleep(20);
    175
    176	rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
    177
    178	/* Initialize SD_CFG1 register */
    179	rtsx_pci_write_register(pcr, SD_CFG1, 0xFF,
    180			SD_CLK_DIVIDE_128 | SD_20_MODE | SD_BUS_WIDTH_1BIT);
    181
    182	rtsx_pci_write_register(pcr, SD_SAMPLE_POINT_CTL,
    183			0xFF, SD20_RX_POS_EDGE);
    184	rtsx_pci_write_register(pcr, SD_PUSH_POINT_CTL, 0xFF, 0);
    185	rtsx_pci_write_register(pcr, CARD_STOP, SD_STOP | SD_CLR_ERR,
    186			SD_STOP | SD_CLR_ERR);
    187
    188	/* Reset SD_CFG3 register */
    189	rtsx_pci_write_register(pcr, SD_CFG3, SD30_CLK_END_EN, 0);
    190	rtsx_pci_write_register(pcr, REG_SD_STOP_SDCLK_CFG,
    191			SD30_CLK_STOP_CFG_EN | SD30_CLK_STOP_CFG1 |
    192			SD30_CLK_STOP_CFG0, 0);
    193
    194	if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50 ||
    195	    pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
    196		rts5261_sd_set_sample_push_timing_sd30(pcr);
    197
    198	return 0;
    199}
    200
    201static int rts5261_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
    202{
    203	int err;
    204	u16 val = 0;
    205
    206	rtsx_pci_write_register(pcr, RTS5261_CARD_PWR_CTL,
    207			RTS5261_PUPDC, RTS5261_PUPDC);
    208
    209	switch (voltage) {
    210	case OUTPUT_3V3:
    211		rtsx_pci_read_phy_register(pcr, PHY_TUNE, &val);
    212		val |= PHY_TUNE_SDBUS_33;
    213		err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, val);
    214		if (err < 0)
    215			return err;
    216
    217		rtsx_pci_write_register(pcr, RTS5261_DV3318_CFG,
    218				RTS5261_DV3318_TUNE_MASK, RTS5261_DV3318_33);
    219		rtsx_pci_write_register(pcr, SD_PAD_CTL,
    220				SD_IO_USING_1V8, 0);
    221		break;
    222	case OUTPUT_1V8:
    223		rtsx_pci_read_phy_register(pcr, PHY_TUNE, &val);
    224		val &= ~PHY_TUNE_SDBUS_33;
    225		err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, val);
    226		if (err < 0)
    227			return err;
    228
    229		rtsx_pci_write_register(pcr, RTS5261_DV3318_CFG,
    230				RTS5261_DV3318_TUNE_MASK, RTS5261_DV3318_18);
    231		rtsx_pci_write_register(pcr, SD_PAD_CTL,
    232				SD_IO_USING_1V8, SD_IO_USING_1V8);
    233		break;
    234	default:
    235		return -EINVAL;
    236	}
    237
    238	/* set pad drive */
    239	rts5261_fill_driving(pcr, voltage);
    240
    241	return 0;
    242}
    243
    244static void rts5261_stop_cmd(struct rtsx_pcr *pcr)
    245{
    246	rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
    247	rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
    248	rtsx_pci_write_register(pcr, RTS5260_DMA_RST_CTL_0,
    249				RTS5260_DMA_RST | RTS5260_ADMA3_RST,
    250				RTS5260_DMA_RST | RTS5260_ADMA3_RST);
    251	rtsx_pci_write_register(pcr, RBCTL, RB_FLUSH, RB_FLUSH);
    252}
    253
    254static void rts5261_card_before_power_off(struct rtsx_pcr *pcr)
    255{
    256	rts5261_stop_cmd(pcr);
    257	rts5261_switch_output_voltage(pcr, OUTPUT_3V3);
    258
    259}
    260
    261static void rts5261_enable_ocp(struct rtsx_pcr *pcr)
    262{
    263	u8 val = 0;
    264
    265	val = SD_OCP_INT_EN | SD_DETECT_EN;
    266	rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
    267			RTS5261_LDO1_OCP_EN | RTS5261_LDO1_OCP_LMT_EN,
    268			RTS5261_LDO1_OCP_EN | RTS5261_LDO1_OCP_LMT_EN);
    269	rtsx_pci_write_register(pcr, REG_OCPCTL, 0xFF, val);
    270
    271}
    272
    273static void rts5261_disable_ocp(struct rtsx_pcr *pcr)
    274{
    275	u8 mask = 0;
    276
    277	mask = SD_OCP_INT_EN | SD_DETECT_EN;
    278	rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
    279	rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
    280			RTS5261_LDO1_OCP_EN | RTS5261_LDO1_OCP_LMT_EN, 0);
    281
    282}
    283
    284static int rts5261_card_power_off(struct rtsx_pcr *pcr, int card)
    285{
    286	int err = 0;
    287
    288	rts5261_card_before_power_off(pcr);
    289	err = rtsx_pci_write_register(pcr, RTS5261_LDO1233318_POW_CTL,
    290				RTS5261_LDO_POWERON_MASK, 0);
    291
    292	rtsx_pci_write_register(pcr, REG_CRC_DUMMY_0,
    293		CFG_SD_POW_AUTO_PD, 0);
    294	if (pcr->option.ocp_en)
    295		rtsx_pci_disable_ocp(pcr);
    296
    297	return err;
    298}
    299
    300static void rts5261_init_ocp(struct rtsx_pcr *pcr)
    301{
    302	struct rtsx_cr_option *option = &pcr->option;
    303
    304	if (option->ocp_en) {
    305		u8 mask, val;
    306
    307		rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
    308			RTS5261_LDO1_OCP_EN | RTS5261_LDO1_OCP_LMT_EN,
    309			RTS5261_LDO1_OCP_EN | RTS5261_LDO1_OCP_LMT_EN);
    310
    311		rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
    312			RTS5261_LDO1_OCP_THD_MASK, option->sd_800mA_ocp_thd);
    313
    314		rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
    315			RTS5261_LDO1_OCP_LMT_THD_MASK,
    316			RTS5261_LDO1_LMT_THD_2000);
    317
    318		mask = SD_OCP_GLITCH_MASK;
    319		val = pcr->hw_param.ocp_glitch;
    320		rtsx_pci_write_register(pcr, REG_OCPGLITCH, mask, val);
    321
    322		rts5261_enable_ocp(pcr);
    323	} else {
    324		rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
    325			RTS5261_LDO1_OCP_EN | RTS5261_LDO1_OCP_LMT_EN, 0);
    326	}
    327}
    328
    329static void rts5261_clear_ocpstat(struct rtsx_pcr *pcr)
    330{
    331	u8 mask = 0;
    332	u8 val = 0;
    333
    334	mask = SD_OCP_INT_CLR | SD_OC_CLR;
    335	val = SD_OCP_INT_CLR | SD_OC_CLR;
    336
    337	rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val);
    338
    339	udelay(1000);
    340	rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
    341
    342}
    343
    344static void rts5261_process_ocp(struct rtsx_pcr *pcr)
    345{
    346	if (!pcr->option.ocp_en)
    347		return;
    348
    349	rtsx_pci_get_ocpstat(pcr, &pcr->ocp_stat);
    350
    351	if (pcr->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
    352		rts5261_clear_ocpstat(pcr);
    353		rts5261_card_power_off(pcr, RTSX_SD_CARD);
    354		rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0);
    355		pcr->ocp_stat = 0;
    356	}
    357
    358}
    359
    360static void rts5261_init_from_hw(struct rtsx_pcr *pcr)
    361{
    362	struct pci_dev *pdev = pcr->pci;
    363	u32 lval1, lval2, i;
    364	u16 setting_reg1, setting_reg2;
    365	u8 valid, efuse_valid, tmp;
    366
    367	rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
    368		REG_EFUSE_POR | REG_EFUSE_POWER_MASK,
    369		REG_EFUSE_POR | REG_EFUSE_POWERON);
    370	udelay(1);
    371	rtsx_pci_write_register(pcr, RTS5261_EFUSE_ADDR,
    372		RTS5261_EFUSE_ADDR_MASK, 0x00);
    373	rtsx_pci_write_register(pcr, RTS5261_EFUSE_CTL,
    374		RTS5261_EFUSE_ENABLE | RTS5261_EFUSE_MODE_MASK,
    375		RTS5261_EFUSE_ENABLE);
    376
    377	/* Wait transfer end */
    378	for (i = 0; i < MAX_RW_REG_CNT; i++) {
    379		rtsx_pci_read_register(pcr, RTS5261_EFUSE_CTL, &tmp);
    380		if ((tmp & 0x80) == 0)
    381			break;
    382	}
    383	rtsx_pci_read_register(pcr, RTS5261_EFUSE_READ_DATA, &tmp);
    384	efuse_valid = ((tmp & 0x0C) >> 2);
    385	pcr_dbg(pcr, "Load efuse valid: 0x%x\n", efuse_valid);
    386
    387	pci_read_config_dword(pdev, PCR_SETTING_REG2, &lval2);
    388	pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, lval2);
    389	/* 0x816 */
    390	valid = (u8)((lval2 >> 16) & 0x03);
    391
    392	rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
    393		REG_EFUSE_POR, 0);
    394	pcr_dbg(pcr, "Disable efuse por!\n");
    395
    396	if (efuse_valid == 2 || efuse_valid == 3) {
    397		if (valid == 3) {
    398			/* Bypass efuse */
    399			setting_reg1 = PCR_SETTING_REG1;
    400			setting_reg2 = PCR_SETTING_REG2;
    401		} else {
    402			/* Use efuse data */
    403			setting_reg1 = PCR_SETTING_REG4;
    404			setting_reg2 = PCR_SETTING_REG5;
    405		}
    406	} else if (efuse_valid == 0) {
    407		// default
    408		setting_reg1 = PCR_SETTING_REG1;
    409		setting_reg2 = PCR_SETTING_REG2;
    410	} else {
    411		return;
    412	}
    413
    414	pci_read_config_dword(pdev, setting_reg2, &lval2);
    415	pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", setting_reg2, lval2);
    416
    417	if (!rts5261_vendor_setting_valid(lval2)) {
    418		/* Not support MMC default */
    419		pcr->extra_caps |= EXTRA_CAPS_NO_MMC;
    420		pcr_dbg(pcr, "skip fetch vendor setting\n");
    421		return;
    422	}
    423
    424	if (!rts5261_reg_check_mmc_support(lval2))
    425		pcr->extra_caps |= EXTRA_CAPS_NO_MMC;
    426
    427	pcr->rtd3_en = rts5261_reg_to_rtd3(lval2);
    428
    429	if (rts5261_reg_check_reverse_socket(lval2))
    430		pcr->flags |= PCR_REVERSE_SOCKET;
    431
    432	pci_read_config_dword(pdev, setting_reg1, &lval1);
    433	pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", setting_reg1, lval1);
    434
    435	pcr->aspm_en = rts5261_reg_to_aspm(lval1);
    436	pcr->sd30_drive_sel_1v8 = rts5261_reg_to_sd30_drive_sel_1v8(lval1);
    437	pcr->sd30_drive_sel_3v3 = rts5261_reg_to_sd30_drive_sel_3v3(lval1);
    438
    439	if (setting_reg1 == PCR_SETTING_REG1) {
    440		/* store setting */
    441		rtsx_pci_write_register(pcr, 0xFF0C, 0xFF, (u8)(lval1 & 0xFF));
    442		rtsx_pci_write_register(pcr, 0xFF0D, 0xFF, (u8)((lval1 >> 8) & 0xFF));
    443		rtsx_pci_write_register(pcr, 0xFF0E, 0xFF, (u8)((lval1 >> 16) & 0xFF));
    444		rtsx_pci_write_register(pcr, 0xFF0F, 0xFF, (u8)((lval1 >> 24) & 0xFF));
    445		rtsx_pci_write_register(pcr, 0xFF10, 0xFF, (u8)(lval2 & 0xFF));
    446		rtsx_pci_write_register(pcr, 0xFF11, 0xFF, (u8)((lval2 >> 8) & 0xFF));
    447		rtsx_pci_write_register(pcr, 0xFF12, 0xFF, (u8)((lval2 >> 16) & 0xFF));
    448
    449		pci_write_config_dword(pdev, PCR_SETTING_REG4, lval1);
    450		lval2 = lval2 & 0x00FFFFFF;
    451		pci_write_config_dword(pdev, PCR_SETTING_REG5, lval2);
    452	}
    453}
    454
    455static void rts5261_init_from_cfg(struct rtsx_pcr *pcr)
    456{
    457	struct pci_dev *pdev = pcr->pci;
    458	int l1ss;
    459	u32 lval;
    460	struct rtsx_cr_option *option = &pcr->option;
    461
    462	l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS);
    463	if (!l1ss)
    464		return;
    465
    466	pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval);
    467
    468	if (lval & PCI_L1SS_CTL1_ASPM_L1_1)
    469		rtsx_set_dev_flag(pcr, ASPM_L1_1_EN);
    470	else
    471		rtsx_clear_dev_flag(pcr, ASPM_L1_1_EN);
    472
    473	if (lval & PCI_L1SS_CTL1_ASPM_L1_2)
    474		rtsx_set_dev_flag(pcr, ASPM_L1_2_EN);
    475	else
    476		rtsx_clear_dev_flag(pcr, ASPM_L1_2_EN);
    477
    478	if (lval & PCI_L1SS_CTL1_PCIPM_L1_1)
    479		rtsx_set_dev_flag(pcr, PM_L1_1_EN);
    480	else
    481		rtsx_clear_dev_flag(pcr, PM_L1_1_EN);
    482
    483	if (lval & PCI_L1SS_CTL1_PCIPM_L1_2)
    484		rtsx_set_dev_flag(pcr, PM_L1_2_EN);
    485	else
    486		rtsx_clear_dev_flag(pcr, PM_L1_2_EN);
    487
    488	rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0xFF, 0);
    489	if (option->ltr_en) {
    490		u16 val;
    491
    492		pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &val);
    493		if (val & PCI_EXP_DEVCTL2_LTR_EN) {
    494			option->ltr_enabled = true;
    495			option->ltr_active = true;
    496			rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
    497		} else {
    498			option->ltr_enabled = false;
    499		}
    500	}
    501
    502	if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
    503				| PM_L1_1_EN | PM_L1_2_EN))
    504		option->force_clkreq_0 = false;
    505	else
    506		option->force_clkreq_0 = true;
    507}
    508
    509static int rts5261_extra_init_hw(struct rtsx_pcr *pcr)
    510{
    511	struct rtsx_cr_option *option = &pcr->option;
    512	u32 val;
    513
    514	rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG1,
    515			CD_RESUME_EN_MASK, CD_RESUME_EN_MASK);
    516
    517	rts5261_init_from_cfg(pcr);
    518	rts5261_init_from_hw(pcr);
    519
    520	/* power off efuse */
    521	rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
    522			REG_EFUSE_POWER_MASK, REG_EFUSE_POWEROFF);
    523	rtsx_pci_write_register(pcr, L1SUB_CONFIG1,
    524			AUX_CLK_ACTIVE_SEL_MASK, MAC_CKSW_DONE);
    525	rtsx_pci_write_register(pcr, L1SUB_CONFIG3, 0xFF, 0);
    526
    527	if (is_version_higher_than(pcr, PID_5261, IC_VER_B)) {
    528		val = rtsx_pci_readl(pcr, RTSX_DUM_REG);
    529		rtsx_pci_writel(pcr, RTSX_DUM_REG, val | 0x1);
    530	}
    531	rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG4,
    532			RTS5261_AUX_CLK_16M_EN, 0);
    533
    534	/* Release PRSNT# */
    535	rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG4,
    536			RTS5261_FORCE_PRSNT_LOW, 0);
    537	rtsx_pci_write_register(pcr, FUNC_FORCE_CTL,
    538			FUNC_FORCE_UPME_XMT_DBG, FUNC_FORCE_UPME_XMT_DBG);
    539
    540	rtsx_pci_write_register(pcr, PCLK_CTL,
    541			PCLK_MODE_SEL, PCLK_MODE_SEL);
    542
    543	rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0);
    544	rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, CLK_PM_EN, CLK_PM_EN);
    545
    546	/* LED shine disabled, set initial shine cycle period */
    547	rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x0F, 0x02);
    548
    549	/* Configure driving */
    550	rts5261_fill_driving(pcr, OUTPUT_3V3);
    551
    552	if (pcr->flags & PCR_REVERSE_SOCKET)
    553		rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x30);
    554	else
    555		rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x00);
    556
    557	/*
    558	 * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced
    559	 * to drive low, and we forcibly request clock.
    560	 */
    561	if (option->force_clkreq_0)
    562		rtsx_pci_write_register(pcr, PETXCFG,
    563				 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
    564	else
    565		rtsx_pci_write_register(pcr, PETXCFG,
    566				 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
    567
    568	rtsx_pci_write_register(pcr, PWD_SUSPEND_EN, 0xFF, 0xFB);
    569
    570	if (pcr->rtd3_en) {
    571		rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x01);
    572		rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
    573				FORCE_PM_CONTROL | FORCE_PM_VALUE,
    574				FORCE_PM_CONTROL | FORCE_PM_VALUE);
    575	} else {
    576		rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x00);
    577		rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
    578				FORCE_PM_CONTROL | FORCE_PM_VALUE, FORCE_PM_CONTROL);
    579	}
    580	rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, D3_DELINK_MODE_EN, 0x00);
    581
    582	/* Clear Enter RTD3_cold Information*/
    583	rtsx_pci_write_register(pcr, RTS5261_FW_CTL,
    584		RTS5261_INFORM_RTD3_COLD, 0);
    585
    586	return 0;
    587}
    588
    589static void rts5261_enable_aspm(struct rtsx_pcr *pcr, bool enable)
    590{
    591	u8 val = FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;
    592	u8 mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;
    593
    594	if (pcr->aspm_enabled == enable)
    595		return;
    596
    597	val |= (pcr->aspm_en & 0x02);
    598	rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val);
    599	pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
    600					   PCI_EXP_LNKCTL_ASPMC, pcr->aspm_en);
    601	pcr->aspm_enabled = enable;
    602}
    603
    604static void rts5261_disable_aspm(struct rtsx_pcr *pcr, bool enable)
    605{
    606	u8 val = FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;
    607	u8 mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;
    608
    609	if (pcr->aspm_enabled == enable)
    610		return;
    611
    612	pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
    613					   PCI_EXP_LNKCTL_ASPMC, 0);
    614	rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val);
    615	rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
    616	udelay(10);
    617	pcr->aspm_enabled = enable;
    618}
    619
    620static void rts5261_set_aspm(struct rtsx_pcr *pcr, bool enable)
    621{
    622	if (enable)
    623		rts5261_enable_aspm(pcr, true);
    624	else
    625		rts5261_disable_aspm(pcr, false);
    626}
    627
    628static void rts5261_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)
    629{
    630	struct rtsx_cr_option *option = &pcr->option;
    631	int aspm_L1_1, aspm_L1_2;
    632	u8 val = 0;
    633
    634	aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN);
    635	aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN);
    636
    637	if (active) {
    638		/* run, latency: 60us */
    639		if (aspm_L1_1)
    640			val = option->ltr_l1off_snooze_sspwrgate;
    641	} else {
    642		/* l1off, latency: 300us */
    643		if (aspm_L1_2)
    644			val = option->ltr_l1off_sspwrgate;
    645	}
    646
    647	rtsx_set_l1off_sub(pcr, val);
    648}
    649
    650static const struct pcr_ops rts5261_pcr_ops = {
    651	.turn_on_led = rts5261_turn_on_led,
    652	.turn_off_led = rts5261_turn_off_led,
    653	.extra_init_hw = rts5261_extra_init_hw,
    654	.enable_auto_blink = rts5261_enable_auto_blink,
    655	.disable_auto_blink = rts5261_disable_auto_blink,
    656	.card_power_on = rts5261_card_power_on,
    657	.card_power_off = rts5261_card_power_off,
    658	.switch_output_voltage = rts5261_switch_output_voltage,
    659	.force_power_down = rts5261_force_power_down,
    660	.stop_cmd = rts5261_stop_cmd,
    661	.set_aspm = rts5261_set_aspm,
    662	.set_l1off_cfg_sub_d0 = rts5261_set_l1off_cfg_sub_d0,
    663	.enable_ocp = rts5261_enable_ocp,
    664	.disable_ocp = rts5261_disable_ocp,
    665	.init_ocp = rts5261_init_ocp,
    666	.process_ocp = rts5261_process_ocp,
    667	.clear_ocpstat = rts5261_clear_ocpstat,
    668};
    669
    670static inline u8 double_ssc_depth(u8 depth)
    671{
    672	return ((depth > 1) ? (depth - 1) : depth);
    673}
    674
    675int rts5261_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
    676		u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk)
    677{
    678	int err, clk;
    679	u16 n;
    680	u8 clk_divider, mcu_cnt, div;
    681	static const u8 depth[] = {
    682		[RTSX_SSC_DEPTH_4M] = RTS5261_SSC_DEPTH_4M,
    683		[RTSX_SSC_DEPTH_2M] = RTS5261_SSC_DEPTH_2M,
    684		[RTSX_SSC_DEPTH_1M] = RTS5261_SSC_DEPTH_1M,
    685		[RTSX_SSC_DEPTH_500K] = RTS5261_SSC_DEPTH_512K,
    686	};
    687
    688	if (initial_mode) {
    689		/* We use 250k(around) here, in initial stage */
    690		if (is_version_higher_than(pcr, PID_5261, IC_VER_C)) {
    691			clk_divider = SD_CLK_DIVIDE_256;
    692			card_clock = 60000000;
    693		} else {
    694			clk_divider = SD_CLK_DIVIDE_128;
    695			card_clock = 30000000;
    696		}
    697	} else {
    698		clk_divider = SD_CLK_DIVIDE_0;
    699	}
    700	err = rtsx_pci_write_register(pcr, SD_CFG1,
    701			SD_CLK_DIVIDE_MASK, clk_divider);
    702	if (err < 0)
    703		return err;
    704
    705	card_clock /= 1000000;
    706	pcr_dbg(pcr, "Switch card clock to %dMHz\n", card_clock);
    707
    708	clk = card_clock;
    709	if (!initial_mode && double_clk)
    710		clk = card_clock * 2;
    711	pcr_dbg(pcr, "Internal SSC clock: %dMHz (cur_clock = %d)\n",
    712		clk, pcr->cur_clock);
    713
    714	if (clk == pcr->cur_clock)
    715		return 0;
    716
    717	if (pcr->ops->conv_clk_and_div_n)
    718		n = pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N);
    719	else
    720		n = clk - 4;
    721	if ((clk <= 4) || (n > 396))
    722		return -EINVAL;
    723
    724	mcu_cnt = 125/clk + 3;
    725	if (mcu_cnt > 15)
    726		mcu_cnt = 15;
    727
    728	div = CLK_DIV_1;
    729	while ((n < MIN_DIV_N_PCR - 4) && (div < CLK_DIV_8)) {
    730		if (pcr->ops->conv_clk_and_div_n) {
    731			int dbl_clk = pcr->ops->conv_clk_and_div_n(n,
    732					DIV_N_TO_CLK) * 2;
    733			n = pcr->ops->conv_clk_and_div_n(dbl_clk,
    734					CLK_TO_DIV_N);
    735		} else {
    736			n = (n + 4) * 2 - 4;
    737		}
    738		div++;
    739	}
    740
    741	n = (n / 2) - 1;
    742	pcr_dbg(pcr, "n = %d, div = %d\n", n, div);
    743
    744	ssc_depth = depth[ssc_depth];
    745	if (double_clk)
    746		ssc_depth = double_ssc_depth(ssc_depth);
    747
    748	if (ssc_depth) {
    749		if (div == CLK_DIV_2) {
    750			if (ssc_depth > 1)
    751				ssc_depth -= 1;
    752			else
    753				ssc_depth = RTS5261_SSC_DEPTH_8M;
    754		} else if (div == CLK_DIV_4) {
    755			if (ssc_depth > 2)
    756				ssc_depth -= 2;
    757			else
    758				ssc_depth = RTS5261_SSC_DEPTH_8M;
    759		} else if (div == CLK_DIV_8) {
    760			if (ssc_depth > 3)
    761				ssc_depth -= 3;
    762			else
    763				ssc_depth = RTS5261_SSC_DEPTH_8M;
    764		}
    765	} else {
    766		ssc_depth = 0;
    767	}
    768	pcr_dbg(pcr, "ssc_depth = %d\n", ssc_depth);
    769
    770	rtsx_pci_init_cmd(pcr);
    771	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
    772				CLK_LOW_FREQ, CLK_LOW_FREQ);
    773	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV,
    774			0xFF, (div << 4) | mcu_cnt);
    775	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
    776	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2,
    777			SSC_DEPTH_MASK, ssc_depth);
    778	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n);
    779	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);
    780	if (vpclk) {
    781		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
    782				PHASE_NOT_RESET, 0);
    783		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK1_CTL,
    784				PHASE_NOT_RESET, 0);
    785		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
    786				PHASE_NOT_RESET, PHASE_NOT_RESET);
    787		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK1_CTL,
    788				PHASE_NOT_RESET, PHASE_NOT_RESET);
    789	}
    790
    791	err = rtsx_pci_send_cmd(pcr, 2000);
    792	if (err < 0)
    793		return err;
    794
    795	/* Wait SSC clock stable */
    796	udelay(SSC_CLOCK_STABLE_WAIT);
    797	err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
    798	if (err < 0)
    799		return err;
    800
    801	pcr->cur_clock = clk;
    802	return 0;
    803
    804}
    805
    806void rts5261_init_params(struct rtsx_pcr *pcr)
    807{
    808	struct rtsx_cr_option *option = &pcr->option;
    809	struct rtsx_hw_param *hw_param = &pcr->hw_param;
    810	u8 val;
    811
    812	pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
    813	rtsx_pci_read_register(pcr, RTS5261_FW_STATUS, &val);
    814	if (!(val & RTS5261_EXPRESS_LINK_FAIL_MASK))
    815		pcr->extra_caps |= EXTRA_CAPS_SD_EXPRESS;
    816	pcr->num_slots = 1;
    817	pcr->ops = &rts5261_pcr_ops;
    818
    819	pcr->flags = 0;
    820	pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
    821	pcr->sd30_drive_sel_1v8 = 0x00;
    822	pcr->sd30_drive_sel_3v3 = 0x00;
    823	pcr->aspm_en = ASPM_L1_EN;
    824	pcr->aspm_mode = ASPM_MODE_REG;
    825	pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 11);
    826	pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
    827
    828	pcr->ic_version = rts5261_get_ic_version(pcr);
    829	pcr->sd_pull_ctl_enable_tbl = rts5261_sd_pull_ctl_enable_tbl;
    830	pcr->sd_pull_ctl_disable_tbl = rts5261_sd_pull_ctl_disable_tbl;
    831
    832	pcr->reg_pm_ctrl3 = RTS5261_AUTOLOAD_CFG3;
    833
    834	option->dev_flags = (LTR_L1SS_PWR_GATE_CHECK_CARD_EN
    835				| LTR_L1SS_PWR_GATE_EN);
    836	option->ltr_en = true;
    837
    838	/* init latency of active, idle, L1OFF to 60us, 300us, 3ms */
    839	option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF;
    840	option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF;
    841	option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF;
    842	option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF;
    843	option->ltr_l1off_sspwrgate = 0x7F;
    844	option->ltr_l1off_snooze_sspwrgate = 0x78;
    845
    846	option->ocp_en = 1;
    847	hw_param->interrupt_en |= SD_OC_INT_EN;
    848	hw_param->ocp_glitch =  SD_OCP_GLITCH_800U;
    849	option->sd_800mA_ocp_thd =  RTS5261_LDO1_OCP_THD_1040;
    850}