dma0_qm_regs.h (32569B)
1/* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2018 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8/************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13#ifndef ASIC_REG_DMA0_QM_REGS_H_ 14#define ASIC_REG_DMA0_QM_REGS_H_ 15 16/* 17 ***************************************** 18 * DMA0_QM (Prototype: QMAN) 19 ***************************************** 20 */ 21 22#define mmDMA0_QM_GLBL_CFG0 0x508000 23 24#define mmDMA0_QM_GLBL_CFG1 0x508004 25 26#define mmDMA0_QM_GLBL_PROT 0x508008 27 28#define mmDMA0_QM_GLBL_ERR_CFG 0x50800C 29 30#define mmDMA0_QM_GLBL_SECURE_PROPS_0 0x508010 31 32#define mmDMA0_QM_GLBL_SECURE_PROPS_1 0x508014 33 34#define mmDMA0_QM_GLBL_SECURE_PROPS_2 0x508018 35 36#define mmDMA0_QM_GLBL_SECURE_PROPS_3 0x50801C 37 38#define mmDMA0_QM_GLBL_SECURE_PROPS_4 0x508020 39 40#define mmDMA0_QM_GLBL_NON_SECURE_PROPS_0 0x508024 41 42#define mmDMA0_QM_GLBL_NON_SECURE_PROPS_1 0x508028 43 44#define mmDMA0_QM_GLBL_NON_SECURE_PROPS_2 0x50802C 45 46#define mmDMA0_QM_GLBL_NON_SECURE_PROPS_3 0x508030 47 48#define mmDMA0_QM_GLBL_NON_SECURE_PROPS_4 0x508034 49 50#define mmDMA0_QM_GLBL_STS0 0x508038 51 52#define mmDMA0_QM_GLBL_STS1_0 0x508040 53 54#define mmDMA0_QM_GLBL_STS1_1 0x508044 55 56#define mmDMA0_QM_GLBL_STS1_2 0x508048 57 58#define mmDMA0_QM_GLBL_STS1_3 0x50804C 59 60#define mmDMA0_QM_GLBL_STS1_4 0x508050 61 62#define mmDMA0_QM_GLBL_MSG_EN_0 0x508054 63 64#define mmDMA0_QM_GLBL_MSG_EN_1 0x508058 65 66#define mmDMA0_QM_GLBL_MSG_EN_2 0x50805C 67 68#define mmDMA0_QM_GLBL_MSG_EN_3 0x508060 69 70#define mmDMA0_QM_GLBL_MSG_EN_4 0x508068 71 72#define mmDMA0_QM_PQ_BASE_LO_0 0x508070 73 74#define mmDMA0_QM_PQ_BASE_LO_1 0x508074 75 76#define mmDMA0_QM_PQ_BASE_LO_2 0x508078 77 78#define mmDMA0_QM_PQ_BASE_LO_3 0x50807C 79 80#define mmDMA0_QM_PQ_BASE_HI_0 0x508080 81 82#define mmDMA0_QM_PQ_BASE_HI_1 0x508084 83 84#define mmDMA0_QM_PQ_BASE_HI_2 0x508088 85 86#define mmDMA0_QM_PQ_BASE_HI_3 0x50808C 87 88#define mmDMA0_QM_PQ_SIZE_0 0x508090 89 90#define mmDMA0_QM_PQ_SIZE_1 0x508094 91 92#define mmDMA0_QM_PQ_SIZE_2 0x508098 93 94#define mmDMA0_QM_PQ_SIZE_3 0x50809C 95 96#define mmDMA0_QM_PQ_PI_0 0x5080A0 97 98#define mmDMA0_QM_PQ_PI_1 0x5080A4 99 100#define mmDMA0_QM_PQ_PI_2 0x5080A8 101 102#define mmDMA0_QM_PQ_PI_3 0x5080AC 103 104#define mmDMA0_QM_PQ_CI_0 0x5080B0 105 106#define mmDMA0_QM_PQ_CI_1 0x5080B4 107 108#define mmDMA0_QM_PQ_CI_2 0x5080B8 109 110#define mmDMA0_QM_PQ_CI_3 0x5080BC 111 112#define mmDMA0_QM_PQ_CFG0_0 0x5080C0 113 114#define mmDMA0_QM_PQ_CFG0_1 0x5080C4 115 116#define mmDMA0_QM_PQ_CFG0_2 0x5080C8 117 118#define mmDMA0_QM_PQ_CFG0_3 0x5080CC 119 120#define mmDMA0_QM_PQ_CFG1_0 0x5080D0 121 122#define mmDMA0_QM_PQ_CFG1_1 0x5080D4 123 124#define mmDMA0_QM_PQ_CFG1_2 0x5080D8 125 126#define mmDMA0_QM_PQ_CFG1_3 0x5080DC 127 128#define mmDMA0_QM_PQ_ARUSER_31_11_0 0x5080E0 129 130#define mmDMA0_QM_PQ_ARUSER_31_11_1 0x5080E4 131 132#define mmDMA0_QM_PQ_ARUSER_31_11_2 0x5080E8 133 134#define mmDMA0_QM_PQ_ARUSER_31_11_3 0x5080EC 135 136#define mmDMA0_QM_PQ_STS0_0 0x5080F0 137 138#define mmDMA0_QM_PQ_STS0_1 0x5080F4 139 140#define mmDMA0_QM_PQ_STS0_2 0x5080F8 141 142#define mmDMA0_QM_PQ_STS0_3 0x5080FC 143 144#define mmDMA0_QM_PQ_STS1_0 0x508100 145 146#define mmDMA0_QM_PQ_STS1_1 0x508104 147 148#define mmDMA0_QM_PQ_STS1_2 0x508108 149 150#define mmDMA0_QM_PQ_STS1_3 0x50810C 151 152#define mmDMA0_QM_CQ_CFG0_0 0x508110 153 154#define mmDMA0_QM_CQ_CFG0_1 0x508114 155 156#define mmDMA0_QM_CQ_CFG0_2 0x508118 157 158#define mmDMA0_QM_CQ_CFG0_3 0x50811C 159 160#define mmDMA0_QM_CQ_CFG0_4 0x508120 161 162#define mmDMA0_QM_CQ_CFG1_0 0x508124 163 164#define mmDMA0_QM_CQ_CFG1_1 0x508128 165 166#define mmDMA0_QM_CQ_CFG1_2 0x50812C 167 168#define mmDMA0_QM_CQ_CFG1_3 0x508130 169 170#define mmDMA0_QM_CQ_CFG1_4 0x508134 171 172#define mmDMA0_QM_CQ_ARUSER_31_11_0 0x508138 173 174#define mmDMA0_QM_CQ_ARUSER_31_11_1 0x50813C 175 176#define mmDMA0_QM_CQ_ARUSER_31_11_2 0x508140 177 178#define mmDMA0_QM_CQ_ARUSER_31_11_3 0x508144 179 180#define mmDMA0_QM_CQ_ARUSER_31_11_4 0x508148 181 182#define mmDMA0_QM_CQ_STS0_0 0x50814C 183 184#define mmDMA0_QM_CQ_STS0_1 0x508150 185 186#define mmDMA0_QM_CQ_STS0_2 0x508154 187 188#define mmDMA0_QM_CQ_STS0_3 0x508158 189 190#define mmDMA0_QM_CQ_STS0_4 0x50815C 191 192#define mmDMA0_QM_CQ_STS1_0 0x508160 193 194#define mmDMA0_QM_CQ_STS1_1 0x508164 195 196#define mmDMA0_QM_CQ_STS1_2 0x508168 197 198#define mmDMA0_QM_CQ_STS1_3 0x50816C 199 200#define mmDMA0_QM_CQ_STS1_4 0x508170 201 202#define mmDMA0_QM_CQ_PTR_LO_0 0x508174 203 204#define mmDMA0_QM_CQ_PTR_HI_0 0x508178 205 206#define mmDMA0_QM_CQ_TSIZE_0 0x50817C 207 208#define mmDMA0_QM_CQ_CTL_0 0x508180 209 210#define mmDMA0_QM_CQ_PTR_LO_1 0x508184 211 212#define mmDMA0_QM_CQ_PTR_HI_1 0x508188 213 214#define mmDMA0_QM_CQ_TSIZE_1 0x50818C 215 216#define mmDMA0_QM_CQ_CTL_1 0x508190 217 218#define mmDMA0_QM_CQ_PTR_LO_2 0x508194 219 220#define mmDMA0_QM_CQ_PTR_HI_2 0x508198 221 222#define mmDMA0_QM_CQ_TSIZE_2 0x50819C 223 224#define mmDMA0_QM_CQ_CTL_2 0x5081A0 225 226#define mmDMA0_QM_CQ_PTR_LO_3 0x5081A4 227 228#define mmDMA0_QM_CQ_PTR_HI_3 0x5081A8 229 230#define mmDMA0_QM_CQ_TSIZE_3 0x5081AC 231 232#define mmDMA0_QM_CQ_CTL_3 0x5081B0 233 234#define mmDMA0_QM_CQ_PTR_LO_4 0x5081B4 235 236#define mmDMA0_QM_CQ_PTR_HI_4 0x5081B8 237 238#define mmDMA0_QM_CQ_TSIZE_4 0x5081BC 239 240#define mmDMA0_QM_CQ_CTL_4 0x5081C0 241 242#define mmDMA0_QM_CQ_PTR_LO_STS_0 0x5081C4 243 244#define mmDMA0_QM_CQ_PTR_LO_STS_1 0x5081C8 245 246#define mmDMA0_QM_CQ_PTR_LO_STS_2 0x5081CC 247 248#define mmDMA0_QM_CQ_PTR_LO_STS_3 0x5081D0 249 250#define mmDMA0_QM_CQ_PTR_LO_STS_4 0x5081D4 251 252#define mmDMA0_QM_CQ_PTR_HI_STS_0 0x5081D8 253 254#define mmDMA0_QM_CQ_PTR_HI_STS_1 0x5081DC 255 256#define mmDMA0_QM_CQ_PTR_HI_STS_2 0x5081E0 257 258#define mmDMA0_QM_CQ_PTR_HI_STS_3 0x5081E4 259 260#define mmDMA0_QM_CQ_PTR_HI_STS_4 0x5081E8 261 262#define mmDMA0_QM_CQ_TSIZE_STS_0 0x5081EC 263 264#define mmDMA0_QM_CQ_TSIZE_STS_1 0x5081F0 265 266#define mmDMA0_QM_CQ_TSIZE_STS_2 0x5081F4 267 268#define mmDMA0_QM_CQ_TSIZE_STS_3 0x5081F8 269 270#define mmDMA0_QM_CQ_TSIZE_STS_4 0x5081FC 271 272#define mmDMA0_QM_CQ_CTL_STS_0 0x508200 273 274#define mmDMA0_QM_CQ_CTL_STS_1 0x508204 275 276#define mmDMA0_QM_CQ_CTL_STS_2 0x508208 277 278#define mmDMA0_QM_CQ_CTL_STS_3 0x50820C 279 280#define mmDMA0_QM_CQ_CTL_STS_4 0x508210 281 282#define mmDMA0_QM_CQ_IFIFO_CNT_0 0x508214 283 284#define mmDMA0_QM_CQ_IFIFO_CNT_1 0x508218 285 286#define mmDMA0_QM_CQ_IFIFO_CNT_2 0x50821C 287 288#define mmDMA0_QM_CQ_IFIFO_CNT_3 0x508220 289 290#define mmDMA0_QM_CQ_IFIFO_CNT_4 0x508224 291 292#define mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_0 0x508228 293 294#define mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_1 0x50822C 295 296#define mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_2 0x508230 297 298#define mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_3 0x508234 299 300#define mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_4 0x508238 301 302#define mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_0 0x50823C 303 304#define mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_1 0x508240 305 306#define mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_2 0x508244 307 308#define mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_3 0x508248 309 310#define mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_4 0x50824C 311 312#define mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_0 0x508250 313 314#define mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_1 0x508254 315 316#define mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_2 0x508258 317 318#define mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_3 0x50825C 319 320#define mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_4 0x508260 321 322#define mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_0 0x508264 323 324#define mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_1 0x508268 325 326#define mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_2 0x50826C 327 328#define mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_3 0x508270 329 330#define mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_4 0x508274 331 332#define mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_0 0x508278 333 334#define mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_1 0x50827C 335 336#define mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_2 0x508280 337 338#define mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_3 0x508284 339 340#define mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_4 0x508288 341 342#define mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_0 0x50828C 343 344#define mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_1 0x508290 345 346#define mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_2 0x508294 347 348#define mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_3 0x508298 349 350#define mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_4 0x50829C 351 352#define mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_0 0x5082A0 353 354#define mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_1 0x5082A4 355 356#define mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_2 0x5082A8 357 358#define mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_3 0x5082AC 359 360#define mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_4 0x5082B0 361 362#define mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_0 0x5082B4 363 364#define mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_1 0x5082B8 365 366#define mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_2 0x5082BC 367 368#define mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_3 0x5082C0 369 370#define mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_4 0x5082C4 371 372#define mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_0 0x5082C8 373 374#define mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_1 0x5082CC 375 376#define mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_2 0x5082D0 377 378#define mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_3 0x5082D4 379 380#define mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_4 0x5082D8 381 382#define mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x5082E0 383 384#define mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x5082E4 385 386#define mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x5082E8 387 388#define mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x5082EC 389 390#define mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x5082F0 391 392#define mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x5082F4 393 394#define mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x5082F8 395 396#define mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x5082FC 397 398#define mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x508300 399 400#define mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x508304 401 402#define mmDMA0_QM_CP_FENCE0_RDATA_0 0x508308 403 404#define mmDMA0_QM_CP_FENCE0_RDATA_1 0x50830C 405 406#define mmDMA0_QM_CP_FENCE0_RDATA_2 0x508310 407 408#define mmDMA0_QM_CP_FENCE0_RDATA_3 0x508314 409 410#define mmDMA0_QM_CP_FENCE0_RDATA_4 0x508318 411 412#define mmDMA0_QM_CP_FENCE1_RDATA_0 0x50831C 413 414#define mmDMA0_QM_CP_FENCE1_RDATA_1 0x508320 415 416#define mmDMA0_QM_CP_FENCE1_RDATA_2 0x508324 417 418#define mmDMA0_QM_CP_FENCE1_RDATA_3 0x508328 419 420#define mmDMA0_QM_CP_FENCE1_RDATA_4 0x50832C 421 422#define mmDMA0_QM_CP_FENCE2_RDATA_0 0x508330 423 424#define mmDMA0_QM_CP_FENCE2_RDATA_1 0x508334 425 426#define mmDMA0_QM_CP_FENCE2_RDATA_2 0x508338 427 428#define mmDMA0_QM_CP_FENCE2_RDATA_3 0x50833C 429 430#define mmDMA0_QM_CP_FENCE2_RDATA_4 0x508340 431 432#define mmDMA0_QM_CP_FENCE3_RDATA_0 0x508344 433 434#define mmDMA0_QM_CP_FENCE3_RDATA_1 0x508348 435 436#define mmDMA0_QM_CP_FENCE3_RDATA_2 0x50834C 437 438#define mmDMA0_QM_CP_FENCE3_RDATA_3 0x508350 439 440#define mmDMA0_QM_CP_FENCE3_RDATA_4 0x508354 441 442#define mmDMA0_QM_CP_FENCE0_CNT_0 0x508358 443 444#define mmDMA0_QM_CP_FENCE0_CNT_1 0x50835C 445 446#define mmDMA0_QM_CP_FENCE0_CNT_2 0x508360 447 448#define mmDMA0_QM_CP_FENCE0_CNT_3 0x508364 449 450#define mmDMA0_QM_CP_FENCE0_CNT_4 0x508368 451 452#define mmDMA0_QM_CP_FENCE1_CNT_0 0x50836C 453 454#define mmDMA0_QM_CP_FENCE1_CNT_1 0x508370 455 456#define mmDMA0_QM_CP_FENCE1_CNT_2 0x508374 457 458#define mmDMA0_QM_CP_FENCE1_CNT_3 0x508378 459 460#define mmDMA0_QM_CP_FENCE1_CNT_4 0x50837C 461 462#define mmDMA0_QM_CP_FENCE2_CNT_0 0x508380 463 464#define mmDMA0_QM_CP_FENCE2_CNT_1 0x508384 465 466#define mmDMA0_QM_CP_FENCE2_CNT_2 0x508388 467 468#define mmDMA0_QM_CP_FENCE2_CNT_3 0x50838C 469 470#define mmDMA0_QM_CP_FENCE2_CNT_4 0x508390 471 472#define mmDMA0_QM_CP_FENCE3_CNT_0 0x508394 473 474#define mmDMA0_QM_CP_FENCE3_CNT_1 0x508398 475 476#define mmDMA0_QM_CP_FENCE3_CNT_2 0x50839C 477 478#define mmDMA0_QM_CP_FENCE3_CNT_3 0x5083A0 479 480#define mmDMA0_QM_CP_FENCE3_CNT_4 0x5083A4 481 482#define mmDMA0_QM_CP_STS_0 0x5083A8 483 484#define mmDMA0_QM_CP_STS_1 0x5083AC 485 486#define mmDMA0_QM_CP_STS_2 0x5083B0 487 488#define mmDMA0_QM_CP_STS_3 0x5083B4 489 490#define mmDMA0_QM_CP_STS_4 0x5083B8 491 492#define mmDMA0_QM_CP_CURRENT_INST_LO_0 0x5083BC 493 494#define mmDMA0_QM_CP_CURRENT_INST_LO_1 0x5083C0 495 496#define mmDMA0_QM_CP_CURRENT_INST_LO_2 0x5083C4 497 498#define mmDMA0_QM_CP_CURRENT_INST_LO_3 0x5083C8 499 500#define mmDMA0_QM_CP_CURRENT_INST_LO_4 0x5083CC 501 502#define mmDMA0_QM_CP_CURRENT_INST_HI_0 0x5083D0 503 504#define mmDMA0_QM_CP_CURRENT_INST_HI_1 0x5083D4 505 506#define mmDMA0_QM_CP_CURRENT_INST_HI_2 0x5083D8 507 508#define mmDMA0_QM_CP_CURRENT_INST_HI_3 0x5083DC 509 510#define mmDMA0_QM_CP_CURRENT_INST_HI_4 0x5083E0 511 512#define mmDMA0_QM_CP_BARRIER_CFG_0 0x5083F4 513 514#define mmDMA0_QM_CP_BARRIER_CFG_1 0x5083F8 515 516#define mmDMA0_QM_CP_BARRIER_CFG_2 0x5083FC 517 518#define mmDMA0_QM_CP_BARRIER_CFG_3 0x508400 519 520#define mmDMA0_QM_CP_BARRIER_CFG_4 0x508404 521 522#define mmDMA0_QM_CP_DBG_0_0 0x508408 523 524#define mmDMA0_QM_CP_DBG_0_1 0x50840C 525 526#define mmDMA0_QM_CP_DBG_0_2 0x508410 527 528#define mmDMA0_QM_CP_DBG_0_3 0x508414 529 530#define mmDMA0_QM_CP_DBG_0_4 0x508418 531 532#define mmDMA0_QM_CP_ARUSER_31_11_0 0x50841C 533 534#define mmDMA0_QM_CP_ARUSER_31_11_1 0x508420 535 536#define mmDMA0_QM_CP_ARUSER_31_11_2 0x508424 537 538#define mmDMA0_QM_CP_ARUSER_31_11_3 0x508428 539 540#define mmDMA0_QM_CP_ARUSER_31_11_4 0x50842C 541 542#define mmDMA0_QM_CP_AWUSER_31_11_0 0x508430 543 544#define mmDMA0_QM_CP_AWUSER_31_11_1 0x508434 545 546#define mmDMA0_QM_CP_AWUSER_31_11_2 0x508438 547 548#define mmDMA0_QM_CP_AWUSER_31_11_3 0x50843C 549 550#define mmDMA0_QM_CP_AWUSER_31_11_4 0x508440 551 552#define mmDMA0_QM_ARB_CFG_0 0x508A00 553 554#define mmDMA0_QM_ARB_CHOISE_Q_PUSH 0x508A04 555 556#define mmDMA0_QM_ARB_WRR_WEIGHT_0 0x508A08 557 558#define mmDMA0_QM_ARB_WRR_WEIGHT_1 0x508A0C 559 560#define mmDMA0_QM_ARB_WRR_WEIGHT_2 0x508A10 561 562#define mmDMA0_QM_ARB_WRR_WEIGHT_3 0x508A14 563 564#define mmDMA0_QM_ARB_CFG_1 0x508A18 565 566#define mmDMA0_QM_ARB_MST_AVAIL_CRED_0 0x508A20 567 568#define mmDMA0_QM_ARB_MST_AVAIL_CRED_1 0x508A24 569 570#define mmDMA0_QM_ARB_MST_AVAIL_CRED_2 0x508A28 571 572#define mmDMA0_QM_ARB_MST_AVAIL_CRED_3 0x508A2C 573 574#define mmDMA0_QM_ARB_MST_AVAIL_CRED_4 0x508A30 575 576#define mmDMA0_QM_ARB_MST_AVAIL_CRED_5 0x508A34 577 578#define mmDMA0_QM_ARB_MST_AVAIL_CRED_6 0x508A38 579 580#define mmDMA0_QM_ARB_MST_AVAIL_CRED_7 0x508A3C 581 582#define mmDMA0_QM_ARB_MST_AVAIL_CRED_8 0x508A40 583 584#define mmDMA0_QM_ARB_MST_AVAIL_CRED_9 0x508A44 585 586#define mmDMA0_QM_ARB_MST_AVAIL_CRED_10 0x508A48 587 588#define mmDMA0_QM_ARB_MST_AVAIL_CRED_11 0x508A4C 589 590#define mmDMA0_QM_ARB_MST_AVAIL_CRED_12 0x508A50 591 592#define mmDMA0_QM_ARB_MST_AVAIL_CRED_13 0x508A54 593 594#define mmDMA0_QM_ARB_MST_AVAIL_CRED_14 0x508A58 595 596#define mmDMA0_QM_ARB_MST_AVAIL_CRED_15 0x508A5C 597 598#define mmDMA0_QM_ARB_MST_AVAIL_CRED_16 0x508A60 599 600#define mmDMA0_QM_ARB_MST_AVAIL_CRED_17 0x508A64 601 602#define mmDMA0_QM_ARB_MST_AVAIL_CRED_18 0x508A68 603 604#define mmDMA0_QM_ARB_MST_AVAIL_CRED_19 0x508A6C 605 606#define mmDMA0_QM_ARB_MST_AVAIL_CRED_20 0x508A70 607 608#define mmDMA0_QM_ARB_MST_AVAIL_CRED_21 0x508A74 609 610#define mmDMA0_QM_ARB_MST_AVAIL_CRED_22 0x508A78 611 612#define mmDMA0_QM_ARB_MST_AVAIL_CRED_23 0x508A7C 613 614#define mmDMA0_QM_ARB_MST_AVAIL_CRED_24 0x508A80 615 616#define mmDMA0_QM_ARB_MST_AVAIL_CRED_25 0x508A84 617 618#define mmDMA0_QM_ARB_MST_AVAIL_CRED_26 0x508A88 619 620#define mmDMA0_QM_ARB_MST_AVAIL_CRED_27 0x508A8C 621 622#define mmDMA0_QM_ARB_MST_AVAIL_CRED_28 0x508A90 623 624#define mmDMA0_QM_ARB_MST_AVAIL_CRED_29 0x508A94 625 626#define mmDMA0_QM_ARB_MST_AVAIL_CRED_30 0x508A98 627 628#define mmDMA0_QM_ARB_MST_AVAIL_CRED_31 0x508A9C 629 630#define mmDMA0_QM_ARB_MST_CRED_INC 0x508AA0 631 632#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x508AA4 633 634#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x508AA8 635 636#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x508AAC 637 638#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x508AB0 639 640#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x508AB4 641 642#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x508AB8 643 644#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x508ABC 645 646#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x508AC0 647 648#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x508AC4 649 650#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x508AC8 651 652#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x508ACC 653 654#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x508AD0 655 656#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x508AD4 657 658#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x508AD8 659 660#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x508ADC 661 662#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x508AE0 663 664#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x508AE4 665 666#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x508AE8 667 668#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x508AEC 669 670#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x508AF0 671 672#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x508AF4 673 674#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x508AF8 675 676#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x508AFC 677 678#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x508B00 679 680#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x508B04 681 682#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x508B08 683 684#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x508B0C 685 686#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x508B10 687 688#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x508B14 689 690#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x508B18 691 692#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x508B1C 693 694#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x508B20 695 696#define mmDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x508B28 697 698#define mmDMA0_QM_ARB_MST_SLAVE_EN 0x508B2C 699 700#define mmDMA0_QM_ARB_MST_QUIET_PER 0x508B34 701 702#define mmDMA0_QM_ARB_SLV_CHOISE_WDT 0x508B38 703 704#define mmDMA0_QM_ARB_SLV_ID 0x508B3C 705 706#define mmDMA0_QM_ARB_MSG_MAX_INFLIGHT 0x508B44 707 708#define mmDMA0_QM_ARB_MSG_AWUSER_31_11 0x508B48 709 710#define mmDMA0_QM_ARB_MSG_AWUSER_SEC_PROP 0x508B4C 711 712#define mmDMA0_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x508B50 713 714#define mmDMA0_QM_ARB_BASE_LO 0x508B54 715 716#define mmDMA0_QM_ARB_BASE_HI 0x508B58 717 718#define mmDMA0_QM_ARB_STATE_STS 0x508B80 719 720#define mmDMA0_QM_ARB_CHOISE_FULLNESS_STS 0x508B84 721 722#define mmDMA0_QM_ARB_MSG_STS 0x508B88 723 724#define mmDMA0_QM_ARB_SLV_CHOISE_Q_HEAD 0x508B8C 725 726#define mmDMA0_QM_ARB_ERR_CAUSE 0x508B9C 727 728#define mmDMA0_QM_ARB_ERR_MSG_EN 0x508BA0 729 730#define mmDMA0_QM_ARB_ERR_STS_DRP 0x508BA8 731 732#define mmDMA0_QM_ARB_MST_CRED_STS_0 0x508BB0 733 734#define mmDMA0_QM_ARB_MST_CRED_STS_1 0x508BB4 735 736#define mmDMA0_QM_ARB_MST_CRED_STS_2 0x508BB8 737 738#define mmDMA0_QM_ARB_MST_CRED_STS_3 0x508BBC 739 740#define mmDMA0_QM_ARB_MST_CRED_STS_4 0x508BC0 741 742#define mmDMA0_QM_ARB_MST_CRED_STS_5 0x508BC4 743 744#define mmDMA0_QM_ARB_MST_CRED_STS_6 0x508BC8 745 746#define mmDMA0_QM_ARB_MST_CRED_STS_7 0x508BCC 747 748#define mmDMA0_QM_ARB_MST_CRED_STS_8 0x508BD0 749 750#define mmDMA0_QM_ARB_MST_CRED_STS_9 0x508BD4 751 752#define mmDMA0_QM_ARB_MST_CRED_STS_10 0x508BD8 753 754#define mmDMA0_QM_ARB_MST_CRED_STS_11 0x508BDC 755 756#define mmDMA0_QM_ARB_MST_CRED_STS_12 0x508BE0 757 758#define mmDMA0_QM_ARB_MST_CRED_STS_13 0x508BE4 759 760#define mmDMA0_QM_ARB_MST_CRED_STS_14 0x508BE8 761 762#define mmDMA0_QM_ARB_MST_CRED_STS_15 0x508BEC 763 764#define mmDMA0_QM_ARB_MST_CRED_STS_16 0x508BF0 765 766#define mmDMA0_QM_ARB_MST_CRED_STS_17 0x508BF4 767 768#define mmDMA0_QM_ARB_MST_CRED_STS_18 0x508BF8 769 770#define mmDMA0_QM_ARB_MST_CRED_STS_19 0x508BFC 771 772#define mmDMA0_QM_ARB_MST_CRED_STS_20 0x508C00 773 774#define mmDMA0_QM_ARB_MST_CRED_STS_21 0x508C04 775 776#define mmDMA0_QM_ARB_MST_CRED_STS_22 0x508C08 777 778#define mmDMA0_QM_ARB_MST_CRED_STS_23 0x508C0C 779 780#define mmDMA0_QM_ARB_MST_CRED_STS_24 0x508C10 781 782#define mmDMA0_QM_ARB_MST_CRED_STS_25 0x508C14 783 784#define mmDMA0_QM_ARB_MST_CRED_STS_26 0x508C18 785 786#define mmDMA0_QM_ARB_MST_CRED_STS_27 0x508C1C 787 788#define mmDMA0_QM_ARB_MST_CRED_STS_28 0x508C20 789 790#define mmDMA0_QM_ARB_MST_CRED_STS_29 0x508C24 791 792#define mmDMA0_QM_ARB_MST_CRED_STS_30 0x508C28 793 794#define mmDMA0_QM_ARB_MST_CRED_STS_31 0x508C2C 795 796#define mmDMA0_QM_CGM_CFG 0x508C70 797 798#define mmDMA0_QM_CGM_STS 0x508C74 799 800#define mmDMA0_QM_CGM_CFG1 0x508C78 801 802#define mmDMA0_QM_LOCAL_RANGE_BASE 0x508C80 803 804#define mmDMA0_QM_LOCAL_RANGE_SIZE 0x508C84 805 806#define mmDMA0_QM_CSMR_STRICT_PRIO_CFG 0x508C90 807 808#define mmDMA0_QM_HBW_RD_RATE_LIM_CFG_1 0x508C94 809 810#define mmDMA0_QM_LBW_WR_RATE_LIM_CFG_0 0x508C98 811 812#define mmDMA0_QM_LBW_WR_RATE_LIM_CFG_1 0x508C9C 813 814#define mmDMA0_QM_HBW_RD_RATE_LIM_CFG_0 0x508CA0 815 816#define mmDMA0_QM_GLBL_AXCACHE 0x508CA4 817 818#define mmDMA0_QM_IND_GW_APB_CFG 0x508CB0 819 820#define mmDMA0_QM_IND_GW_APB_WDATA 0x508CB4 821 822#define mmDMA0_QM_IND_GW_APB_RDATA 0x508CB8 823 824#define mmDMA0_QM_IND_GW_APB_STATUS 0x508CBC 825 826#define mmDMA0_QM_GLBL_ERR_ADDR_LO 0x508CD0 827 828#define mmDMA0_QM_GLBL_ERR_ADDR_HI 0x508CD4 829 830#define mmDMA0_QM_GLBL_ERR_WDATA 0x508CD8 831 832#define mmDMA0_QM_GLBL_MEM_INIT_BUSY 0x508D00 833 834#endif /* ASIC_REG_DMA0_QM_REGS_H_ */