dma4_qm_regs.h (32569B)
1/* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2018 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8/************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13#ifndef ASIC_REG_DMA4_QM_REGS_H_ 14#define ASIC_REG_DMA4_QM_REGS_H_ 15 16/* 17 ***************************************** 18 * DMA4_QM (Prototype: QMAN) 19 ***************************************** 20 */ 21 22#define mmDMA4_QM_GLBL_CFG0 0x588000 23 24#define mmDMA4_QM_GLBL_CFG1 0x588004 25 26#define mmDMA4_QM_GLBL_PROT 0x588008 27 28#define mmDMA4_QM_GLBL_ERR_CFG 0x58800C 29 30#define mmDMA4_QM_GLBL_SECURE_PROPS_0 0x588010 31 32#define mmDMA4_QM_GLBL_SECURE_PROPS_1 0x588014 33 34#define mmDMA4_QM_GLBL_SECURE_PROPS_2 0x588018 35 36#define mmDMA4_QM_GLBL_SECURE_PROPS_3 0x58801C 37 38#define mmDMA4_QM_GLBL_SECURE_PROPS_4 0x588020 39 40#define mmDMA4_QM_GLBL_NON_SECURE_PROPS_0 0x588024 41 42#define mmDMA4_QM_GLBL_NON_SECURE_PROPS_1 0x588028 43 44#define mmDMA4_QM_GLBL_NON_SECURE_PROPS_2 0x58802C 45 46#define mmDMA4_QM_GLBL_NON_SECURE_PROPS_3 0x588030 47 48#define mmDMA4_QM_GLBL_NON_SECURE_PROPS_4 0x588034 49 50#define mmDMA4_QM_GLBL_STS0 0x588038 51 52#define mmDMA4_QM_GLBL_STS1_0 0x588040 53 54#define mmDMA4_QM_GLBL_STS1_1 0x588044 55 56#define mmDMA4_QM_GLBL_STS1_2 0x588048 57 58#define mmDMA4_QM_GLBL_STS1_3 0x58804C 59 60#define mmDMA4_QM_GLBL_STS1_4 0x588050 61 62#define mmDMA4_QM_GLBL_MSG_EN_0 0x588054 63 64#define mmDMA4_QM_GLBL_MSG_EN_1 0x588058 65 66#define mmDMA4_QM_GLBL_MSG_EN_2 0x58805C 67 68#define mmDMA4_QM_GLBL_MSG_EN_3 0x588060 69 70#define mmDMA4_QM_GLBL_MSG_EN_4 0x588068 71 72#define mmDMA4_QM_PQ_BASE_LO_0 0x588070 73 74#define mmDMA4_QM_PQ_BASE_LO_1 0x588074 75 76#define mmDMA4_QM_PQ_BASE_LO_2 0x588078 77 78#define mmDMA4_QM_PQ_BASE_LO_3 0x58807C 79 80#define mmDMA4_QM_PQ_BASE_HI_0 0x588080 81 82#define mmDMA4_QM_PQ_BASE_HI_1 0x588084 83 84#define mmDMA4_QM_PQ_BASE_HI_2 0x588088 85 86#define mmDMA4_QM_PQ_BASE_HI_3 0x58808C 87 88#define mmDMA4_QM_PQ_SIZE_0 0x588090 89 90#define mmDMA4_QM_PQ_SIZE_1 0x588094 91 92#define mmDMA4_QM_PQ_SIZE_2 0x588098 93 94#define mmDMA4_QM_PQ_SIZE_3 0x58809C 95 96#define mmDMA4_QM_PQ_PI_0 0x5880A0 97 98#define mmDMA4_QM_PQ_PI_1 0x5880A4 99 100#define mmDMA4_QM_PQ_PI_2 0x5880A8 101 102#define mmDMA4_QM_PQ_PI_3 0x5880AC 103 104#define mmDMA4_QM_PQ_CI_0 0x5880B0 105 106#define mmDMA4_QM_PQ_CI_1 0x5880B4 107 108#define mmDMA4_QM_PQ_CI_2 0x5880B8 109 110#define mmDMA4_QM_PQ_CI_3 0x5880BC 111 112#define mmDMA4_QM_PQ_CFG0_0 0x5880C0 113 114#define mmDMA4_QM_PQ_CFG0_1 0x5880C4 115 116#define mmDMA4_QM_PQ_CFG0_2 0x5880C8 117 118#define mmDMA4_QM_PQ_CFG0_3 0x5880CC 119 120#define mmDMA4_QM_PQ_CFG1_0 0x5880D0 121 122#define mmDMA4_QM_PQ_CFG1_1 0x5880D4 123 124#define mmDMA4_QM_PQ_CFG1_2 0x5880D8 125 126#define mmDMA4_QM_PQ_CFG1_3 0x5880DC 127 128#define mmDMA4_QM_PQ_ARUSER_31_11_0 0x5880E0 129 130#define mmDMA4_QM_PQ_ARUSER_31_11_1 0x5880E4 131 132#define mmDMA4_QM_PQ_ARUSER_31_11_2 0x5880E8 133 134#define mmDMA4_QM_PQ_ARUSER_31_11_3 0x5880EC 135 136#define mmDMA4_QM_PQ_STS0_0 0x5880F0 137 138#define mmDMA4_QM_PQ_STS0_1 0x5880F4 139 140#define mmDMA4_QM_PQ_STS0_2 0x5880F8 141 142#define mmDMA4_QM_PQ_STS0_3 0x5880FC 143 144#define mmDMA4_QM_PQ_STS1_0 0x588100 145 146#define mmDMA4_QM_PQ_STS1_1 0x588104 147 148#define mmDMA4_QM_PQ_STS1_2 0x588108 149 150#define mmDMA4_QM_PQ_STS1_3 0x58810C 151 152#define mmDMA4_QM_CQ_CFG0_0 0x588110 153 154#define mmDMA4_QM_CQ_CFG0_1 0x588114 155 156#define mmDMA4_QM_CQ_CFG0_2 0x588118 157 158#define mmDMA4_QM_CQ_CFG0_3 0x58811C 159 160#define mmDMA4_QM_CQ_CFG0_4 0x588120 161 162#define mmDMA4_QM_CQ_CFG1_0 0x588124 163 164#define mmDMA4_QM_CQ_CFG1_1 0x588128 165 166#define mmDMA4_QM_CQ_CFG1_2 0x58812C 167 168#define mmDMA4_QM_CQ_CFG1_3 0x588130 169 170#define mmDMA4_QM_CQ_CFG1_4 0x588134 171 172#define mmDMA4_QM_CQ_ARUSER_31_11_0 0x588138 173 174#define mmDMA4_QM_CQ_ARUSER_31_11_1 0x58813C 175 176#define mmDMA4_QM_CQ_ARUSER_31_11_2 0x588140 177 178#define mmDMA4_QM_CQ_ARUSER_31_11_3 0x588144 179 180#define mmDMA4_QM_CQ_ARUSER_31_11_4 0x588148 181 182#define mmDMA4_QM_CQ_STS0_0 0x58814C 183 184#define mmDMA4_QM_CQ_STS0_1 0x588150 185 186#define mmDMA4_QM_CQ_STS0_2 0x588154 187 188#define mmDMA4_QM_CQ_STS0_3 0x588158 189 190#define mmDMA4_QM_CQ_STS0_4 0x58815C 191 192#define mmDMA4_QM_CQ_STS1_0 0x588160 193 194#define mmDMA4_QM_CQ_STS1_1 0x588164 195 196#define mmDMA4_QM_CQ_STS1_2 0x588168 197 198#define mmDMA4_QM_CQ_STS1_3 0x58816C 199 200#define mmDMA4_QM_CQ_STS1_4 0x588170 201 202#define mmDMA4_QM_CQ_PTR_LO_0 0x588174 203 204#define mmDMA4_QM_CQ_PTR_HI_0 0x588178 205 206#define mmDMA4_QM_CQ_TSIZE_0 0x58817C 207 208#define mmDMA4_QM_CQ_CTL_0 0x588180 209 210#define mmDMA4_QM_CQ_PTR_LO_1 0x588184 211 212#define mmDMA4_QM_CQ_PTR_HI_1 0x588188 213 214#define mmDMA4_QM_CQ_TSIZE_1 0x58818C 215 216#define mmDMA4_QM_CQ_CTL_1 0x588190 217 218#define mmDMA4_QM_CQ_PTR_LO_2 0x588194 219 220#define mmDMA4_QM_CQ_PTR_HI_2 0x588198 221 222#define mmDMA4_QM_CQ_TSIZE_2 0x58819C 223 224#define mmDMA4_QM_CQ_CTL_2 0x5881A0 225 226#define mmDMA4_QM_CQ_PTR_LO_3 0x5881A4 227 228#define mmDMA4_QM_CQ_PTR_HI_3 0x5881A8 229 230#define mmDMA4_QM_CQ_TSIZE_3 0x5881AC 231 232#define mmDMA4_QM_CQ_CTL_3 0x5881B0 233 234#define mmDMA4_QM_CQ_PTR_LO_4 0x5881B4 235 236#define mmDMA4_QM_CQ_PTR_HI_4 0x5881B8 237 238#define mmDMA4_QM_CQ_TSIZE_4 0x5881BC 239 240#define mmDMA4_QM_CQ_CTL_4 0x5881C0 241 242#define mmDMA4_QM_CQ_PTR_LO_STS_0 0x5881C4 243 244#define mmDMA4_QM_CQ_PTR_LO_STS_1 0x5881C8 245 246#define mmDMA4_QM_CQ_PTR_LO_STS_2 0x5881CC 247 248#define mmDMA4_QM_CQ_PTR_LO_STS_3 0x5881D0 249 250#define mmDMA4_QM_CQ_PTR_LO_STS_4 0x5881D4 251 252#define mmDMA4_QM_CQ_PTR_HI_STS_0 0x5881D8 253 254#define mmDMA4_QM_CQ_PTR_HI_STS_1 0x5881DC 255 256#define mmDMA4_QM_CQ_PTR_HI_STS_2 0x5881E0 257 258#define mmDMA4_QM_CQ_PTR_HI_STS_3 0x5881E4 259 260#define mmDMA4_QM_CQ_PTR_HI_STS_4 0x5881E8 261 262#define mmDMA4_QM_CQ_TSIZE_STS_0 0x5881EC 263 264#define mmDMA4_QM_CQ_TSIZE_STS_1 0x5881F0 265 266#define mmDMA4_QM_CQ_TSIZE_STS_2 0x5881F4 267 268#define mmDMA4_QM_CQ_TSIZE_STS_3 0x5881F8 269 270#define mmDMA4_QM_CQ_TSIZE_STS_4 0x5881FC 271 272#define mmDMA4_QM_CQ_CTL_STS_0 0x588200 273 274#define mmDMA4_QM_CQ_CTL_STS_1 0x588204 275 276#define mmDMA4_QM_CQ_CTL_STS_2 0x588208 277 278#define mmDMA4_QM_CQ_CTL_STS_3 0x58820C 279 280#define mmDMA4_QM_CQ_CTL_STS_4 0x588210 281 282#define mmDMA4_QM_CQ_IFIFO_CNT_0 0x588214 283 284#define mmDMA4_QM_CQ_IFIFO_CNT_1 0x588218 285 286#define mmDMA4_QM_CQ_IFIFO_CNT_2 0x58821C 287 288#define mmDMA4_QM_CQ_IFIFO_CNT_3 0x588220 289 290#define mmDMA4_QM_CQ_IFIFO_CNT_4 0x588224 291 292#define mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_0 0x588228 293 294#define mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_1 0x58822C 295 296#define mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_2 0x588230 297 298#define mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_3 0x588234 299 300#define mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_4 0x588238 301 302#define mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_0 0x58823C 303 304#define mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_1 0x588240 305 306#define mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_2 0x588244 307 308#define mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_3 0x588248 309 310#define mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_4 0x58824C 311 312#define mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_0 0x588250 313 314#define mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_1 0x588254 315 316#define mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_2 0x588258 317 318#define mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_3 0x58825C 319 320#define mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_4 0x588260 321 322#define mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_0 0x588264 323 324#define mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_1 0x588268 325 326#define mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_2 0x58826C 327 328#define mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_3 0x588270 329 330#define mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_4 0x588274 331 332#define mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_0 0x588278 333 334#define mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_1 0x58827C 335 336#define mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_2 0x588280 337 338#define mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_3 0x588284 339 340#define mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_4 0x588288 341 342#define mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_0 0x58828C 343 344#define mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_1 0x588290 345 346#define mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_2 0x588294 347 348#define mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_3 0x588298 349 350#define mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_4 0x58829C 351 352#define mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_0 0x5882A0 353 354#define mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_1 0x5882A4 355 356#define mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_2 0x5882A8 357 358#define mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_3 0x5882AC 359 360#define mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_4 0x5882B0 361 362#define mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_0 0x5882B4 363 364#define mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_1 0x5882B8 365 366#define mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_2 0x5882BC 367 368#define mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_3 0x5882C0 369 370#define mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_4 0x5882C4 371 372#define mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_0 0x5882C8 373 374#define mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_1 0x5882CC 375 376#define mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_2 0x5882D0 377 378#define mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_3 0x5882D4 379 380#define mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_4 0x5882D8 381 382#define mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x5882E0 383 384#define mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x5882E4 385 386#define mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x5882E8 387 388#define mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x5882EC 389 390#define mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x5882F0 391 392#define mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x5882F4 393 394#define mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x5882F8 395 396#define mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x5882FC 397 398#define mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x588300 399 400#define mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x588304 401 402#define mmDMA4_QM_CP_FENCE0_RDATA_0 0x588308 403 404#define mmDMA4_QM_CP_FENCE0_RDATA_1 0x58830C 405 406#define mmDMA4_QM_CP_FENCE0_RDATA_2 0x588310 407 408#define mmDMA4_QM_CP_FENCE0_RDATA_3 0x588314 409 410#define mmDMA4_QM_CP_FENCE0_RDATA_4 0x588318 411 412#define mmDMA4_QM_CP_FENCE1_RDATA_0 0x58831C 413 414#define mmDMA4_QM_CP_FENCE1_RDATA_1 0x588320 415 416#define mmDMA4_QM_CP_FENCE1_RDATA_2 0x588324 417 418#define mmDMA4_QM_CP_FENCE1_RDATA_3 0x588328 419 420#define mmDMA4_QM_CP_FENCE1_RDATA_4 0x58832C 421 422#define mmDMA4_QM_CP_FENCE2_RDATA_0 0x588330 423 424#define mmDMA4_QM_CP_FENCE2_RDATA_1 0x588334 425 426#define mmDMA4_QM_CP_FENCE2_RDATA_2 0x588338 427 428#define mmDMA4_QM_CP_FENCE2_RDATA_3 0x58833C 429 430#define mmDMA4_QM_CP_FENCE2_RDATA_4 0x588340 431 432#define mmDMA4_QM_CP_FENCE3_RDATA_0 0x588344 433 434#define mmDMA4_QM_CP_FENCE3_RDATA_1 0x588348 435 436#define mmDMA4_QM_CP_FENCE3_RDATA_2 0x58834C 437 438#define mmDMA4_QM_CP_FENCE3_RDATA_3 0x588350 439 440#define mmDMA4_QM_CP_FENCE3_RDATA_4 0x588354 441 442#define mmDMA4_QM_CP_FENCE0_CNT_0 0x588358 443 444#define mmDMA4_QM_CP_FENCE0_CNT_1 0x58835C 445 446#define mmDMA4_QM_CP_FENCE0_CNT_2 0x588360 447 448#define mmDMA4_QM_CP_FENCE0_CNT_3 0x588364 449 450#define mmDMA4_QM_CP_FENCE0_CNT_4 0x588368 451 452#define mmDMA4_QM_CP_FENCE1_CNT_0 0x58836C 453 454#define mmDMA4_QM_CP_FENCE1_CNT_1 0x588370 455 456#define mmDMA4_QM_CP_FENCE1_CNT_2 0x588374 457 458#define mmDMA4_QM_CP_FENCE1_CNT_3 0x588378 459 460#define mmDMA4_QM_CP_FENCE1_CNT_4 0x58837C 461 462#define mmDMA4_QM_CP_FENCE2_CNT_0 0x588380 463 464#define mmDMA4_QM_CP_FENCE2_CNT_1 0x588384 465 466#define mmDMA4_QM_CP_FENCE2_CNT_2 0x588388 467 468#define mmDMA4_QM_CP_FENCE2_CNT_3 0x58838C 469 470#define mmDMA4_QM_CP_FENCE2_CNT_4 0x588390 471 472#define mmDMA4_QM_CP_FENCE3_CNT_0 0x588394 473 474#define mmDMA4_QM_CP_FENCE3_CNT_1 0x588398 475 476#define mmDMA4_QM_CP_FENCE3_CNT_2 0x58839C 477 478#define mmDMA4_QM_CP_FENCE3_CNT_3 0x5883A0 479 480#define mmDMA4_QM_CP_FENCE3_CNT_4 0x5883A4 481 482#define mmDMA4_QM_CP_STS_0 0x5883A8 483 484#define mmDMA4_QM_CP_STS_1 0x5883AC 485 486#define mmDMA4_QM_CP_STS_2 0x5883B0 487 488#define mmDMA4_QM_CP_STS_3 0x5883B4 489 490#define mmDMA4_QM_CP_STS_4 0x5883B8 491 492#define mmDMA4_QM_CP_CURRENT_INST_LO_0 0x5883BC 493 494#define mmDMA4_QM_CP_CURRENT_INST_LO_1 0x5883C0 495 496#define mmDMA4_QM_CP_CURRENT_INST_LO_2 0x5883C4 497 498#define mmDMA4_QM_CP_CURRENT_INST_LO_3 0x5883C8 499 500#define mmDMA4_QM_CP_CURRENT_INST_LO_4 0x5883CC 501 502#define mmDMA4_QM_CP_CURRENT_INST_HI_0 0x5883D0 503 504#define mmDMA4_QM_CP_CURRENT_INST_HI_1 0x5883D4 505 506#define mmDMA4_QM_CP_CURRENT_INST_HI_2 0x5883D8 507 508#define mmDMA4_QM_CP_CURRENT_INST_HI_3 0x5883DC 509 510#define mmDMA4_QM_CP_CURRENT_INST_HI_4 0x5883E0 511 512#define mmDMA4_QM_CP_BARRIER_CFG_0 0x5883F4 513 514#define mmDMA4_QM_CP_BARRIER_CFG_1 0x5883F8 515 516#define mmDMA4_QM_CP_BARRIER_CFG_2 0x5883FC 517 518#define mmDMA4_QM_CP_BARRIER_CFG_3 0x588400 519 520#define mmDMA4_QM_CP_BARRIER_CFG_4 0x588404 521 522#define mmDMA4_QM_CP_DBG_0_0 0x588408 523 524#define mmDMA4_QM_CP_DBG_0_1 0x58840C 525 526#define mmDMA4_QM_CP_DBG_0_2 0x588410 527 528#define mmDMA4_QM_CP_DBG_0_3 0x588414 529 530#define mmDMA4_QM_CP_DBG_0_4 0x588418 531 532#define mmDMA4_QM_CP_ARUSER_31_11_0 0x58841C 533 534#define mmDMA4_QM_CP_ARUSER_31_11_1 0x588420 535 536#define mmDMA4_QM_CP_ARUSER_31_11_2 0x588424 537 538#define mmDMA4_QM_CP_ARUSER_31_11_3 0x588428 539 540#define mmDMA4_QM_CP_ARUSER_31_11_4 0x58842C 541 542#define mmDMA4_QM_CP_AWUSER_31_11_0 0x588430 543 544#define mmDMA4_QM_CP_AWUSER_31_11_1 0x588434 545 546#define mmDMA4_QM_CP_AWUSER_31_11_2 0x588438 547 548#define mmDMA4_QM_CP_AWUSER_31_11_3 0x58843C 549 550#define mmDMA4_QM_CP_AWUSER_31_11_4 0x588440 551 552#define mmDMA4_QM_ARB_CFG_0 0x588A00 553 554#define mmDMA4_QM_ARB_CHOISE_Q_PUSH 0x588A04 555 556#define mmDMA4_QM_ARB_WRR_WEIGHT_0 0x588A08 557 558#define mmDMA4_QM_ARB_WRR_WEIGHT_1 0x588A0C 559 560#define mmDMA4_QM_ARB_WRR_WEIGHT_2 0x588A10 561 562#define mmDMA4_QM_ARB_WRR_WEIGHT_3 0x588A14 563 564#define mmDMA4_QM_ARB_CFG_1 0x588A18 565 566#define mmDMA4_QM_ARB_MST_AVAIL_CRED_0 0x588A20 567 568#define mmDMA4_QM_ARB_MST_AVAIL_CRED_1 0x588A24 569 570#define mmDMA4_QM_ARB_MST_AVAIL_CRED_2 0x588A28 571 572#define mmDMA4_QM_ARB_MST_AVAIL_CRED_3 0x588A2C 573 574#define mmDMA4_QM_ARB_MST_AVAIL_CRED_4 0x588A30 575 576#define mmDMA4_QM_ARB_MST_AVAIL_CRED_5 0x588A34 577 578#define mmDMA4_QM_ARB_MST_AVAIL_CRED_6 0x588A38 579 580#define mmDMA4_QM_ARB_MST_AVAIL_CRED_7 0x588A3C 581 582#define mmDMA4_QM_ARB_MST_AVAIL_CRED_8 0x588A40 583 584#define mmDMA4_QM_ARB_MST_AVAIL_CRED_9 0x588A44 585 586#define mmDMA4_QM_ARB_MST_AVAIL_CRED_10 0x588A48 587 588#define mmDMA4_QM_ARB_MST_AVAIL_CRED_11 0x588A4C 589 590#define mmDMA4_QM_ARB_MST_AVAIL_CRED_12 0x588A50 591 592#define mmDMA4_QM_ARB_MST_AVAIL_CRED_13 0x588A54 593 594#define mmDMA4_QM_ARB_MST_AVAIL_CRED_14 0x588A58 595 596#define mmDMA4_QM_ARB_MST_AVAIL_CRED_15 0x588A5C 597 598#define mmDMA4_QM_ARB_MST_AVAIL_CRED_16 0x588A60 599 600#define mmDMA4_QM_ARB_MST_AVAIL_CRED_17 0x588A64 601 602#define mmDMA4_QM_ARB_MST_AVAIL_CRED_18 0x588A68 603 604#define mmDMA4_QM_ARB_MST_AVAIL_CRED_19 0x588A6C 605 606#define mmDMA4_QM_ARB_MST_AVAIL_CRED_20 0x588A70 607 608#define mmDMA4_QM_ARB_MST_AVAIL_CRED_21 0x588A74 609 610#define mmDMA4_QM_ARB_MST_AVAIL_CRED_22 0x588A78 611 612#define mmDMA4_QM_ARB_MST_AVAIL_CRED_23 0x588A7C 613 614#define mmDMA4_QM_ARB_MST_AVAIL_CRED_24 0x588A80 615 616#define mmDMA4_QM_ARB_MST_AVAIL_CRED_25 0x588A84 617 618#define mmDMA4_QM_ARB_MST_AVAIL_CRED_26 0x588A88 619 620#define mmDMA4_QM_ARB_MST_AVAIL_CRED_27 0x588A8C 621 622#define mmDMA4_QM_ARB_MST_AVAIL_CRED_28 0x588A90 623 624#define mmDMA4_QM_ARB_MST_AVAIL_CRED_29 0x588A94 625 626#define mmDMA4_QM_ARB_MST_AVAIL_CRED_30 0x588A98 627 628#define mmDMA4_QM_ARB_MST_AVAIL_CRED_31 0x588A9C 629 630#define mmDMA4_QM_ARB_MST_CRED_INC 0x588AA0 631 632#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x588AA4 633 634#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x588AA8 635 636#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x588AAC 637 638#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x588AB0 639 640#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x588AB4 641 642#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x588AB8 643 644#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x588ABC 645 646#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x588AC0 647 648#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x588AC4 649 650#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x588AC8 651 652#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x588ACC 653 654#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x588AD0 655 656#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x588AD4 657 658#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x588AD8 659 660#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x588ADC 661 662#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x588AE0 663 664#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x588AE4 665 666#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x588AE8 667 668#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x588AEC 669 670#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x588AF0 671 672#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x588AF4 673 674#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x588AF8 675 676#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x588AFC 677 678#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x588B00 679 680#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x588B04 681 682#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x588B08 683 684#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x588B0C 685 686#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x588B10 687 688#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x588B14 689 690#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x588B18 691 692#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x588B1C 693 694#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x588B20 695 696#define mmDMA4_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x588B28 697 698#define mmDMA4_QM_ARB_MST_SLAVE_EN 0x588B2C 699 700#define mmDMA4_QM_ARB_MST_QUIET_PER 0x588B34 701 702#define mmDMA4_QM_ARB_SLV_CHOISE_WDT 0x588B38 703 704#define mmDMA4_QM_ARB_SLV_ID 0x588B3C 705 706#define mmDMA4_QM_ARB_MSG_MAX_INFLIGHT 0x588B44 707 708#define mmDMA4_QM_ARB_MSG_AWUSER_31_11 0x588B48 709 710#define mmDMA4_QM_ARB_MSG_AWUSER_SEC_PROP 0x588B4C 711 712#define mmDMA4_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x588B50 713 714#define mmDMA4_QM_ARB_BASE_LO 0x588B54 715 716#define mmDMA4_QM_ARB_BASE_HI 0x588B58 717 718#define mmDMA4_QM_ARB_STATE_STS 0x588B80 719 720#define mmDMA4_QM_ARB_CHOISE_FULLNESS_STS 0x588B84 721 722#define mmDMA4_QM_ARB_MSG_STS 0x588B88 723 724#define mmDMA4_QM_ARB_SLV_CHOISE_Q_HEAD 0x588B8C 725 726#define mmDMA4_QM_ARB_ERR_CAUSE 0x588B9C 727 728#define mmDMA4_QM_ARB_ERR_MSG_EN 0x588BA0 729 730#define mmDMA4_QM_ARB_ERR_STS_DRP 0x588BA8 731 732#define mmDMA4_QM_ARB_MST_CRED_STS_0 0x588BB0 733 734#define mmDMA4_QM_ARB_MST_CRED_STS_1 0x588BB4 735 736#define mmDMA4_QM_ARB_MST_CRED_STS_2 0x588BB8 737 738#define mmDMA4_QM_ARB_MST_CRED_STS_3 0x588BBC 739 740#define mmDMA4_QM_ARB_MST_CRED_STS_4 0x588BC0 741 742#define mmDMA4_QM_ARB_MST_CRED_STS_5 0x588BC4 743 744#define mmDMA4_QM_ARB_MST_CRED_STS_6 0x588BC8 745 746#define mmDMA4_QM_ARB_MST_CRED_STS_7 0x588BCC 747 748#define mmDMA4_QM_ARB_MST_CRED_STS_8 0x588BD0 749 750#define mmDMA4_QM_ARB_MST_CRED_STS_9 0x588BD4 751 752#define mmDMA4_QM_ARB_MST_CRED_STS_10 0x588BD8 753 754#define mmDMA4_QM_ARB_MST_CRED_STS_11 0x588BDC 755 756#define mmDMA4_QM_ARB_MST_CRED_STS_12 0x588BE0 757 758#define mmDMA4_QM_ARB_MST_CRED_STS_13 0x588BE4 759 760#define mmDMA4_QM_ARB_MST_CRED_STS_14 0x588BE8 761 762#define mmDMA4_QM_ARB_MST_CRED_STS_15 0x588BEC 763 764#define mmDMA4_QM_ARB_MST_CRED_STS_16 0x588BF0 765 766#define mmDMA4_QM_ARB_MST_CRED_STS_17 0x588BF4 767 768#define mmDMA4_QM_ARB_MST_CRED_STS_18 0x588BF8 769 770#define mmDMA4_QM_ARB_MST_CRED_STS_19 0x588BFC 771 772#define mmDMA4_QM_ARB_MST_CRED_STS_20 0x588C00 773 774#define mmDMA4_QM_ARB_MST_CRED_STS_21 0x588C04 775 776#define mmDMA4_QM_ARB_MST_CRED_STS_22 0x588C08 777 778#define mmDMA4_QM_ARB_MST_CRED_STS_23 0x588C0C 779 780#define mmDMA4_QM_ARB_MST_CRED_STS_24 0x588C10 781 782#define mmDMA4_QM_ARB_MST_CRED_STS_25 0x588C14 783 784#define mmDMA4_QM_ARB_MST_CRED_STS_26 0x588C18 785 786#define mmDMA4_QM_ARB_MST_CRED_STS_27 0x588C1C 787 788#define mmDMA4_QM_ARB_MST_CRED_STS_28 0x588C20 789 790#define mmDMA4_QM_ARB_MST_CRED_STS_29 0x588C24 791 792#define mmDMA4_QM_ARB_MST_CRED_STS_30 0x588C28 793 794#define mmDMA4_QM_ARB_MST_CRED_STS_31 0x588C2C 795 796#define mmDMA4_QM_CGM_CFG 0x588C70 797 798#define mmDMA4_QM_CGM_STS 0x588C74 799 800#define mmDMA4_QM_CGM_CFG1 0x588C78 801 802#define mmDMA4_QM_LOCAL_RANGE_BASE 0x588C80 803 804#define mmDMA4_QM_LOCAL_RANGE_SIZE 0x588C84 805 806#define mmDMA4_QM_CSMR_STRICT_PRIO_CFG 0x588C90 807 808#define mmDMA4_QM_HBW_RD_RATE_LIM_CFG_1 0x588C94 809 810#define mmDMA4_QM_LBW_WR_RATE_LIM_CFG_0 0x588C98 811 812#define mmDMA4_QM_LBW_WR_RATE_LIM_CFG_1 0x588C9C 813 814#define mmDMA4_QM_HBW_RD_RATE_LIM_CFG_0 0x588CA0 815 816#define mmDMA4_QM_GLBL_AXCACHE 0x588CA4 817 818#define mmDMA4_QM_IND_GW_APB_CFG 0x588CB0 819 820#define mmDMA4_QM_IND_GW_APB_WDATA 0x588CB4 821 822#define mmDMA4_QM_IND_GW_APB_RDATA 0x588CB8 823 824#define mmDMA4_QM_IND_GW_APB_STATUS 0x588CBC 825 826#define mmDMA4_QM_GLBL_ERR_ADDR_LO 0x588CD0 827 828#define mmDMA4_QM_GLBL_ERR_ADDR_HI 0x588CD4 829 830#define mmDMA4_QM_GLBL_ERR_WDATA 0x588CD8 831 832#define mmDMA4_QM_GLBL_MEM_INIT_BUSY 0x588D00 833 834#endif /* ASIC_REG_DMA4_QM_REGS_H_ */