gaudi_blocks.h (303071B)
1/* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2018 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8/************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13#ifndef GAUDI_BLOCKS_H_ 14#define GAUDI_BLOCKS_H_ 15 16#define mmNIC0_PHY0_BASE 0x0ull 17#define NIC0_PHY0_MAX_OFFSET 0x9F13 18#define mmMME0_ACC_BASE 0x7FFC020000ull 19#define MME0_ACC_MAX_OFFSET 0x5C00 20#define MME0_ACC_SECTION 0x20000 21#define mmMME0_SBAB_BASE 0x7FFC040000ull 22#define MME0_SBAB_MAX_OFFSET 0x5800 23#define MME0_SBAB_SECTION 0x1000 24#define mmMME0_PRTN_BASE 0x7FFC041000ull 25#define MME0_PRTN_MAX_OFFSET 0x5000 26#define MME0_PRTN_SECTION 0x1F000 27#define mmMME0_CTRL_BASE 0x7FFC060000ull 28#define MME0_CTRL_MAX_OFFSET 0xDA80 29#define MME0_CTRL_SECTION 0x8000 30#define mmARCH_MME0_CTRL_BASE 0x7FFC060008ull 31#define ARCH_MME0_CTRL_MAX_OFFSET 0x3400 32#define ARCH_MME0_CTRL_SECTION 0x3400 33#define mmARCH_TENSOR_S_MME0_CTRL_BASE 0x7FFC06003Cull 34#define ARCH_TENSOR_S_MME0_CTRL_MAX_OFFSET 0x4C00 35#define ARCH_TENSOR_S_MME0_CTRL_SECTION 0x4C00 36#define mmARCH_AGU_S_MME0_CTRL_BASE 0x7FFC060088ull 37#define ARCH_AGU_S_MME0_CTRL_MAX_OFFSET 0x2400 38#define ARCH_AGU_S_MME0_CTRL_SECTION 0x2400 39#define mmARCH_TENSOR_L_MME0_CTRL_BASE 0x7FFC0600ACull 40#define ARCH_TENSOR_L_MME0_CTRL_MAX_OFFSET 0x4C00 41#define ARCH_TENSOR_L_MME0_CTRL_SECTION 0x4C00 42#define mmARCH_AGU_L_LOCAL_MME0_CTRL_BASE 0x7FFC0600F8ull 43#define ARCH_AGU_L_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400 44#define ARCH_AGU_L_LOCAL_MME0_CTRL_SECTION 0x2400 45#define mmARCH_AGU_L_REMOTE_MME0_CTRL_BASE 0x7FFC06011Cull 46#define ARCH_AGU_L_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400 47#define ARCH_AGU_L_REMOTE_MME0_CTRL_SECTION 0x2400 48#define mmARCH_TENSOR_O_MME0_CTRL_BASE 0x7FFC060140ull 49#define ARCH_TENSOR_O_MME0_CTRL_MAX_OFFSET 0x4C00 50#define ARCH_TENSOR_O_MME0_CTRL_SECTION 0x4C00 51#define mmARCH_AGU_O_LOCAL_MME0_CTRL_BASE 0x7FFC06018Cull 52#define ARCH_AGU_O_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400 53#define ARCH_AGU_O_LOCAL_MME0_CTRL_SECTION 0x2400 54#define mmARCH_AGU_O_REMOTE_MME0_CTRL_BASE 0x7FFC0601B0ull 55#define ARCH_AGU_O_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400 56#define ARCH_AGU_O_REMOTE_MME0_CTRL_SECTION 0x2400 57#define mmARCH_DESC_MME0_CTRL_BASE 0x7FFC0601D4ull 58#define ARCH_DESC_MME0_CTRL_MAX_OFFSET 0x5400 59#define ARCH_DESC_MME0_CTRL_SECTION 0x2340 60#define mmSHADOW_0_MME0_CTRL_BASE 0x7FFC060408ull 61#define SHADOW_0_MME0_CTRL_MAX_OFFSET 0x3400 62#define SHADOW_0_MME0_CTRL_SECTION 0x3400 63#define mmSHADOW_0_TENSOR_S_MME0_CTRL_BASE 0x7FFC06043Cull 64#define SHADOW_0_TENSOR_S_MME0_CTRL_MAX_OFFSET 0x4C00 65#define SHADOW_0_TENSOR_S_MME0_CTRL_SECTION 0x4C00 66#define mmSHADOW_0_AGU_S_MME0_CTRL_BASE 0x7FFC060488ull 67#define SHADOW_0_AGU_S_MME0_CTRL_MAX_OFFSET 0x2400 68#define SHADOW_0_AGU_S_MME0_CTRL_SECTION 0x2400 69#define mmSHADOW_0_TENSOR_L_MME0_CTRL_BASE 0x7FFC0604ACull 70#define SHADOW_0_TENSOR_L_MME0_CTRL_MAX_OFFSET 0x4C00 71#define SHADOW_0_TENSOR_L_MME0_CTRL_SECTION 0x4C00 72#define mmSHADOW_0_AGU_L_LOCAL_MME0_CTRL_BASE 0x7FFC0604F8ull 73#define SHADOW_0_AGU_L_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400 74#define SHADOW_0_AGU_L_LOCAL_MME0_CTRL_SECTION 0x2400 75#define mmSHADOW_0_AGU_L_REMOTE_MME0_CTRL_BASE 0x7FFC06051Cull 76#define SHADOW_0_AGU_L_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400 77#define SHADOW_0_AGU_L_REMOTE_MME0_CTRL_SECTION 0x2400 78#define mmSHADOW_0_TENSOR_O_MME0_CTRL_BASE 0x7FFC060540ull 79#define SHADOW_0_TENSOR_O_MME0_CTRL_MAX_OFFSET 0x4C00 80#define SHADOW_0_TENSOR_O_MME0_CTRL_SECTION 0x4C00 81#define mmSHADOW_0_AGU_O_LOCAL_MME0_CTRL_BASE 0x7FFC06058Cull 82#define SHADOW_0_AGU_O_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400 83#define SHADOW_0_AGU_O_LOCAL_MME0_CTRL_SECTION 0x2400 84#define mmSHADOW_0_AGU_O_REMOTE_MME0_CTRL_BASE 0x7FFC0605B0ull 85#define SHADOW_0_AGU_O_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400 86#define SHADOW_0_AGU_O_REMOTE_MME0_CTRL_SECTION 0x2400 87#define mmSHADOW_0_DESC_MME0_CTRL_BASE 0x7FFC0605D4ull 88#define SHADOW_0_DESC_MME0_CTRL_MAX_OFFSET 0x5400 89#define SHADOW_0_DESC_MME0_CTRL_SECTION 0xB400 90#define mmSHADOW_1_MME0_CTRL_BASE 0x7FFC060688ull 91#define SHADOW_1_MME0_CTRL_MAX_OFFSET 0x3400 92#define SHADOW_1_MME0_CTRL_SECTION 0x3400 93#define mmSHADOW_1_TENSOR_S_MME0_CTRL_BASE 0x7FFC0606BCull 94#define SHADOW_1_TENSOR_S_MME0_CTRL_MAX_OFFSET 0x4C00 95#define SHADOW_1_TENSOR_S_MME0_CTRL_SECTION 0x4C00 96#define mmSHADOW_1_AGU_S_MME0_CTRL_BASE 0x7FFC060708ull 97#define SHADOW_1_AGU_S_MME0_CTRL_MAX_OFFSET 0x2400 98#define SHADOW_1_AGU_S_MME0_CTRL_SECTION 0x2400 99#define mmSHADOW_1_TENSOR_L_MME0_CTRL_BASE 0x7FFC06072Cull 100#define SHADOW_1_TENSOR_L_MME0_CTRL_MAX_OFFSET 0x4C00 101#define SHADOW_1_TENSOR_L_MME0_CTRL_SECTION 0x4C00 102#define mmSHADOW_1_AGU_L_LOCAL_MME0_CTRL_BASE 0x7FFC060778ull 103#define SHADOW_1_AGU_L_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400 104#define SHADOW_1_AGU_L_LOCAL_MME0_CTRL_SECTION 0x2400 105#define mmSHADOW_1_AGU_L_REMOTE_MME0_CTRL_BASE 0x7FFC06079Cull 106#define SHADOW_1_AGU_L_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400 107#define SHADOW_1_AGU_L_REMOTE_MME0_CTRL_SECTION 0x2400 108#define mmSHADOW_1_TENSOR_O_MME0_CTRL_BASE 0x7FFC0607C0ull 109#define SHADOW_1_TENSOR_O_MME0_CTRL_MAX_OFFSET 0x4C00 110#define SHADOW_1_TENSOR_O_MME0_CTRL_SECTION 0x4C00 111#define mmSHADOW_1_AGU_O_LOCAL_MME0_CTRL_BASE 0x7FFC06080Cull 112#define SHADOW_1_AGU_O_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400 113#define SHADOW_1_AGU_O_LOCAL_MME0_CTRL_SECTION 0x2400 114#define mmSHADOW_1_AGU_O_REMOTE_MME0_CTRL_BASE 0x7FFC060830ull 115#define SHADOW_1_AGU_O_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400 116#define SHADOW_1_AGU_O_REMOTE_MME0_CTRL_SECTION 0x2400 117#define mmSHADOW_1_DESC_MME0_CTRL_BASE 0x7FFC060854ull 118#define SHADOW_1_DESC_MME0_CTRL_MAX_OFFSET 0x5400 119#define SHADOW_1_DESC_MME0_CTRL_SECTION 0xB400 120#define mmSHADOW_2_MME0_CTRL_BASE 0x7FFC060908ull 121#define SHADOW_2_MME0_CTRL_MAX_OFFSET 0x3400 122#define SHADOW_2_MME0_CTRL_SECTION 0x3400 123#define mmSHADOW_2_TENSOR_S_MME0_CTRL_BASE 0x7FFC06093Cull 124#define SHADOW_2_TENSOR_S_MME0_CTRL_MAX_OFFSET 0x4C00 125#define SHADOW_2_TENSOR_S_MME0_CTRL_SECTION 0x4C00 126#define mmSHADOW_2_AGU_S_MME0_CTRL_BASE 0x7FFC060988ull 127#define SHADOW_2_AGU_S_MME0_CTRL_MAX_OFFSET 0x2400 128#define SHADOW_2_AGU_S_MME0_CTRL_SECTION 0x2400 129#define mmSHADOW_2_TENSOR_L_MME0_CTRL_BASE 0x7FFC0609ACull 130#define SHADOW_2_TENSOR_L_MME0_CTRL_MAX_OFFSET 0x4C00 131#define SHADOW_2_TENSOR_L_MME0_CTRL_SECTION 0x4C00 132#define mmSHADOW_2_AGU_L_LOCAL_MME0_CTRL_BASE 0x7FFC0609F8ull 133#define SHADOW_2_AGU_L_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400 134#define SHADOW_2_AGU_L_LOCAL_MME0_CTRL_SECTION 0x2400 135#define mmSHADOW_2_AGU_L_REMOTE_MME0_CTRL_BASE 0x7FFC060A1Cull 136#define SHADOW_2_AGU_L_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400 137#define SHADOW_2_AGU_L_REMOTE_MME0_CTRL_SECTION 0x2400 138#define mmSHADOW_2_TENSOR_O_MME0_CTRL_BASE 0x7FFC060A40ull 139#define SHADOW_2_TENSOR_O_MME0_CTRL_MAX_OFFSET 0x4C00 140#define SHADOW_2_TENSOR_O_MME0_CTRL_SECTION 0x4C00 141#define mmSHADOW_2_AGU_O_LOCAL_MME0_CTRL_BASE 0x7FFC060A8Cull 142#define SHADOW_2_AGU_O_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400 143#define SHADOW_2_AGU_O_LOCAL_MME0_CTRL_SECTION 0x2400 144#define mmSHADOW_2_AGU_O_REMOTE_MME0_CTRL_BASE 0x7FFC060AB0ull 145#define SHADOW_2_AGU_O_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400 146#define SHADOW_2_AGU_O_REMOTE_MME0_CTRL_SECTION 0x2400 147#define mmSHADOW_2_DESC_MME0_CTRL_BASE 0x7FFC060AD4ull 148#define SHADOW_2_DESC_MME0_CTRL_MAX_OFFSET 0x5400 149#define SHADOW_2_DESC_MME0_CTRL_SECTION 0xB400 150#define mmSHADOW_3_MME0_CTRL_BASE 0x7FFC060B88ull 151#define SHADOW_3_MME0_CTRL_MAX_OFFSET 0x3400 152#define SHADOW_3_MME0_CTRL_SECTION 0x3400 153#define mmSHADOW_3_TENSOR_S_MME0_CTRL_BASE 0x7FFC060BBCull 154#define SHADOW_3_TENSOR_S_MME0_CTRL_MAX_OFFSET 0x4C00 155#define SHADOW_3_TENSOR_S_MME0_CTRL_SECTION 0x4C00 156#define mmSHADOW_3_AGU_S_MME0_CTRL_BASE 0x7FFC060C08ull 157#define SHADOW_3_AGU_S_MME0_CTRL_MAX_OFFSET 0x2400 158#define SHADOW_3_AGU_S_MME0_CTRL_SECTION 0x2400 159#define mmSHADOW_3_TENSOR_L_MME0_CTRL_BASE 0x7FFC060C2Cull 160#define SHADOW_3_TENSOR_L_MME0_CTRL_MAX_OFFSET 0x4C00 161#define SHADOW_3_TENSOR_L_MME0_CTRL_SECTION 0x4C00 162#define mmSHADOW_3_AGU_L_LOCAL_MME0_CTRL_BASE 0x7FFC060C78ull 163#define SHADOW_3_AGU_L_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400 164#define SHADOW_3_AGU_L_LOCAL_MME0_CTRL_SECTION 0x2400 165#define mmSHADOW_3_AGU_L_REMOTE_MME0_CTRL_BASE 0x7FFC060C9Cull 166#define SHADOW_3_AGU_L_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400 167#define SHADOW_3_AGU_L_REMOTE_MME0_CTRL_SECTION 0x2400 168#define mmSHADOW_3_TENSOR_O_MME0_CTRL_BASE 0x7FFC060CC0ull 169#define SHADOW_3_TENSOR_O_MME0_CTRL_MAX_OFFSET 0x4C00 170#define SHADOW_3_TENSOR_O_MME0_CTRL_SECTION 0x4C00 171#define mmSHADOW_3_AGU_O_LOCAL_MME0_CTRL_BASE 0x7FFC060D0Cull 172#define SHADOW_3_AGU_O_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400 173#define SHADOW_3_AGU_O_LOCAL_MME0_CTRL_SECTION 0x2400 174#define mmSHADOW_3_AGU_O_REMOTE_MME0_CTRL_BASE 0x7FFC060D30ull 175#define SHADOW_3_AGU_O_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400 176#define SHADOW_3_AGU_O_REMOTE_MME0_CTRL_SECTION 0x2400 177#define mmSHADOW_3_DESC_MME0_CTRL_BASE 0x7FFC060D54ull 178#define SHADOW_3_DESC_MME0_CTRL_MAX_OFFSET 0x5400 179#define SHADOW_3_DESC_MME0_CTRL_SECTION 0x72AC 180#define mmMME0_QM_BASE 0x7FFC068000ull 181#define MME0_QM_MAX_OFFSET 0xD040 182#define MME0_QM_SECTION 0x38000 183#define mmMME1_ACC_BASE 0x7FFC0A0000ull 184#define MME1_ACC_MAX_OFFSET 0x5C00 185#define MME1_ACC_SECTION 0x20000 186#define mmMME1_SBAB_BASE 0x7FFC0C0000ull 187#define MME1_SBAB_MAX_OFFSET 0x5800 188#define MME1_SBAB_SECTION 0x1000 189#define mmMME1_PRTN_BASE 0x7FFC0C1000ull 190#define MME1_PRTN_MAX_OFFSET 0x5000 191#define MME1_PRTN_SECTION 0x1F000 192#define mmMME1_CTRL_BASE 0x7FFC0E0000ull 193#define MME1_CTRL_MAX_OFFSET 0xDA80 194#define MME1_CTRL_SECTION 0x8000 195#define mmARCH_MME1_CTRL_BASE 0x7FFC0E0008ull 196#define ARCH_MME1_CTRL_MAX_OFFSET 0x3400 197#define ARCH_MME1_CTRL_SECTION 0x3400 198#define mmARCH_TENSOR_S_MME1_CTRL_BASE 0x7FFC0E003Cull 199#define ARCH_TENSOR_S_MME1_CTRL_MAX_OFFSET 0x4C00 200#define ARCH_TENSOR_S_MME1_CTRL_SECTION 0x4C00 201#define mmARCH_AGU_S_MME1_CTRL_BASE 0x7FFC0E0088ull 202#define ARCH_AGU_S_MME1_CTRL_MAX_OFFSET 0x2400 203#define ARCH_AGU_S_MME1_CTRL_SECTION 0x2400 204#define mmARCH_TENSOR_L_MME1_CTRL_BASE 0x7FFC0E00ACull 205#define ARCH_TENSOR_L_MME1_CTRL_MAX_OFFSET 0x4C00 206#define ARCH_TENSOR_L_MME1_CTRL_SECTION 0x4C00 207#define mmARCH_AGU_L_LOCAL_MME1_CTRL_BASE 0x7FFC0E00F8ull 208#define ARCH_AGU_L_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400 209#define ARCH_AGU_L_LOCAL_MME1_CTRL_SECTION 0x2400 210#define mmARCH_AGU_L_REMOTE_MME1_CTRL_BASE 0x7FFC0E011Cull 211#define ARCH_AGU_L_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400 212#define ARCH_AGU_L_REMOTE_MME1_CTRL_SECTION 0x2400 213#define mmARCH_TENSOR_O_MME1_CTRL_BASE 0x7FFC0E0140ull 214#define ARCH_TENSOR_O_MME1_CTRL_MAX_OFFSET 0x4C00 215#define ARCH_TENSOR_O_MME1_CTRL_SECTION 0x4C00 216#define mmARCH_AGU_O_LOCAL_MME1_CTRL_BASE 0x7FFC0E018Cull 217#define ARCH_AGU_O_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400 218#define ARCH_AGU_O_LOCAL_MME1_CTRL_SECTION 0x2400 219#define mmARCH_AGU_O_REMOTE_MME1_CTRL_BASE 0x7FFC0E01B0ull 220#define ARCH_AGU_O_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400 221#define ARCH_AGU_O_REMOTE_MME1_CTRL_SECTION 0x2400 222#define mmARCH_DESC_MME1_CTRL_BASE 0x7FFC0E01D4ull 223#define ARCH_DESC_MME1_CTRL_MAX_OFFSET 0x5400 224#define ARCH_DESC_MME1_CTRL_SECTION 0x2340 225#define mmSHADOW_0_MME1_CTRL_BASE 0x7FFC0E0408ull 226#define SHADOW_0_MME1_CTRL_MAX_OFFSET 0x3400 227#define SHADOW_0_MME1_CTRL_SECTION 0x3400 228#define mmSHADOW_0_TENSOR_S_MME1_CTRL_BASE 0x7FFC0E043Cull 229#define SHADOW_0_TENSOR_S_MME1_CTRL_MAX_OFFSET 0x4C00 230#define SHADOW_0_TENSOR_S_MME1_CTRL_SECTION 0x4C00 231#define mmSHADOW_0_AGU_S_MME1_CTRL_BASE 0x7FFC0E0488ull 232#define SHADOW_0_AGU_S_MME1_CTRL_MAX_OFFSET 0x2400 233#define SHADOW_0_AGU_S_MME1_CTRL_SECTION 0x2400 234#define mmSHADOW_0_TENSOR_L_MME1_CTRL_BASE 0x7FFC0E04ACull 235#define SHADOW_0_TENSOR_L_MME1_CTRL_MAX_OFFSET 0x4C00 236#define SHADOW_0_TENSOR_L_MME1_CTRL_SECTION 0x4C00 237#define mmSHADOW_0_AGU_L_LOCAL_MME1_CTRL_BASE 0x7FFC0E04F8ull 238#define SHADOW_0_AGU_L_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400 239#define SHADOW_0_AGU_L_LOCAL_MME1_CTRL_SECTION 0x2400 240#define mmSHADOW_0_AGU_L_REMOTE_MME1_CTRL_BASE 0x7FFC0E051Cull 241#define SHADOW_0_AGU_L_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400 242#define SHADOW_0_AGU_L_REMOTE_MME1_CTRL_SECTION 0x2400 243#define mmSHADOW_0_TENSOR_O_MME1_CTRL_BASE 0x7FFC0E0540ull 244#define SHADOW_0_TENSOR_O_MME1_CTRL_MAX_OFFSET 0x4C00 245#define SHADOW_0_TENSOR_O_MME1_CTRL_SECTION 0x4C00 246#define mmSHADOW_0_AGU_O_LOCAL_MME1_CTRL_BASE 0x7FFC0E058Cull 247#define SHADOW_0_AGU_O_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400 248#define SHADOW_0_AGU_O_LOCAL_MME1_CTRL_SECTION 0x2400 249#define mmSHADOW_0_AGU_O_REMOTE_MME1_CTRL_BASE 0x7FFC0E05B0ull 250#define SHADOW_0_AGU_O_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400 251#define SHADOW_0_AGU_O_REMOTE_MME1_CTRL_SECTION 0x2400 252#define mmSHADOW_0_DESC_MME1_CTRL_BASE 0x7FFC0E05D4ull 253#define SHADOW_0_DESC_MME1_CTRL_MAX_OFFSET 0x5400 254#define SHADOW_0_DESC_MME1_CTRL_SECTION 0xB400 255#define mmSHADOW_1_MME1_CTRL_BASE 0x7FFC0E0688ull 256#define SHADOW_1_MME1_CTRL_MAX_OFFSET 0x3400 257#define SHADOW_1_MME1_CTRL_SECTION 0x3400 258#define mmSHADOW_1_TENSOR_S_MME1_CTRL_BASE 0x7FFC0E06BCull 259#define SHADOW_1_TENSOR_S_MME1_CTRL_MAX_OFFSET 0x4C00 260#define SHADOW_1_TENSOR_S_MME1_CTRL_SECTION 0x4C00 261#define mmSHADOW_1_AGU_S_MME1_CTRL_BASE 0x7FFC0E0708ull 262#define SHADOW_1_AGU_S_MME1_CTRL_MAX_OFFSET 0x2400 263#define SHADOW_1_AGU_S_MME1_CTRL_SECTION 0x2400 264#define mmSHADOW_1_TENSOR_L_MME1_CTRL_BASE 0x7FFC0E072Cull 265#define SHADOW_1_TENSOR_L_MME1_CTRL_MAX_OFFSET 0x4C00 266#define SHADOW_1_TENSOR_L_MME1_CTRL_SECTION 0x4C00 267#define mmSHADOW_1_AGU_L_LOCAL_MME1_CTRL_BASE 0x7FFC0E0778ull 268#define SHADOW_1_AGU_L_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400 269#define SHADOW_1_AGU_L_LOCAL_MME1_CTRL_SECTION 0x2400 270#define mmSHADOW_1_AGU_L_REMOTE_MME1_CTRL_BASE 0x7FFC0E079Cull 271#define SHADOW_1_AGU_L_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400 272#define SHADOW_1_AGU_L_REMOTE_MME1_CTRL_SECTION 0x2400 273#define mmSHADOW_1_TENSOR_O_MME1_CTRL_BASE 0x7FFC0E07C0ull 274#define SHADOW_1_TENSOR_O_MME1_CTRL_MAX_OFFSET 0x4C00 275#define SHADOW_1_TENSOR_O_MME1_CTRL_SECTION 0x4C00 276#define mmSHADOW_1_AGU_O_LOCAL_MME1_CTRL_BASE 0x7FFC0E080Cull 277#define SHADOW_1_AGU_O_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400 278#define SHADOW_1_AGU_O_LOCAL_MME1_CTRL_SECTION 0x2400 279#define mmSHADOW_1_AGU_O_REMOTE_MME1_CTRL_BASE 0x7FFC0E0830ull 280#define SHADOW_1_AGU_O_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400 281#define SHADOW_1_AGU_O_REMOTE_MME1_CTRL_SECTION 0x2400 282#define mmSHADOW_1_DESC_MME1_CTRL_BASE 0x7FFC0E0854ull 283#define SHADOW_1_DESC_MME1_CTRL_MAX_OFFSET 0x5400 284#define SHADOW_1_DESC_MME1_CTRL_SECTION 0xB400 285#define mmSHADOW_2_MME1_CTRL_BASE 0x7FFC0E0908ull 286#define SHADOW_2_MME1_CTRL_MAX_OFFSET 0x3400 287#define SHADOW_2_MME1_CTRL_SECTION 0x3400 288#define mmSHADOW_2_TENSOR_S_MME1_CTRL_BASE 0x7FFC0E093Cull 289#define SHADOW_2_TENSOR_S_MME1_CTRL_MAX_OFFSET 0x4C00 290#define SHADOW_2_TENSOR_S_MME1_CTRL_SECTION 0x4C00 291#define mmSHADOW_2_AGU_S_MME1_CTRL_BASE 0x7FFC0E0988ull 292#define SHADOW_2_AGU_S_MME1_CTRL_MAX_OFFSET 0x2400 293#define SHADOW_2_AGU_S_MME1_CTRL_SECTION 0x2400 294#define mmSHADOW_2_TENSOR_L_MME1_CTRL_BASE 0x7FFC0E09ACull 295#define SHADOW_2_TENSOR_L_MME1_CTRL_MAX_OFFSET 0x4C00 296#define SHADOW_2_TENSOR_L_MME1_CTRL_SECTION 0x4C00 297#define mmSHADOW_2_AGU_L_LOCAL_MME1_CTRL_BASE 0x7FFC0E09F8ull 298#define SHADOW_2_AGU_L_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400 299#define SHADOW_2_AGU_L_LOCAL_MME1_CTRL_SECTION 0x2400 300#define mmSHADOW_2_AGU_L_REMOTE_MME1_CTRL_BASE 0x7FFC0E0A1Cull 301#define SHADOW_2_AGU_L_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400 302#define SHADOW_2_AGU_L_REMOTE_MME1_CTRL_SECTION 0x2400 303#define mmSHADOW_2_TENSOR_O_MME1_CTRL_BASE 0x7FFC0E0A40ull 304#define SHADOW_2_TENSOR_O_MME1_CTRL_MAX_OFFSET 0x4C00 305#define SHADOW_2_TENSOR_O_MME1_CTRL_SECTION 0x4C00 306#define mmSHADOW_2_AGU_O_LOCAL_MME1_CTRL_BASE 0x7FFC0E0A8Cull 307#define SHADOW_2_AGU_O_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400 308#define SHADOW_2_AGU_O_LOCAL_MME1_CTRL_SECTION 0x2400 309#define mmSHADOW_2_AGU_O_REMOTE_MME1_CTRL_BASE 0x7FFC0E0AB0ull 310#define SHADOW_2_AGU_O_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400 311#define SHADOW_2_AGU_O_REMOTE_MME1_CTRL_SECTION 0x2400 312#define mmSHADOW_2_DESC_MME1_CTRL_BASE 0x7FFC0E0AD4ull 313#define SHADOW_2_DESC_MME1_CTRL_MAX_OFFSET 0x5400 314#define SHADOW_2_DESC_MME1_CTRL_SECTION 0xB400 315#define mmSHADOW_3_MME1_CTRL_BASE 0x7FFC0E0B88ull 316#define SHADOW_3_MME1_CTRL_MAX_OFFSET 0x3400 317#define SHADOW_3_MME1_CTRL_SECTION 0x3400 318#define mmSHADOW_3_TENSOR_S_MME1_CTRL_BASE 0x7FFC0E0BBCull 319#define SHADOW_3_TENSOR_S_MME1_CTRL_MAX_OFFSET 0x4C00 320#define SHADOW_3_TENSOR_S_MME1_CTRL_SECTION 0x4C00 321#define mmSHADOW_3_AGU_S_MME1_CTRL_BASE 0x7FFC0E0C08ull 322#define SHADOW_3_AGU_S_MME1_CTRL_MAX_OFFSET 0x2400 323#define SHADOW_3_AGU_S_MME1_CTRL_SECTION 0x2400 324#define mmSHADOW_3_TENSOR_L_MME1_CTRL_BASE 0x7FFC0E0C2Cull 325#define SHADOW_3_TENSOR_L_MME1_CTRL_MAX_OFFSET 0x4C00 326#define SHADOW_3_TENSOR_L_MME1_CTRL_SECTION 0x4C00 327#define mmSHADOW_3_AGU_L_LOCAL_MME1_CTRL_BASE 0x7FFC0E0C78ull 328#define SHADOW_3_AGU_L_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400 329#define SHADOW_3_AGU_L_LOCAL_MME1_CTRL_SECTION 0x2400 330#define mmSHADOW_3_AGU_L_REMOTE_MME1_CTRL_BASE 0x7FFC0E0C9Cull 331#define SHADOW_3_AGU_L_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400 332#define SHADOW_3_AGU_L_REMOTE_MME1_CTRL_SECTION 0x2400 333#define mmSHADOW_3_TENSOR_O_MME1_CTRL_BASE 0x7FFC0E0CC0ull 334#define SHADOW_3_TENSOR_O_MME1_CTRL_MAX_OFFSET 0x4C00 335#define SHADOW_3_TENSOR_O_MME1_CTRL_SECTION 0x4C00 336#define mmSHADOW_3_AGU_O_LOCAL_MME1_CTRL_BASE 0x7FFC0E0D0Cull 337#define SHADOW_3_AGU_O_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400 338#define SHADOW_3_AGU_O_LOCAL_MME1_CTRL_SECTION 0x2400 339#define mmSHADOW_3_AGU_O_REMOTE_MME1_CTRL_BASE 0x7FFC0E0D30ull 340#define SHADOW_3_AGU_O_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400 341#define SHADOW_3_AGU_O_REMOTE_MME1_CTRL_SECTION 0x2400 342#define mmSHADOW_3_DESC_MME1_CTRL_BASE 0x7FFC0E0D54ull 343#define SHADOW_3_DESC_MME1_CTRL_MAX_OFFSET 0x5400 344#define SHADOW_3_DESC_MME1_CTRL_SECTION 0x72AC 345#define mmMME1_QM_BASE 0x7FFC0E8000ull 346#define MME1_QM_MAX_OFFSET 0xD040 347#define MME1_QM_SECTION 0x38000 348#define mmMME2_ACC_BASE 0x7FFC120000ull 349#define MME2_ACC_MAX_OFFSET 0x5C00 350#define MME2_ACC_SECTION 0x20000 351#define mmMME2_SBAB_BASE 0x7FFC140000ull 352#define MME2_SBAB_MAX_OFFSET 0x5800 353#define MME2_SBAB_SECTION 0x1000 354#define mmMME2_PRTN_BASE 0x7FFC141000ull 355#define MME2_PRTN_MAX_OFFSET 0x5000 356#define MME2_PRTN_SECTION 0x1F000 357#define mmMME2_CTRL_BASE 0x7FFC160000ull 358#define MME2_CTRL_MAX_OFFSET 0xDA80 359#define MME2_CTRL_SECTION 0x8000 360#define mmARCH_MME2_CTRL_BASE 0x7FFC160008ull 361#define ARCH_MME2_CTRL_MAX_OFFSET 0x3400 362#define ARCH_MME2_CTRL_SECTION 0x3400 363#define mmARCH_TENSOR_S_MME2_CTRL_BASE 0x7FFC16003Cull 364#define ARCH_TENSOR_S_MME2_CTRL_MAX_OFFSET 0x4C00 365#define ARCH_TENSOR_S_MME2_CTRL_SECTION 0x4C00 366#define mmARCH_AGU_S_MME2_CTRL_BASE 0x7FFC160088ull 367#define ARCH_AGU_S_MME2_CTRL_MAX_OFFSET 0x2400 368#define ARCH_AGU_S_MME2_CTRL_SECTION 0x2400 369#define mmARCH_TENSOR_L_MME2_CTRL_BASE 0x7FFC1600ACull 370#define ARCH_TENSOR_L_MME2_CTRL_MAX_OFFSET 0x4C00 371#define ARCH_TENSOR_L_MME2_CTRL_SECTION 0x4C00 372#define mmARCH_AGU_L_LOCAL_MME2_CTRL_BASE 0x7FFC1600F8ull 373#define ARCH_AGU_L_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400 374#define ARCH_AGU_L_LOCAL_MME2_CTRL_SECTION 0x2400 375#define mmARCH_AGU_L_REMOTE_MME2_CTRL_BASE 0x7FFC16011Cull 376#define ARCH_AGU_L_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400 377#define ARCH_AGU_L_REMOTE_MME2_CTRL_SECTION 0x2400 378#define mmARCH_TENSOR_O_MME2_CTRL_BASE 0x7FFC160140ull 379#define ARCH_TENSOR_O_MME2_CTRL_MAX_OFFSET 0x4C00 380#define ARCH_TENSOR_O_MME2_CTRL_SECTION 0x4C00 381#define mmARCH_AGU_O_LOCAL_MME2_CTRL_BASE 0x7FFC16018Cull 382#define ARCH_AGU_O_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400 383#define ARCH_AGU_O_LOCAL_MME2_CTRL_SECTION 0x2400 384#define mmARCH_AGU_O_REMOTE_MME2_CTRL_BASE 0x7FFC1601B0ull 385#define ARCH_AGU_O_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400 386#define ARCH_AGU_O_REMOTE_MME2_CTRL_SECTION 0x2400 387#define mmARCH_DESC_MME2_CTRL_BASE 0x7FFC1601D4ull 388#define ARCH_DESC_MME2_CTRL_MAX_OFFSET 0x5400 389#define ARCH_DESC_MME2_CTRL_SECTION 0x2340 390#define mmSHADOW_0_MME2_CTRL_BASE 0x7FFC160408ull 391#define SHADOW_0_MME2_CTRL_MAX_OFFSET 0x3400 392#define SHADOW_0_MME2_CTRL_SECTION 0x3400 393#define mmSHADOW_0_TENSOR_S_MME2_CTRL_BASE 0x7FFC16043Cull 394#define SHADOW_0_TENSOR_S_MME2_CTRL_MAX_OFFSET 0x4C00 395#define SHADOW_0_TENSOR_S_MME2_CTRL_SECTION 0x4C00 396#define mmSHADOW_0_AGU_S_MME2_CTRL_BASE 0x7FFC160488ull 397#define SHADOW_0_AGU_S_MME2_CTRL_MAX_OFFSET 0x2400 398#define SHADOW_0_AGU_S_MME2_CTRL_SECTION 0x2400 399#define mmSHADOW_0_TENSOR_L_MME2_CTRL_BASE 0x7FFC1604ACull 400#define SHADOW_0_TENSOR_L_MME2_CTRL_MAX_OFFSET 0x4C00 401#define SHADOW_0_TENSOR_L_MME2_CTRL_SECTION 0x4C00 402#define mmSHADOW_0_AGU_L_LOCAL_MME2_CTRL_BASE 0x7FFC1604F8ull 403#define SHADOW_0_AGU_L_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400 404#define SHADOW_0_AGU_L_LOCAL_MME2_CTRL_SECTION 0x2400 405#define mmSHADOW_0_AGU_L_REMOTE_MME2_CTRL_BASE 0x7FFC16051Cull 406#define SHADOW_0_AGU_L_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400 407#define SHADOW_0_AGU_L_REMOTE_MME2_CTRL_SECTION 0x2400 408#define mmSHADOW_0_TENSOR_O_MME2_CTRL_BASE 0x7FFC160540ull 409#define SHADOW_0_TENSOR_O_MME2_CTRL_MAX_OFFSET 0x4C00 410#define SHADOW_0_TENSOR_O_MME2_CTRL_SECTION 0x4C00 411#define mmSHADOW_0_AGU_O_LOCAL_MME2_CTRL_BASE 0x7FFC16058Cull 412#define SHADOW_0_AGU_O_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400 413#define SHADOW_0_AGU_O_LOCAL_MME2_CTRL_SECTION 0x2400 414#define mmSHADOW_0_AGU_O_REMOTE_MME2_CTRL_BASE 0x7FFC1605B0ull 415#define SHADOW_0_AGU_O_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400 416#define SHADOW_0_AGU_O_REMOTE_MME2_CTRL_SECTION 0x2400 417#define mmSHADOW_0_DESC_MME2_CTRL_BASE 0x7FFC1605D4ull 418#define SHADOW_0_DESC_MME2_CTRL_MAX_OFFSET 0x5400 419#define SHADOW_0_DESC_MME2_CTRL_SECTION 0xB400 420#define mmSHADOW_1_MME2_CTRL_BASE 0x7FFC160688ull 421#define SHADOW_1_MME2_CTRL_MAX_OFFSET 0x3400 422#define SHADOW_1_MME2_CTRL_SECTION 0x3400 423#define mmSHADOW_1_TENSOR_S_MME2_CTRL_BASE 0x7FFC1606BCull 424#define SHADOW_1_TENSOR_S_MME2_CTRL_MAX_OFFSET 0x4C00 425#define SHADOW_1_TENSOR_S_MME2_CTRL_SECTION 0x4C00 426#define mmSHADOW_1_AGU_S_MME2_CTRL_BASE 0x7FFC160708ull 427#define SHADOW_1_AGU_S_MME2_CTRL_MAX_OFFSET 0x2400 428#define SHADOW_1_AGU_S_MME2_CTRL_SECTION 0x2400 429#define mmSHADOW_1_TENSOR_L_MME2_CTRL_BASE 0x7FFC16072Cull 430#define SHADOW_1_TENSOR_L_MME2_CTRL_MAX_OFFSET 0x4C00 431#define SHADOW_1_TENSOR_L_MME2_CTRL_SECTION 0x4C00 432#define mmSHADOW_1_AGU_L_LOCAL_MME2_CTRL_BASE 0x7FFC160778ull 433#define SHADOW_1_AGU_L_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400 434#define SHADOW_1_AGU_L_LOCAL_MME2_CTRL_SECTION 0x2400 435#define mmSHADOW_1_AGU_L_REMOTE_MME2_CTRL_BASE 0x7FFC16079Cull 436#define SHADOW_1_AGU_L_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400 437#define SHADOW_1_AGU_L_REMOTE_MME2_CTRL_SECTION 0x2400 438#define mmSHADOW_1_TENSOR_O_MME2_CTRL_BASE 0x7FFC1607C0ull 439#define SHADOW_1_TENSOR_O_MME2_CTRL_MAX_OFFSET 0x4C00 440#define SHADOW_1_TENSOR_O_MME2_CTRL_SECTION 0x4C00 441#define mmSHADOW_1_AGU_O_LOCAL_MME2_CTRL_BASE 0x7FFC16080Cull 442#define SHADOW_1_AGU_O_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400 443#define SHADOW_1_AGU_O_LOCAL_MME2_CTRL_SECTION 0x2400 444#define mmSHADOW_1_AGU_O_REMOTE_MME2_CTRL_BASE 0x7FFC160830ull 445#define SHADOW_1_AGU_O_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400 446#define SHADOW_1_AGU_O_REMOTE_MME2_CTRL_SECTION 0x2400 447#define mmSHADOW_1_DESC_MME2_CTRL_BASE 0x7FFC160854ull 448#define SHADOW_1_DESC_MME2_CTRL_MAX_OFFSET 0x5400 449#define SHADOW_1_DESC_MME2_CTRL_SECTION 0xB400 450#define mmSHADOW_2_MME2_CTRL_BASE 0x7FFC160908ull 451#define SHADOW_2_MME2_CTRL_MAX_OFFSET 0x3400 452#define SHADOW_2_MME2_CTRL_SECTION 0x3400 453#define mmSHADOW_2_TENSOR_S_MME2_CTRL_BASE 0x7FFC16093Cull 454#define SHADOW_2_TENSOR_S_MME2_CTRL_MAX_OFFSET 0x4C00 455#define SHADOW_2_TENSOR_S_MME2_CTRL_SECTION 0x4C00 456#define mmSHADOW_2_AGU_S_MME2_CTRL_BASE 0x7FFC160988ull 457#define SHADOW_2_AGU_S_MME2_CTRL_MAX_OFFSET 0x2400 458#define SHADOW_2_AGU_S_MME2_CTRL_SECTION 0x2400 459#define mmSHADOW_2_TENSOR_L_MME2_CTRL_BASE 0x7FFC1609ACull 460#define SHADOW_2_TENSOR_L_MME2_CTRL_MAX_OFFSET 0x4C00 461#define SHADOW_2_TENSOR_L_MME2_CTRL_SECTION 0x4C00 462#define mmSHADOW_2_AGU_L_LOCAL_MME2_CTRL_BASE 0x7FFC1609F8ull 463#define SHADOW_2_AGU_L_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400 464#define SHADOW_2_AGU_L_LOCAL_MME2_CTRL_SECTION 0x2400 465#define mmSHADOW_2_AGU_L_REMOTE_MME2_CTRL_BASE 0x7FFC160A1Cull 466#define SHADOW_2_AGU_L_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400 467#define SHADOW_2_AGU_L_REMOTE_MME2_CTRL_SECTION 0x2400 468#define mmSHADOW_2_TENSOR_O_MME2_CTRL_BASE 0x7FFC160A40ull 469#define SHADOW_2_TENSOR_O_MME2_CTRL_MAX_OFFSET 0x4C00 470#define SHADOW_2_TENSOR_O_MME2_CTRL_SECTION 0x4C00 471#define mmSHADOW_2_AGU_O_LOCAL_MME2_CTRL_BASE 0x7FFC160A8Cull 472#define SHADOW_2_AGU_O_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400 473#define SHADOW_2_AGU_O_LOCAL_MME2_CTRL_SECTION 0x2400 474#define mmSHADOW_2_AGU_O_REMOTE_MME2_CTRL_BASE 0x7FFC160AB0ull 475#define SHADOW_2_AGU_O_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400 476#define SHADOW_2_AGU_O_REMOTE_MME2_CTRL_SECTION 0x2400 477#define mmSHADOW_2_DESC_MME2_CTRL_BASE 0x7FFC160AD4ull 478#define SHADOW_2_DESC_MME2_CTRL_MAX_OFFSET 0x5400 479#define SHADOW_2_DESC_MME2_CTRL_SECTION 0xB400 480#define mmSHADOW_3_MME2_CTRL_BASE 0x7FFC160B88ull 481#define SHADOW_3_MME2_CTRL_MAX_OFFSET 0x3400 482#define SHADOW_3_MME2_CTRL_SECTION 0x3400 483#define mmSHADOW_3_TENSOR_S_MME2_CTRL_BASE 0x7FFC160BBCull 484#define SHADOW_3_TENSOR_S_MME2_CTRL_MAX_OFFSET 0x4C00 485#define SHADOW_3_TENSOR_S_MME2_CTRL_SECTION 0x4C00 486#define mmSHADOW_3_AGU_S_MME2_CTRL_BASE 0x7FFC160C08ull 487#define SHADOW_3_AGU_S_MME2_CTRL_MAX_OFFSET 0x2400 488#define SHADOW_3_AGU_S_MME2_CTRL_SECTION 0x2400 489#define mmSHADOW_3_TENSOR_L_MME2_CTRL_BASE 0x7FFC160C2Cull 490#define SHADOW_3_TENSOR_L_MME2_CTRL_MAX_OFFSET 0x4C00 491#define SHADOW_3_TENSOR_L_MME2_CTRL_SECTION 0x4C00 492#define mmSHADOW_3_AGU_L_LOCAL_MME2_CTRL_BASE 0x7FFC160C78ull 493#define SHADOW_3_AGU_L_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400 494#define SHADOW_3_AGU_L_LOCAL_MME2_CTRL_SECTION 0x2400 495#define mmSHADOW_3_AGU_L_REMOTE_MME2_CTRL_BASE 0x7FFC160C9Cull 496#define SHADOW_3_AGU_L_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400 497#define SHADOW_3_AGU_L_REMOTE_MME2_CTRL_SECTION 0x2400 498#define mmSHADOW_3_TENSOR_O_MME2_CTRL_BASE 0x7FFC160CC0ull 499#define SHADOW_3_TENSOR_O_MME2_CTRL_MAX_OFFSET 0x4C00 500#define SHADOW_3_TENSOR_O_MME2_CTRL_SECTION 0x4C00 501#define mmSHADOW_3_AGU_O_LOCAL_MME2_CTRL_BASE 0x7FFC160D0Cull 502#define SHADOW_3_AGU_O_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400 503#define SHADOW_3_AGU_O_LOCAL_MME2_CTRL_SECTION 0x2400 504#define mmSHADOW_3_AGU_O_REMOTE_MME2_CTRL_BASE 0x7FFC160D30ull 505#define SHADOW_3_AGU_O_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400 506#define SHADOW_3_AGU_O_REMOTE_MME2_CTRL_SECTION 0x2400 507#define mmSHADOW_3_DESC_MME2_CTRL_BASE 0x7FFC160D54ull 508#define SHADOW_3_DESC_MME2_CTRL_MAX_OFFSET 0x5400 509#define SHADOW_3_DESC_MME2_CTRL_SECTION 0x72AC 510#define mmMME2_QM_BASE 0x7FFC168000ull 511#define MME2_QM_MAX_OFFSET 0xD040 512#define MME2_QM_SECTION 0x38000 513#define mmMME3_ACC_BASE 0x7FFC1A0000ull 514#define MME3_ACC_MAX_OFFSET 0x5C00 515#define MME3_ACC_SECTION 0x20000 516#define mmMME3_SBAB_BASE 0x7FFC1C0000ull 517#define MME3_SBAB_MAX_OFFSET 0x5800 518#define MME3_SBAB_SECTION 0x1000 519#define mmMME3_PRTN_BASE 0x7FFC1C1000ull 520#define MME3_PRTN_MAX_OFFSET 0x5000 521#define MME3_PRTN_SECTION 0x1F000 522#define mmMME3_CTRL_BASE 0x7FFC1E0000ull 523#define MME3_CTRL_MAX_OFFSET 0xDA80 524#define MME3_CTRL_SECTION 0x8000 525#define mmARCH_MME3_CTRL_BASE 0x7FFC1E0008ull 526#define ARCH_MME3_CTRL_MAX_OFFSET 0x3400 527#define ARCH_MME3_CTRL_SECTION 0x3400 528#define mmARCH_TENSOR_S_MME3_CTRL_BASE 0x7FFC1E003Cull 529#define ARCH_TENSOR_S_MME3_CTRL_MAX_OFFSET 0x4C00 530#define ARCH_TENSOR_S_MME3_CTRL_SECTION 0x4C00 531#define mmARCH_AGU_S_MME3_CTRL_BASE 0x7FFC1E0088ull 532#define ARCH_AGU_S_MME3_CTRL_MAX_OFFSET 0x2400 533#define ARCH_AGU_S_MME3_CTRL_SECTION 0x2400 534#define mmARCH_TENSOR_L_MME3_CTRL_BASE 0x7FFC1E00ACull 535#define ARCH_TENSOR_L_MME3_CTRL_MAX_OFFSET 0x4C00 536#define ARCH_TENSOR_L_MME3_CTRL_SECTION 0x4C00 537#define mmARCH_AGU_L_LOCAL_MME3_CTRL_BASE 0x7FFC1E00F8ull 538#define ARCH_AGU_L_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400 539#define ARCH_AGU_L_LOCAL_MME3_CTRL_SECTION 0x2400 540#define mmARCH_AGU_L_REMOTE_MME3_CTRL_BASE 0x7FFC1E011Cull 541#define ARCH_AGU_L_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400 542#define ARCH_AGU_L_REMOTE_MME3_CTRL_SECTION 0x2400 543#define mmARCH_TENSOR_O_MME3_CTRL_BASE 0x7FFC1E0140ull 544#define ARCH_TENSOR_O_MME3_CTRL_MAX_OFFSET 0x4C00 545#define ARCH_TENSOR_O_MME3_CTRL_SECTION 0x4C00 546#define mmARCH_AGU_O_LOCAL_MME3_CTRL_BASE 0x7FFC1E018Cull 547#define ARCH_AGU_O_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400 548#define ARCH_AGU_O_LOCAL_MME3_CTRL_SECTION 0x2400 549#define mmARCH_AGU_O_REMOTE_MME3_CTRL_BASE 0x7FFC1E01B0ull 550#define ARCH_AGU_O_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400 551#define ARCH_AGU_O_REMOTE_MME3_CTRL_SECTION 0x2400 552#define mmARCH_DESC_MME3_CTRL_BASE 0x7FFC1E01D4ull 553#define ARCH_DESC_MME3_CTRL_MAX_OFFSET 0x5400 554#define ARCH_DESC_MME3_CTRL_SECTION 0x2340 555#define mmSHADOW_0_MME3_CTRL_BASE 0x7FFC1E0408ull 556#define SHADOW_0_MME3_CTRL_MAX_OFFSET 0x3400 557#define SHADOW_0_MME3_CTRL_SECTION 0x3400 558#define mmSHADOW_0_TENSOR_S_MME3_CTRL_BASE 0x7FFC1E043Cull 559#define SHADOW_0_TENSOR_S_MME3_CTRL_MAX_OFFSET 0x4C00 560#define SHADOW_0_TENSOR_S_MME3_CTRL_SECTION 0x4C00 561#define mmSHADOW_0_AGU_S_MME3_CTRL_BASE 0x7FFC1E0488ull 562#define SHADOW_0_AGU_S_MME3_CTRL_MAX_OFFSET 0x2400 563#define SHADOW_0_AGU_S_MME3_CTRL_SECTION 0x2400 564#define mmSHADOW_0_TENSOR_L_MME3_CTRL_BASE 0x7FFC1E04ACull 565#define SHADOW_0_TENSOR_L_MME3_CTRL_MAX_OFFSET 0x4C00 566#define SHADOW_0_TENSOR_L_MME3_CTRL_SECTION 0x4C00 567#define mmSHADOW_0_AGU_L_LOCAL_MME3_CTRL_BASE 0x7FFC1E04F8ull 568#define SHADOW_0_AGU_L_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400 569#define SHADOW_0_AGU_L_LOCAL_MME3_CTRL_SECTION 0x2400 570#define mmSHADOW_0_AGU_L_REMOTE_MME3_CTRL_BASE 0x7FFC1E051Cull 571#define SHADOW_0_AGU_L_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400 572#define SHADOW_0_AGU_L_REMOTE_MME3_CTRL_SECTION 0x2400 573#define mmSHADOW_0_TENSOR_O_MME3_CTRL_BASE 0x7FFC1E0540ull 574#define SHADOW_0_TENSOR_O_MME3_CTRL_MAX_OFFSET 0x4C00 575#define SHADOW_0_TENSOR_O_MME3_CTRL_SECTION 0x4C00 576#define mmSHADOW_0_AGU_O_LOCAL_MME3_CTRL_BASE 0x7FFC1E058Cull 577#define SHADOW_0_AGU_O_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400 578#define SHADOW_0_AGU_O_LOCAL_MME3_CTRL_SECTION 0x2400 579#define mmSHADOW_0_AGU_O_REMOTE_MME3_CTRL_BASE 0x7FFC1E05B0ull 580#define SHADOW_0_AGU_O_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400 581#define SHADOW_0_AGU_O_REMOTE_MME3_CTRL_SECTION 0x2400 582#define mmSHADOW_0_DESC_MME3_CTRL_BASE 0x7FFC1E05D4ull 583#define SHADOW_0_DESC_MME3_CTRL_MAX_OFFSET 0x5400 584#define SHADOW_0_DESC_MME3_CTRL_SECTION 0xB400 585#define mmSHADOW_1_MME3_CTRL_BASE 0x7FFC1E0688ull 586#define SHADOW_1_MME3_CTRL_MAX_OFFSET 0x3400 587#define SHADOW_1_MME3_CTRL_SECTION 0x3400 588#define mmSHADOW_1_TENSOR_S_MME3_CTRL_BASE 0x7FFC1E06BCull 589#define SHADOW_1_TENSOR_S_MME3_CTRL_MAX_OFFSET 0x4C00 590#define SHADOW_1_TENSOR_S_MME3_CTRL_SECTION 0x4C00 591#define mmSHADOW_1_AGU_S_MME3_CTRL_BASE 0x7FFC1E0708ull 592#define SHADOW_1_AGU_S_MME3_CTRL_MAX_OFFSET 0x2400 593#define SHADOW_1_AGU_S_MME3_CTRL_SECTION 0x2400 594#define mmSHADOW_1_TENSOR_L_MME3_CTRL_BASE 0x7FFC1E072Cull 595#define SHADOW_1_TENSOR_L_MME3_CTRL_MAX_OFFSET 0x4C00 596#define SHADOW_1_TENSOR_L_MME3_CTRL_SECTION 0x4C00 597#define mmSHADOW_1_AGU_L_LOCAL_MME3_CTRL_BASE 0x7FFC1E0778ull 598#define SHADOW_1_AGU_L_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400 599#define SHADOW_1_AGU_L_LOCAL_MME3_CTRL_SECTION 0x2400 600#define mmSHADOW_1_AGU_L_REMOTE_MME3_CTRL_BASE 0x7FFC1E079Cull 601#define SHADOW_1_AGU_L_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400 602#define SHADOW_1_AGU_L_REMOTE_MME3_CTRL_SECTION 0x2400 603#define mmSHADOW_1_TENSOR_O_MME3_CTRL_BASE 0x7FFC1E07C0ull 604#define SHADOW_1_TENSOR_O_MME3_CTRL_MAX_OFFSET 0x4C00 605#define SHADOW_1_TENSOR_O_MME3_CTRL_SECTION 0x4C00 606#define mmSHADOW_1_AGU_O_LOCAL_MME3_CTRL_BASE 0x7FFC1E080Cull 607#define SHADOW_1_AGU_O_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400 608#define SHADOW_1_AGU_O_LOCAL_MME3_CTRL_SECTION 0x2400 609#define mmSHADOW_1_AGU_O_REMOTE_MME3_CTRL_BASE 0x7FFC1E0830ull 610#define SHADOW_1_AGU_O_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400 611#define SHADOW_1_AGU_O_REMOTE_MME3_CTRL_SECTION 0x2400 612#define mmSHADOW_1_DESC_MME3_CTRL_BASE 0x7FFC1E0854ull 613#define SHADOW_1_DESC_MME3_CTRL_MAX_OFFSET 0x5400 614#define SHADOW_1_DESC_MME3_CTRL_SECTION 0xB400 615#define mmSHADOW_2_MME3_CTRL_BASE 0x7FFC1E0908ull 616#define SHADOW_2_MME3_CTRL_MAX_OFFSET 0x3400 617#define SHADOW_2_MME3_CTRL_SECTION 0x3400 618#define mmSHADOW_2_TENSOR_S_MME3_CTRL_BASE 0x7FFC1E093Cull 619#define SHADOW_2_TENSOR_S_MME3_CTRL_MAX_OFFSET 0x4C00 620#define SHADOW_2_TENSOR_S_MME3_CTRL_SECTION 0x4C00 621#define mmSHADOW_2_AGU_S_MME3_CTRL_BASE 0x7FFC1E0988ull 622#define SHADOW_2_AGU_S_MME3_CTRL_MAX_OFFSET 0x2400 623#define SHADOW_2_AGU_S_MME3_CTRL_SECTION 0x2400 624#define mmSHADOW_2_TENSOR_L_MME3_CTRL_BASE 0x7FFC1E09ACull 625#define SHADOW_2_TENSOR_L_MME3_CTRL_MAX_OFFSET 0x4C00 626#define SHADOW_2_TENSOR_L_MME3_CTRL_SECTION 0x4C00 627#define mmSHADOW_2_AGU_L_LOCAL_MME3_CTRL_BASE 0x7FFC1E09F8ull 628#define SHADOW_2_AGU_L_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400 629#define SHADOW_2_AGU_L_LOCAL_MME3_CTRL_SECTION 0x2400 630#define mmSHADOW_2_AGU_L_REMOTE_MME3_CTRL_BASE 0x7FFC1E0A1Cull 631#define SHADOW_2_AGU_L_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400 632#define SHADOW_2_AGU_L_REMOTE_MME3_CTRL_SECTION 0x2400 633#define mmSHADOW_2_TENSOR_O_MME3_CTRL_BASE 0x7FFC1E0A40ull 634#define SHADOW_2_TENSOR_O_MME3_CTRL_MAX_OFFSET 0x4C00 635#define SHADOW_2_TENSOR_O_MME3_CTRL_SECTION 0x4C00 636#define mmSHADOW_2_AGU_O_LOCAL_MME3_CTRL_BASE 0x7FFC1E0A8Cull 637#define SHADOW_2_AGU_O_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400 638#define SHADOW_2_AGU_O_LOCAL_MME3_CTRL_SECTION 0x2400 639#define mmSHADOW_2_AGU_O_REMOTE_MME3_CTRL_BASE 0x7FFC1E0AB0ull 640#define SHADOW_2_AGU_O_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400 641#define SHADOW_2_AGU_O_REMOTE_MME3_CTRL_SECTION 0x2400 642#define mmSHADOW_2_DESC_MME3_CTRL_BASE 0x7FFC1E0AD4ull 643#define SHADOW_2_DESC_MME3_CTRL_MAX_OFFSET 0x5400 644#define SHADOW_2_DESC_MME3_CTRL_SECTION 0xB400 645#define mmSHADOW_3_MME3_CTRL_BASE 0x7FFC1E0B88ull 646#define SHADOW_3_MME3_CTRL_MAX_OFFSET 0x3400 647#define SHADOW_3_MME3_CTRL_SECTION 0x3400 648#define mmSHADOW_3_TENSOR_S_MME3_CTRL_BASE 0x7FFC1E0BBCull 649#define SHADOW_3_TENSOR_S_MME3_CTRL_MAX_OFFSET 0x4C00 650#define SHADOW_3_TENSOR_S_MME3_CTRL_SECTION 0x4C00 651#define mmSHADOW_3_AGU_S_MME3_CTRL_BASE 0x7FFC1E0C08ull 652#define SHADOW_3_AGU_S_MME3_CTRL_MAX_OFFSET 0x2400 653#define SHADOW_3_AGU_S_MME3_CTRL_SECTION 0x2400 654#define mmSHADOW_3_TENSOR_L_MME3_CTRL_BASE 0x7FFC1E0C2Cull 655#define SHADOW_3_TENSOR_L_MME3_CTRL_MAX_OFFSET 0x4C00 656#define SHADOW_3_TENSOR_L_MME3_CTRL_SECTION 0x4C00 657#define mmSHADOW_3_AGU_L_LOCAL_MME3_CTRL_BASE 0x7FFC1E0C78ull 658#define SHADOW_3_AGU_L_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400 659#define SHADOW_3_AGU_L_LOCAL_MME3_CTRL_SECTION 0x2400 660#define mmSHADOW_3_AGU_L_REMOTE_MME3_CTRL_BASE 0x7FFC1E0C9Cull 661#define SHADOW_3_AGU_L_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400 662#define SHADOW_3_AGU_L_REMOTE_MME3_CTRL_SECTION 0x2400 663#define mmSHADOW_3_TENSOR_O_MME3_CTRL_BASE 0x7FFC1E0CC0ull 664#define SHADOW_3_TENSOR_O_MME3_CTRL_MAX_OFFSET 0x4C00 665#define SHADOW_3_TENSOR_O_MME3_CTRL_SECTION 0x4C00 666#define mmSHADOW_3_AGU_O_LOCAL_MME3_CTRL_BASE 0x7FFC1E0D0Cull 667#define SHADOW_3_AGU_O_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400 668#define SHADOW_3_AGU_O_LOCAL_MME3_CTRL_SECTION 0x2400 669#define mmSHADOW_3_AGU_O_REMOTE_MME3_CTRL_BASE 0x7FFC1E0D30ull 670#define SHADOW_3_AGU_O_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400 671#define SHADOW_3_AGU_O_REMOTE_MME3_CTRL_SECTION 0x2400 672#define mmSHADOW_3_DESC_MME3_CTRL_BASE 0x7FFC1E0D54ull 673#define SHADOW_3_DESC_MME3_CTRL_MAX_OFFSET 0x5400 674#define SHADOW_3_DESC_MME3_CTRL_SECTION 0x72AC 675#define mmMME3_QM_BASE 0x7FFC1E8000ull 676#define MME3_QM_MAX_OFFSET 0xD040 677#define MME3_QM_SECTION 0x18000 678#define mmSRAM_Y0_X0_BANK_BASE 0x7FFC200000ull 679#define SRAM_Y0_X0_BANK_MAX_OFFSET 0x4000 680#define SRAM_Y0_X0_BANK_SECTION 0x1000 681#define mmSRAM_Y0_X0_RTR_BASE 0x7FFC201000ull 682#define SRAM_Y0_X0_RTR_MAX_OFFSET 0x3340 683#define SRAM_Y0_X0_RTR_SECTION 0x7000 684#define mmSRAM_Y0_X1_BANK_BASE 0x7FFC208000ull 685#define SRAM_Y0_X1_BANK_MAX_OFFSET 0x4000 686#define SRAM_Y0_X1_BANK_SECTION 0x1000 687#define mmSRAM_Y0_X1_RTR_BASE 0x7FFC209000ull 688#define SRAM_Y0_X1_RTR_MAX_OFFSET 0x3340 689#define SRAM_Y0_X1_RTR_SECTION 0x7000 690#define mmSRAM_Y0_X2_BANK_BASE 0x7FFC210000ull 691#define SRAM_Y0_X2_BANK_MAX_OFFSET 0x4000 692#define SRAM_Y0_X2_BANK_SECTION 0x1000 693#define mmSRAM_Y0_X2_RTR_BASE 0x7FFC211000ull 694#define SRAM_Y0_X2_RTR_MAX_OFFSET 0x3340 695#define SRAM_Y0_X2_RTR_SECTION 0x7000 696#define mmSRAM_Y0_X3_BANK_BASE 0x7FFC218000ull 697#define SRAM_Y0_X3_BANK_MAX_OFFSET 0x4000 698#define SRAM_Y0_X3_BANK_SECTION 0x1000 699#define mmSRAM_Y0_X3_RTR_BASE 0x7FFC219000ull 700#define SRAM_Y0_X3_RTR_MAX_OFFSET 0x3340 701#define SRAM_Y0_X3_RTR_SECTION 0x7000 702#define mmSRAM_Y0_X4_BANK_BASE 0x7FFC220000ull 703#define SRAM_Y0_X4_BANK_MAX_OFFSET 0x4000 704#define SRAM_Y0_X4_BANK_SECTION 0x1000 705#define mmSRAM_Y0_X4_RTR_BASE 0x7FFC221000ull 706#define SRAM_Y0_X4_RTR_MAX_OFFSET 0x3340 707#define SRAM_Y0_X4_RTR_SECTION 0x7000 708#define mmSRAM_Y0_X5_BANK_BASE 0x7FFC228000ull 709#define SRAM_Y0_X5_BANK_MAX_OFFSET 0x4000 710#define SRAM_Y0_X5_BANK_SECTION 0x1000 711#define mmSRAM_Y0_X5_RTR_BASE 0x7FFC229000ull 712#define SRAM_Y0_X5_RTR_MAX_OFFSET 0x3340 713#define SRAM_Y0_X5_RTR_SECTION 0x7000 714#define mmSRAM_Y0_X6_BANK_BASE 0x7FFC230000ull 715#define SRAM_Y0_X6_BANK_MAX_OFFSET 0x4000 716#define SRAM_Y0_X6_BANK_SECTION 0x1000 717#define mmSRAM_Y0_X6_RTR_BASE 0x7FFC231000ull 718#define SRAM_Y0_X6_RTR_MAX_OFFSET 0x3340 719#define SRAM_Y0_X6_RTR_SECTION 0x7000 720#define mmSRAM_Y0_X7_BANK_BASE 0x7FFC238000ull 721#define SRAM_Y0_X7_BANK_MAX_OFFSET 0x4000 722#define SRAM_Y0_X7_BANK_SECTION 0x1000 723#define mmSRAM_Y0_X7_RTR_BASE 0x7FFC239000ull 724#define SRAM_Y0_X7_RTR_MAX_OFFSET 0x3340 725#define SRAM_Y0_X7_RTR_SECTION 0x7000 726#define mmSRAM_Y1_X0_BANK_BASE 0x7FFC240000ull 727#define SRAM_Y1_X0_BANK_MAX_OFFSET 0x4000 728#define SRAM_Y1_X0_BANK_SECTION 0x1000 729#define mmSRAM_Y1_X0_RTR_BASE 0x7FFC241000ull 730#define SRAM_Y1_X0_RTR_MAX_OFFSET 0x3340 731#define SRAM_Y1_X0_RTR_SECTION 0x7000 732#define mmSRAM_Y1_X1_BANK_BASE 0x7FFC248000ull 733#define SRAM_Y1_X1_BANK_MAX_OFFSET 0x4000 734#define SRAM_Y1_X1_BANK_SECTION 0x1000 735#define mmSRAM_Y1_X1_RTR_BASE 0x7FFC249000ull 736#define SRAM_Y1_X1_RTR_MAX_OFFSET 0x3340 737#define SRAM_Y1_X1_RTR_SECTION 0x7000 738#define mmSRAM_Y1_X2_BANK_BASE 0x7FFC250000ull 739#define SRAM_Y1_X2_BANK_MAX_OFFSET 0x4000 740#define SRAM_Y1_X2_BANK_SECTION 0x1000 741#define mmSRAM_Y1_X2_RTR_BASE 0x7FFC251000ull 742#define SRAM_Y1_X2_RTR_MAX_OFFSET 0x3340 743#define SRAM_Y1_X2_RTR_SECTION 0x7000 744#define mmSRAM_Y1_X3_BANK_BASE 0x7FFC258000ull 745#define SRAM_Y1_X3_BANK_MAX_OFFSET 0x4000 746#define SRAM_Y1_X3_BANK_SECTION 0x1000 747#define mmSRAM_Y1_X3_RTR_BASE 0x7FFC259000ull 748#define SRAM_Y1_X3_RTR_MAX_OFFSET 0x3340 749#define SRAM_Y1_X3_RTR_SECTION 0x7000 750#define mmSRAM_Y1_X4_BANK_BASE 0x7FFC260000ull 751#define SRAM_Y1_X4_BANK_MAX_OFFSET 0x4000 752#define SRAM_Y1_X4_BANK_SECTION 0x1000 753#define mmSRAM_Y1_X4_RTR_BASE 0x7FFC261000ull 754#define SRAM_Y1_X4_RTR_MAX_OFFSET 0x3340 755#define SRAM_Y1_X4_RTR_SECTION 0x7000 756#define mmSRAM_Y1_X5_BANK_BASE 0x7FFC268000ull 757#define SRAM_Y1_X5_BANK_MAX_OFFSET 0x4000 758#define SRAM_Y1_X5_BANK_SECTION 0x1000 759#define mmSRAM_Y1_X5_RTR_BASE 0x7FFC269000ull 760#define SRAM_Y1_X5_RTR_MAX_OFFSET 0x3340 761#define SRAM_Y1_X5_RTR_SECTION 0x7000 762#define mmSRAM_Y1_X6_BANK_BASE 0x7FFC270000ull 763#define SRAM_Y1_X6_BANK_MAX_OFFSET 0x4000 764#define SRAM_Y1_X6_BANK_SECTION 0x1000 765#define mmSRAM_Y1_X6_RTR_BASE 0x7FFC271000ull 766#define SRAM_Y1_X6_RTR_MAX_OFFSET 0x3340 767#define SRAM_Y1_X6_RTR_SECTION 0x7000 768#define mmSRAM_Y1_X7_BANK_BASE 0x7FFC278000ull 769#define SRAM_Y1_X7_BANK_MAX_OFFSET 0x4000 770#define SRAM_Y1_X7_BANK_SECTION 0x1000 771#define mmSRAM_Y1_X7_RTR_BASE 0x7FFC279000ull 772#define SRAM_Y1_X7_RTR_MAX_OFFSET 0x3340 773#define SRAM_Y1_X7_RTR_SECTION 0x7000 774#define mmSRAM_Y2_X0_BANK_BASE 0x7FFC280000ull 775#define SRAM_Y2_X0_BANK_MAX_OFFSET 0x4000 776#define SRAM_Y2_X0_BANK_SECTION 0x1000 777#define mmSRAM_Y2_X0_RTR_BASE 0x7FFC281000ull 778#define SRAM_Y2_X0_RTR_MAX_OFFSET 0x3340 779#define SRAM_Y2_X0_RTR_SECTION 0x7000 780#define mmSRAM_Y2_X1_BANK_BASE 0x7FFC288000ull 781#define SRAM_Y2_X1_BANK_MAX_OFFSET 0x4000 782#define SRAM_Y2_X1_BANK_SECTION 0x1000 783#define mmSRAM_Y2_X1_RTR_BASE 0x7FFC289000ull 784#define SRAM_Y2_X1_RTR_MAX_OFFSET 0x3340 785#define SRAM_Y2_X1_RTR_SECTION 0x7000 786#define mmSRAM_Y2_X2_BANK_BASE 0x7FFC290000ull 787#define SRAM_Y2_X2_BANK_MAX_OFFSET 0x4000 788#define SRAM_Y2_X2_BANK_SECTION 0x1000 789#define mmSRAM_Y2_X2_RTR_BASE 0x7FFC291000ull 790#define SRAM_Y2_X2_RTR_MAX_OFFSET 0x3340 791#define SRAM_Y2_X2_RTR_SECTION 0x7000 792#define mmSRAM_Y2_X3_BANK_BASE 0x7FFC298000ull 793#define SRAM_Y2_X3_BANK_MAX_OFFSET 0x4000 794#define SRAM_Y2_X3_BANK_SECTION 0x1000 795#define mmSRAM_Y2_X3_RTR_BASE 0x7FFC299000ull 796#define SRAM_Y2_X3_RTR_MAX_OFFSET 0x3340 797#define SRAM_Y2_X3_RTR_SECTION 0x7000 798#define mmSRAM_Y2_X4_BANK_BASE 0x7FFC2A0000ull 799#define SRAM_Y2_X4_BANK_MAX_OFFSET 0x4000 800#define SRAM_Y2_X4_BANK_SECTION 0x1000 801#define mmSRAM_Y2_X4_RTR_BASE 0x7FFC2A1000ull 802#define SRAM_Y2_X4_RTR_MAX_OFFSET 0x3340 803#define SRAM_Y2_X4_RTR_SECTION 0x7000 804#define mmSRAM_Y2_X5_BANK_BASE 0x7FFC2A8000ull 805#define SRAM_Y2_X5_BANK_MAX_OFFSET 0x4000 806#define SRAM_Y2_X5_BANK_SECTION 0x1000 807#define mmSRAM_Y2_X5_RTR_BASE 0x7FFC2A9000ull 808#define SRAM_Y2_X5_RTR_MAX_OFFSET 0x3340 809#define SRAM_Y2_X5_RTR_SECTION 0x7000 810#define mmSRAM_Y2_X6_BANK_BASE 0x7FFC2B0000ull 811#define SRAM_Y2_X6_BANK_MAX_OFFSET 0x4000 812#define SRAM_Y2_X6_BANK_SECTION 0x1000 813#define mmSRAM_Y2_X6_RTR_BASE 0x7FFC2B1000ull 814#define SRAM_Y2_X6_RTR_MAX_OFFSET 0x3340 815#define SRAM_Y2_X6_RTR_SECTION 0x7000 816#define mmSRAM_Y2_X7_BANK_BASE 0x7FFC2B8000ull 817#define SRAM_Y2_X7_BANK_MAX_OFFSET 0x4000 818#define SRAM_Y2_X7_BANK_SECTION 0x1000 819#define mmSRAM_Y2_X7_RTR_BASE 0x7FFC2B9000ull 820#define SRAM_Y2_X7_RTR_MAX_OFFSET 0x3340 821#define SRAM_Y2_X7_RTR_SECTION 0x7000 822#define mmSRAM_Y3_X0_BANK_BASE 0x7FFC2C0000ull 823#define SRAM_Y3_X0_BANK_MAX_OFFSET 0x4000 824#define SRAM_Y3_X0_BANK_SECTION 0x1000 825#define mmSRAM_Y3_X0_RTR_BASE 0x7FFC2C1000ull 826#define SRAM_Y3_X0_RTR_MAX_OFFSET 0x3340 827#define SRAM_Y3_X0_RTR_SECTION 0x7000 828#define mmSRAM_Y3_X1_BANK_BASE 0x7FFC2C8000ull 829#define SRAM_Y3_X1_BANK_MAX_OFFSET 0x4000 830#define SRAM_Y3_X1_BANK_SECTION 0x1000 831#define mmSRAM_Y3_X1_RTR_BASE 0x7FFC2C9000ull 832#define SRAM_Y3_X1_RTR_MAX_OFFSET 0x3340 833#define SRAM_Y3_X1_RTR_SECTION 0x7000 834#define mmSRAM_Y3_X2_BANK_BASE 0x7FFC2D0000ull 835#define SRAM_Y3_X2_BANK_MAX_OFFSET 0x4000 836#define SRAM_Y3_X2_BANK_SECTION 0x1000 837#define mmSRAM_Y3_X2_RTR_BASE 0x7FFC2D1000ull 838#define SRAM_Y3_X2_RTR_MAX_OFFSET 0x3340 839#define SRAM_Y3_X2_RTR_SECTION 0x7000 840#define mmSRAM_Y3_X3_BANK_BASE 0x7FFC2D8000ull 841#define SRAM_Y3_X3_BANK_MAX_OFFSET 0x4000 842#define SRAM_Y3_X3_BANK_SECTION 0x1000 843#define mmSRAM_Y3_X3_RTR_BASE 0x7FFC2D9000ull 844#define SRAM_Y3_X3_RTR_MAX_OFFSET 0x3340 845#define SRAM_Y3_X3_RTR_SECTION 0x7000 846#define mmSRAM_Y3_X4_BANK_BASE 0x7FFC2E0000ull 847#define SRAM_Y3_X4_BANK_MAX_OFFSET 0x4000 848#define SRAM_Y3_X4_BANK_SECTION 0x1000 849#define mmSRAM_Y3_X4_RTR_BASE 0x7FFC2E1000ull 850#define SRAM_Y3_X4_RTR_MAX_OFFSET 0x3340 851#define SRAM_Y3_X4_RTR_SECTION 0x7000 852#define mmSRAM_Y3_X5_BANK_BASE 0x7FFC2E8000ull 853#define SRAM_Y3_X5_BANK_MAX_OFFSET 0x4000 854#define SRAM_Y3_X5_BANK_SECTION 0x1000 855#define mmSRAM_Y3_X5_RTR_BASE 0x7FFC2E9000ull 856#define SRAM_Y3_X5_RTR_MAX_OFFSET 0x3340 857#define SRAM_Y3_X5_RTR_SECTION 0x7000 858#define mmSRAM_Y3_X6_BANK_BASE 0x7FFC2F0000ull 859#define SRAM_Y3_X6_BANK_MAX_OFFSET 0x4000 860#define SRAM_Y3_X6_BANK_SECTION 0x1000 861#define mmSRAM_Y3_X6_RTR_BASE 0x7FFC2F1000ull 862#define SRAM_Y3_X6_RTR_MAX_OFFSET 0x3340 863#define SRAM_Y3_X6_RTR_SECTION 0x7000 864#define mmSRAM_Y3_X7_BANK_BASE 0x7FFC2F8000ull 865#define SRAM_Y3_X7_BANK_MAX_OFFSET 0x4000 866#define SRAM_Y3_X7_BANK_SECTION 0x1000 867#define mmSRAM_Y3_X7_RTR_BASE 0x7FFC2F9000ull 868#define SRAM_Y3_X7_RTR_MAX_OFFSET 0x3340 869#define SRAM_Y3_X7_RTR_SECTION 0x7000 870#define mmSIF_RTR_0_BASE 0x7FFC300000ull 871#define SIF_RTR_0_MAX_OFFSET 0x6500 872#define SIF_RTR_0_SECTION 0x6000 873#define mmSIF_RTR_CTRL_0_BASE 0x7FFC306000ull 874#define SIF_RTR_CTRL_0_MAX_OFFSET 0xCC00 875#define SIF_RTR_CTRL_0_SECTION 0xA000 876#define mmSIF_RTR_1_BASE 0x7FFC310000ull 877#define SIF_RTR_1_MAX_OFFSET 0x6500 878#define SIF_RTR_1_SECTION 0x6000 879#define mmSIF_RTR_CTRL_1_BASE 0x7FFC316000ull 880#define SIF_RTR_CTRL_1_MAX_OFFSET 0xCC00 881#define SIF_RTR_CTRL_1_SECTION 0xA000 882#define mmSIF_RTR_2_BASE 0x7FFC320000ull 883#define SIF_RTR_2_MAX_OFFSET 0x6500 884#define SIF_RTR_2_SECTION 0x6000 885#define mmSIF_RTR_CTRL_2_BASE 0x7FFC326000ull 886#define SIF_RTR_CTRL_2_MAX_OFFSET 0xCC00 887#define SIF_RTR_CTRL_2_SECTION 0xA000 888#define mmSIF_RTR_3_BASE 0x7FFC330000ull 889#define SIF_RTR_3_MAX_OFFSET 0x6500 890#define SIF_RTR_3_SECTION 0x6000 891#define mmSIF_RTR_CTRL_3_BASE 0x7FFC336000ull 892#define SIF_RTR_CTRL_3_MAX_OFFSET 0xCC00 893#define SIF_RTR_CTRL_3_SECTION 0xA000 894#define mmSIF_RTR_4_BASE 0x7FFC340000ull 895#define SIF_RTR_4_MAX_OFFSET 0x6500 896#define SIF_RTR_4_SECTION 0x6000 897#define mmSIF_RTR_CTRL_4_BASE 0x7FFC346000ull 898#define SIF_RTR_CTRL_4_MAX_OFFSET 0xCC00 899#define SIF_RTR_CTRL_4_SECTION 0xA000 900#define mmSIF_RTR_5_BASE 0x7FFC350000ull 901#define SIF_RTR_5_MAX_OFFSET 0x6500 902#define SIF_RTR_5_SECTION 0x6000 903#define mmSIF_RTR_CTRL_5_BASE 0x7FFC356000ull 904#define SIF_RTR_CTRL_5_MAX_OFFSET 0xCC00 905#define SIF_RTR_CTRL_5_SECTION 0xA000 906#define mmSIF_RTR_6_BASE 0x7FFC360000ull 907#define SIF_RTR_6_MAX_OFFSET 0x6500 908#define SIF_RTR_6_SECTION 0x6000 909#define mmSIF_RTR_CTRL_6_BASE 0x7FFC366000ull 910#define SIF_RTR_CTRL_6_MAX_OFFSET 0xCC00 911#define SIF_RTR_CTRL_6_SECTION 0xA000 912#define mmSIF_RTR_7_BASE 0x7FFC370000ull 913#define SIF_RTR_7_MAX_OFFSET 0x6500 914#define SIF_RTR_7_SECTION 0x6000 915#define mmSIF_RTR_CTRL_7_BASE 0x7FFC376000ull 916#define SIF_RTR_CTRL_7_MAX_OFFSET 0xCC00 917#define SIF_RTR_CTRL_7_SECTION 0xA000 918#define mmNIF_RTR_0_BASE 0x7FFC380000ull 919#define NIF_RTR_0_MAX_OFFSET 0x6500 920#define NIF_RTR_0_SECTION 0x6000 921#define mmNIF_RTR_CTRL_0_BASE 0x7FFC386000ull 922#define NIF_RTR_CTRL_0_MAX_OFFSET 0xCC00 923#define NIF_RTR_CTRL_0_SECTION 0xA000 924#define mmNIF_RTR_1_BASE 0x7FFC390000ull 925#define NIF_RTR_1_MAX_OFFSET 0x6500 926#define NIF_RTR_1_SECTION 0x6000 927#define mmNIF_RTR_CTRL_1_BASE 0x7FFC396000ull 928#define NIF_RTR_CTRL_1_MAX_OFFSET 0xCC00 929#define NIF_RTR_CTRL_1_SECTION 0xA000 930#define mmNIF_RTR_2_BASE 0x7FFC3A0000ull 931#define NIF_RTR_2_MAX_OFFSET 0x6500 932#define NIF_RTR_2_SECTION 0x6000 933#define mmNIF_RTR_CTRL_2_BASE 0x7FFC3A6000ull 934#define NIF_RTR_CTRL_2_MAX_OFFSET 0xCC00 935#define NIF_RTR_CTRL_2_SECTION 0xA000 936#define mmNIF_RTR_3_BASE 0x7FFC3B0000ull 937#define NIF_RTR_3_MAX_OFFSET 0x6500 938#define NIF_RTR_3_SECTION 0x6000 939#define mmNIF_RTR_CTRL_3_BASE 0x7FFC3B6000ull 940#define NIF_RTR_CTRL_3_MAX_OFFSET 0xCC00 941#define NIF_RTR_CTRL_3_SECTION 0xA000 942#define mmNIF_RTR_4_BASE 0x7FFC3C0000ull 943#define NIF_RTR_4_MAX_OFFSET 0x6500 944#define NIF_RTR_4_SECTION 0x6000 945#define mmNIF_RTR_CTRL_4_BASE 0x7FFC3C6000ull 946#define NIF_RTR_CTRL_4_MAX_OFFSET 0xCC00 947#define NIF_RTR_CTRL_4_SECTION 0xA000 948#define mmNIF_RTR_5_BASE 0x7FFC3D0000ull 949#define NIF_RTR_5_MAX_OFFSET 0x6500 950#define NIF_RTR_5_SECTION 0x6000 951#define mmNIF_RTR_CTRL_5_BASE 0x7FFC3D6000ull 952#define NIF_RTR_CTRL_5_MAX_OFFSET 0xCC00 953#define NIF_RTR_CTRL_5_SECTION 0xA000 954#define mmNIF_RTR_6_BASE 0x7FFC3E0000ull 955#define NIF_RTR_6_MAX_OFFSET 0x6500 956#define NIF_RTR_6_SECTION 0x6000 957#define mmNIF_RTR_CTRL_6_BASE 0x7FFC3E6000ull 958#define NIF_RTR_CTRL_6_MAX_OFFSET 0xCC00 959#define NIF_RTR_CTRL_6_SECTION 0xA000 960#define mmNIF_RTR_7_BASE 0x7FFC3F0000ull 961#define NIF_RTR_7_MAX_OFFSET 0x6500 962#define NIF_RTR_7_SECTION 0x6000 963#define mmNIF_RTR_CTRL_7_BASE 0x7FFC3F6000ull 964#define NIF_RTR_CTRL_7_MAX_OFFSET 0xCC00 965#define NIF_RTR_CTRL_7_SECTION 0x4B000 966#define mmCPU_CA53_CFG_BASE 0x7FFC441000ull 967#define CPU_CA53_CFG_MAX_OFFSET 0x2180 968#define CPU_CA53_CFG_SECTION 0x1000 969#define mmCPU_IF_BASE 0x7FFC442000ull 970#define CPU_IF_MAX_OFFSET 0x43C0 971#define CPU_IF_SECTION 0x2000 972#define mmCPU_TIMESTAMP_BASE 0x7FFC444000ull 973#define CPU_TIMESTAMP_MAX_OFFSET 0x1000 974#define CPU_TIMESTAMP_SECTION 0x3C000 975#define mmDMA_IF_W_S_BASE 0x7FFC480000ull 976#define DMA_IF_W_S_MAX_OFFSET 0x8380 977#define DMA_IF_W_S_SECTION 0x1000 978#define mmDMA_IF_W_S_DOWN_CH0_BASE 0x7FFC481000ull 979#define DMA_IF_W_S_DOWN_CH0_MAX_OFFSET 0xCC00 980#define DMA_IF_W_S_DOWN_CH0_SECTION 0x1000 981#define mmDMA_IF_W_S_DOWN_CH1_BASE 0x7FFC482000ull 982#define DMA_IF_W_S_DOWN_CH1_MAX_OFFSET 0xCC00 983#define DMA_IF_W_S_DOWN_CH1_SECTION 0x5000 984#define mmDMA_W_PLL_BASE 0x7FFC487000ull 985#define DMA_W_PLL_MAX_OFFSET 0x5200 986#define DMA_W_PLL_SECTION 0x1000 987#define mmIF_W_PLL_BASE 0x7FFC488000ull 988#define IF_W_PLL_MAX_OFFSET 0x5200 989#define IF_W_PLL_SECTION 0x1000 990#define mmDMA_IF_W_S_DOWN_BASE 0x7FFC489000ull 991#define DMA_IF_W_S_DOWN_MAX_OFFSET 0x1500 992#define DMA_IF_W_S_DOWN_SECTION 0x7000 993#define mmSYNC_MNGR_GLBL_W_S_BASE 0x7FFC490000ull 994#define SYNC_MNGR_GLBL_W_S_MAX_OFFSET 0x6C00 995#define SYNC_MNGR_GLBL_W_S_SECTION 0x1000 996#define mmSYNC_MNGR_OBJS_W_S_BASE 0x7FFC491000ull 997#define SYNC_MNGR_OBJS_W_S_MAX_OFFSET 0x5C00 998#define SYNC_MNGR_OBJS_W_S_SECTION 0xF000 999#define mmDMA_IF_E_S_BASE 0x7FFC4A0000ull 1000#define DMA_IF_E_S_MAX_OFFSET 0x8380 1001#define DMA_IF_E_S_SECTION 0x1000 1002#define mmDMA_IF_E_S_DOWN_CH0_BASE 0x7FFC4A1000ull 1003#define DMA_IF_E_S_DOWN_CH0_MAX_OFFSET 0xCC00 1004#define DMA_IF_E_S_DOWN_CH0_SECTION 0x1000 1005#define mmDMA_IF_E_S_DOWN_CH1_BASE 0x7FFC4A2000ull 1006#define DMA_IF_E_S_DOWN_CH1_MAX_OFFSET 0xCC00 1007#define DMA_IF_E_S_DOWN_CH1_SECTION 0x5000 1008#define mmIF_E_PLL_BASE 0x7FFC4A7000ull 1009#define IF_E_PLL_MAX_OFFSET 0x5200 1010#define IF_E_PLL_SECTION 0x1000 1011#define mmDMA_E_PLL_BASE 0x7FFC4A8000ull 1012#define DMA_E_PLL_MAX_OFFSET 0x5200 1013#define DMA_E_PLL_SECTION 0x1000 1014#define mmDMA_IF_E_S_DOWN_BASE 0x7FFC4A9000ull 1015#define DMA_IF_E_S_DOWN_MAX_OFFSET 0x1500 1016#define DMA_IF_E_S_DOWN_SECTION 0x7000 1017#define mmSYNC_MNGR_GLBL_E_S_BASE 0x7FFC4B0000ull 1018#define SYNC_MNGR_GLBL_E_S_MAX_OFFSET 0x6C00 1019#define SYNC_MNGR_GLBL_E_S_SECTION 0x1000 1020#define mmSYNC_MNGR_OBJS_E_S_BASE 0x7FFC4B1000ull 1021#define SYNC_MNGR_OBJS_E_S_MAX_OFFSET 0x5C00 1022#define SYNC_MNGR_OBJS_E_S_SECTION 0xF000 1023#define mmDMA_IF_W_N_BASE 0x7FFC4C0000ull 1024#define DMA_IF_W_N_MAX_OFFSET 0x8380 1025#define DMA_IF_W_N_SECTION 0x1000 1026#define mmDMA_IF_W_N_DOWN_CH0_BASE 0x7FFC4C1000ull 1027#define DMA_IF_W_N_DOWN_CH0_MAX_OFFSET 0xCC00 1028#define DMA_IF_W_N_DOWN_CH0_SECTION 0x1000 1029#define mmDMA_IF_W_N_DOWN_CH1_BASE 0x7FFC4C2000ull 1030#define DMA_IF_W_N_DOWN_CH1_MAX_OFFSET 0xCC00 1031#define DMA_IF_W_N_DOWN_CH1_SECTION 0x5000 1032#define mmMESH_W_PLL_BASE 0x7FFC4C7000ull 1033#define MESH_W_PLL_MAX_OFFSET 0x5200 1034#define MESH_W_PLL_SECTION 0x1000 1035#define mmSRAM_W_PLL_BASE 0x7FFC4C8000ull 1036#define SRAM_W_PLL_MAX_OFFSET 0x5200 1037#define SRAM_W_PLL_SECTION 0x1000 1038#define mmDMA_IF_W_N_DOWN_BASE 0x7FFC4C9000ull 1039#define DMA_IF_W_N_DOWN_MAX_OFFSET 0x1500 1040#define DMA_IF_W_N_DOWN_SECTION 0x7000 1041#define mmSYNC_MNGR_GLBL_W_N_BASE 0x7FFC4D0000ull 1042#define SYNC_MNGR_GLBL_W_N_MAX_OFFSET 0x6C00 1043#define SYNC_MNGR_GLBL_W_N_SECTION 0x1000 1044#define mmSYNC_MNGR_OBJS_W_N_BASE 0x7FFC4D1000ull 1045#define SYNC_MNGR_OBJS_W_N_MAX_OFFSET 0x5C00 1046#define SYNC_MNGR_OBJS_W_N_SECTION 0xF000 1047#define mmDMA_IF_E_N_BASE 0x7FFC4E0000ull 1048#define DMA_IF_E_N_MAX_OFFSET 0x8380 1049#define DMA_IF_E_N_SECTION 0x1000 1050#define mmDMA_IF_E_N_DOWN_CH0_BASE 0x7FFC4E1000ull 1051#define DMA_IF_E_N_DOWN_CH0_MAX_OFFSET 0xCC00 1052#define DMA_IF_E_N_DOWN_CH0_SECTION 0x1000 1053#define mmDMA_IF_E_N_DOWN_CH1_BASE 0x7FFC4E2000ull 1054#define DMA_IF_E_N_DOWN_CH1_MAX_OFFSET 0xCC00 1055#define DMA_IF_E_N_DOWN_CH1_SECTION 0x5000 1056#define mmMESH_E_PLL_BASE 0x7FFC4E7000ull 1057#define MESH_E_PLL_MAX_OFFSET 0x5200 1058#define MESH_E_PLL_SECTION 0x1000 1059#define mmSRAM_E_PLL_BASE 0x7FFC4E8000ull 1060#define SRAM_E_PLL_MAX_OFFSET 0x5200 1061#define SRAM_E_PLL_SECTION 0x1000 1062#define mmDMA_IF_E_N_DOWN_BASE 0x7FFC4E9000ull 1063#define DMA_IF_E_N_DOWN_MAX_OFFSET 0x1500 1064#define DMA_IF_E_N_DOWN_SECTION 0x7000 1065#define mmSYNC_MNGR_GLBL_E_N_BASE 0x7FFC4F0000ull 1066#define SYNC_MNGR_GLBL_E_N_MAX_OFFSET 0x6C00 1067#define SYNC_MNGR_GLBL_E_N_SECTION 0x1000 1068#define mmSYNC_MNGR_OBJS_E_N_BASE 0x7FFC4F1000ull 1069#define SYNC_MNGR_OBJS_E_N_MAX_OFFSET 0x5C00 1070#define SYNC_MNGR_OBJS_E_N_SECTION 0xF000 1071#define mmDMA0_CORE_BASE 0x7FFC500000ull 1072#define DMA0_CORE_MAX_OFFSET 0x23C0 1073#define DMA0_CORE_SECTION 0x8000 1074#define mmDMA0_QM_BASE 0x7FFC508000ull 1075#define DMA0_QM_MAX_OFFSET 0xD040 1076#define DMA0_QM_SECTION 0x18000 1077#define mmDMA1_CORE_BASE 0x7FFC520000ull 1078#define DMA1_CORE_MAX_OFFSET 0x23C0 1079#define DMA1_CORE_SECTION 0x8000 1080#define mmDMA1_QM_BASE 0x7FFC528000ull 1081#define DMA1_QM_MAX_OFFSET 0xD040 1082#define DMA1_QM_SECTION 0x18000 1083#define mmDMA2_CORE_BASE 0x7FFC540000ull 1084#define DMA2_CORE_MAX_OFFSET 0x23C0 1085#define DMA2_CORE_SECTION 0x8000 1086#define mmDMA2_QM_BASE 0x7FFC548000ull 1087#define DMA2_QM_MAX_OFFSET 0xD040 1088#define DMA2_QM_SECTION 0x18000 1089#define mmDMA3_CORE_BASE 0x7FFC560000ull 1090#define DMA3_CORE_MAX_OFFSET 0x23C0 1091#define DMA3_CORE_SECTION 0x8000 1092#define mmDMA3_QM_BASE 0x7FFC568000ull 1093#define DMA3_QM_MAX_OFFSET 0xD040 1094#define DMA3_QM_SECTION 0x18000 1095#define mmDMA4_CORE_BASE 0x7FFC580000ull 1096#define DMA4_CORE_MAX_OFFSET 0x23C0 1097#define DMA4_CORE_SECTION 0x8000 1098#define mmDMA4_QM_BASE 0x7FFC588000ull 1099#define DMA4_QM_MAX_OFFSET 0xD040 1100#define DMA4_QM_SECTION 0x18000 1101#define mmDMA5_CORE_BASE 0x7FFC5A0000ull 1102#define DMA5_CORE_MAX_OFFSET 0x23C0 1103#define DMA5_CORE_SECTION 0x8000 1104#define mmDMA5_QM_BASE 0x7FFC5A8000ull 1105#define DMA5_QM_MAX_OFFSET 0xD040 1106#define DMA5_QM_SECTION 0x18000 1107#define mmDMA6_CORE_BASE 0x7FFC5C0000ull 1108#define DMA6_CORE_MAX_OFFSET 0x23C0 1109#define DMA6_CORE_SECTION 0x8000 1110#define mmDMA6_QM_BASE 0x7FFC5C8000ull 1111#define DMA6_QM_MAX_OFFSET 0xD040 1112#define DMA6_QM_SECTION 0x18000 1113#define mmDMA7_CORE_BASE 0x7FFC5E0000ull 1114#define DMA7_CORE_MAX_OFFSET 0x23C0 1115#define DMA7_CORE_SECTION 0x8000 1116#define mmDMA7_QM_BASE 0x7FFC5E8000ull 1117#define DMA7_QM_MAX_OFFSET 0xD040 1118#define DMA7_QM_SECTION 0x18000 1119#define mmHBM0_BASE 0x7FFC600000ull 1120#define HBM0_MAX_OFFSET 0x8F58 1121#define HBM0_SECTION 0x80000 1122#define mmHBM1_BASE 0x7FFC680000ull 1123#define HBM1_MAX_OFFSET 0x8F58 1124#define HBM1_SECTION 0x80000 1125#define mmHBM2_BASE 0x7FFC700000ull 1126#define HBM2_MAX_OFFSET 0x8F58 1127#define HBM2_SECTION 0x80000 1128#define mmHBM3_BASE 0x7FFC780000ull 1129#define HBM3_MAX_OFFSET 0x8F58 1130#define HBM3_SECTION 0x80000 1131#define mmGIC_BASE 0x7FFC800000ull 1132#define GIC_MAX_OFFSET 0x10000 1133#define GIC_SECTION 0x401000 1134#define mmPCIE_WRAP_BASE 0x7FFCC01000ull 1135#define PCIE_WRAP_MAX_OFFSET 0xDF00 1136#define PCIE_WRAP_SECTION 0x1000 1137#define mmPCIE_DBI_BASE 0x7FFCC02000ull 1138#define PCIE_DBI_MAX_OFFSET 0xC040 1139#define PCIE_DBI_SECTION 0x2000 1140#define mmPCIE_CORE_BASE 0x7FFCC04000ull 1141#define PCIE_CORE_MAX_OFFSET 0x9BC0 1142#define PCIE_CORE_SECTION 0x3000 1143#define mmPCIE_AUX_BASE 0x7FFCC07000ull 1144#define PCIE_AUX_MAX_OFFSET 0x9C40 1145#define PCIE_AUX_SECTION 0x9000 1146#define mmPCIE_PHY_BASE 0x7FFCC10000ull 1147#define PCIE_PHY_MAX_OFFSET 0x9640 1148#define PCIE_PHY_SECTION 0x1000 1149#define mmMMU_UP_BASE 0x7FFCC11000ull 1150#define MMU_UP_MAX_OFFSET 0x7000 1151#define MMU_UP_SECTION 0x1000 1152#define mmSTLB_BASE 0x7FFCC12000ull 1153#define STLB_MAX_OFFSET 0x8800 1154#define STLB_SECTION 0x1000 1155#define mmPCIE_MSI_BASE 0x7FFCC13000ull 1156#define PCIE_MSI_MAX_OFFSET 0x8000 1157#define PCIE_MSI_SECTION 0x2D000 1158#define mmPSOC_I2C_M0_BASE 0x7FFCC40000ull 1159#define PSOC_I2C_M0_MAX_OFFSET 0x1000 1160#define PSOC_I2C_M0_SECTION 0x1000 1161#define mmPSOC_I2C_M1_BASE 0x7FFCC41000ull 1162#define PSOC_I2C_M1_MAX_OFFSET 0x1000 1163#define PSOC_I2C_M1_SECTION 0x1000 1164#define mmPSOC_I2C_S_BASE 0x7FFCC42000ull 1165#define PSOC_I2C_S_MAX_OFFSET 0x1000 1166#define PSOC_I2C_S_SECTION 0x1000 1167#define mmPSOC_SPI_BASE 0x7FFCC43000ull 1168#define PSOC_SPI_MAX_OFFSET 0x1000 1169#define PSOC_SPI_SECTION 0x2000 1170#define mmPSOC_UART_0_BASE 0x7FFCC45000ull 1171#define PSOC_UART_0_MAX_OFFSET 0x1000 1172#define PSOC_UART_0_SECTION 0x1000 1173#define mmPSOC_UART_1_BASE 0x7FFCC46000ull 1174#define PSOC_UART_1_MAX_OFFSET 0x1000 1175#define PSOC_UART_1_SECTION 0x1000 1176#define mmPSOC_TIMER_BASE 0x7FFCC47000ull 1177#define PSOC_TIMER_MAX_OFFSET 0x1000 1178#define PSOC_TIMER_SECTION 0x1000 1179#define mmPSOC_WDOG_BASE 0x7FFCC48000ull 1180#define PSOC_WDOG_MAX_OFFSET 0x1000 1181#define PSOC_WDOG_SECTION 0x1000 1182#define mmPSOC_TIMESTAMP_BASE 0x7FFCC49000ull 1183#define PSOC_TIMESTAMP_MAX_OFFSET 0x1000 1184#define PSOC_TIMESTAMP_SECTION 0x1000 1185#define mmPSOC_EFUSE_BASE 0x7FFCC4A000ull 1186#define PSOC_EFUSE_MAX_OFFSET 0x3040 1187#define PSOC_EFUSE_SECTION 0x1000 1188#define mmPSOC_GLOBAL_CONF_BASE 0x7FFCC4B000ull 1189#define PSOC_GLOBAL_CONF_MAX_OFFSET 0xCD80 1190#define PSOC_GLOBAL_CONF_SECTION 0x1000 1191#define mmPSOC_GPIO0_BASE 0x7FFCC4C000ull 1192#define PSOC_GPIO0_MAX_OFFSET 0x1000 1193#define PSOC_GPIO0_SECTION 0x1000 1194#define mmPSOC_GPIO1_BASE 0x7FFCC4D000ull 1195#define PSOC_GPIO1_MAX_OFFSET 0x1000 1196#define PSOC_GPIO1_SECTION 0x1000 1197#define mmPSOC_BTL_BASE 0x7FFCC4E000ull 1198#define PSOC_BTL_MAX_OFFSET 0x1480 1199#define PSOC_BTL_SECTION 0x1000 1200#define mmPSOC_CS_TRACE_BASE 0x7FFCC4F000ull 1201#define PSOC_CS_TRACE_MAX_OFFSET 0x1680 1202#define PSOC_CS_TRACE_SECTION 0x1000 1203#define mmPSOC_GPIO2_BASE 0x7FFCC50000ull 1204#define PSOC_GPIO2_MAX_OFFSET 0x1000 1205#define PSOC_GPIO2_SECTION 0x1000 1206#define mmPSOC_GPIO3_BASE 0x7FFCC51000ull 1207#define PSOC_GPIO3_MAX_OFFSET 0x1000 1208#define PSOC_GPIO3_SECTION 0x1000 1209#define mmPSOC_GPIO4_BASE 0x7FFCC52000ull 1210#define PSOC_GPIO4_MAX_OFFSET 0x1000 1211#define PSOC_GPIO4_SECTION 0x1000 1212#define mmPSOC_DFT_EFUSE_BASE 0x7FFCC53000ull 1213#define PSOC_DFT_EFUSE_MAX_OFFSET 0x3040 1214#define PSOC_DFT_EFUSE_SECTION 0x1000 1215#define mmPSOC_RPM_0_BASE 0x7FFCC54000ull 1216#define PSOC_RPM_0_MAX_OFFSET 0x8800 1217#define PSOC_RPM_0_SECTION 0x1000 1218#define mmPSOC_RPM_1_BASE 0x7FFCC55000ull 1219#define PSOC_RPM_1_MAX_OFFSET 0x8800 1220#define PSOC_RPM_1_SECTION 0x1000 1221#define mmPSOC_RPM_2_BASE 0x7FFCC56000ull 1222#define PSOC_RPM_2_MAX_OFFSET 0x8800 1223#define PSOC_RPM_2_SECTION 0x1000 1224#define mmPSOC_RPM_3_BASE 0x7FFCC57000ull 1225#define PSOC_RPM_3_MAX_OFFSET 0x8800 1226#define PSOC_RPM_3_SECTION 0x19000 1227#define mmPSOC_CPU_PLL_BASE 0x7FFCC70000ull 1228#define PSOC_CPU_PLL_MAX_OFFSET 0x5200 1229#define PSOC_CPU_PLL_SECTION 0x1000 1230#define mmPSOC_MME_PLL_BASE 0x7FFCC71000ull 1231#define PSOC_MME_PLL_MAX_OFFSET 0x5200 1232#define PSOC_MME_PLL_SECTION 0x1000 1233#define mmPSOC_PCI_PLL_BASE 0x7FFCC72000ull 1234#define PSOC_PCI_PLL_MAX_OFFSET 0x5200 1235#define PSOC_PCI_PLL_SECTION 0x1000 1236#define mmPSOC_TPC_PLL_BASE 0x7FFCC73000ull 1237#define PSOC_TPC_PLL_MAX_OFFSET 0x5200 1238#define PSOC_TPC_PLL_SECTION 0x1000 1239#define mmPSOC_HBM_PLL_BASE 0x7FFCC74000ull 1240#define PSOC_HBM_PLL_MAX_OFFSET 0x5200 1241#define PSOC_HBM_PLL_SECTION 0x1000 1242#define mmPSOC_PM_BASE 0x7FFCC75000ull 1243#define PSOC_PM_MAX_OFFSET 0x1F00 1244#define PSOC_PM_SECTION 0x1000 1245#define mmPSOC_TS_BASE 0x7FFCC76000ull 1246#define PSOC_TS_MAX_OFFSET 0xE640 1247#define PSOC_TS_SECTION 0x2000 1248#define mmPSOC_PWM0_BASE 0x7FFCC78000ull 1249#define PSOC_PWM0_MAX_OFFSET 0x5800 1250#define PSOC_PWM0_SECTION 0x1000 1251#define mmPSOC_PWM1_BASE 0x7FFCC79000ull 1252#define PSOC_PWM1_MAX_OFFSET 0x5800 1253#define PSOC_PWM1_SECTION 0x1000 1254#define mmPSOC_PWM2_BASE 0x7FFCC7A000ull 1255#define PSOC_PWM2_MAX_OFFSET 0x5800 1256#define PSOC_PWM2_SECTION 0x1000 1257#define mmPSOC_PWM3_BASE 0x7FFCC7B000ull 1258#define PSOC_PWM3_MAX_OFFSET 0x5800 1259#define PSOC_PWM3_SECTION 0x1000 1260#define mmPSOC_GPIO5_BASE 0x7FFCC7C000ull 1261#define PSOC_GPIO5_MAX_OFFSET 0x1000 1262#define PSOC_GPIO5_SECTION 0x1000 1263#define mmPSOC_GPIO6_BASE 0x7FFCC7D000ull 1264#define PSOC_GPIO6_MAX_OFFSET 0x1000 1265#define PSOC_GPIO6_SECTION 0x3000 1266#define mmPCIE_PMA_0_BASE 0x7FFCC80000ull 1267#define PCIE_PMA_0_MAX_OFFSET 0x10003 1268#define PCIE_PMA_0_SECTION 0x10000 1269#define mmPCIE_PMA_1_BASE 0x7FFCC90000ull 1270#define PCIE_PMA_1_MAX_OFFSET 0x10003 1271#define PCIE_PMA_1_SECTION 0x10000 1272#define mmPCIE_PMA_2_BASE 0x7FFCCA0000ull 1273#define PCIE_PMA_2_MAX_OFFSET 0x10003 1274#define PCIE_PMA_2_SECTION 0x10000 1275#define mmPCIE_PMA_3_BASE 0x7FFCCB0000ull 1276#define PCIE_PMA_3_MAX_OFFSET 0x10003 1277#define PCIE_PMA_3_SECTION 0x10000 1278#define mmNIC0_MAC_CH0_BASE 0x7FFCCC0000ull 1279#define NIC0_MAC_CH0_MAX_OFFSET 0x8400 1280#define NIC0_MAC_CH0_SECTION 0x1000 1281#define mmNIC0_MAC_CH1_BASE 0x7FFCCC1000ull 1282#define NIC0_MAC_CH1_MAX_OFFSET 0x8400 1283#define NIC0_MAC_CH1_SECTION 0x1000 1284#define mmNIC0_MAC_CH2_BASE 0x7FFCCC2000ull 1285#define NIC0_MAC_CH2_MAX_OFFSET 0x8400 1286#define NIC0_MAC_CH2_SECTION 0x1000 1287#define mmNIC0_MAC_CH3_BASE 0x7FFCCC3000ull 1288#define NIC0_MAC_CH3_MAX_OFFSET 0x8400 1289#define NIC0_MAC_CH3_SECTION 0x1000 1290#define mmNIC0_STAT_BASE 0x7FFCCC4000ull 1291#define NIC0_STAT_MAX_OFFSET 0x4D00 1292#define NIC0_STAT_SECTION 0x1000 1293#define mmNIC0_MAC_XPCS91_BASE 0x7FFCCC5000ull 1294#define NIC0_MAC_XPCS91_MAX_OFFSET 0x2380 1295#define NIC0_MAC_XPCS91_SECTION 0x3000 1296#define mmNIC0_MAC_CORE_BASE 0x7FFCCC8000ull 1297#define NIC0_MAC_CORE_MAX_OFFSET 0x5400 1298#define NIC0_MAC_CORE_SECTION 0x1000 1299#define mmNIC0_MAC_AUX_BASE 0x7FFCCC9000ull 1300#define NIC0_MAC_AUX_MAX_OFFSET 0x3000 1301#define NIC0_MAC_AUX_SECTION 0xF000 1302#define mmNIC0_PHY_BASE 0x7FFCCD8000ull 1303#define NIC0_PHY_MAX_OFFSET 0x3400 1304#define NIC0_PHY_SECTION 0x8000 1305#define mmNIC0_QM0_BASE 0x7FFCCE0000ull 1306#define NIC0_QM0_MAX_OFFSET 0xD040 1307#define NIC0_QM0_SECTION 0x2000 1308#define mmNIC0_QM1_BASE 0x7FFCCE2000ull 1309#define NIC0_QM1_MAX_OFFSET 0xD040 1310#define NIC0_QM1_SECTION 0x2000 1311#define mmNIC0_QPC0_BASE 0x7FFCCE4000ull 1312#define NIC0_QPC0_MAX_OFFSET 0x7140 1313#define NIC0_QPC0_SECTION 0x1000 1314#define mmNIC0_QPC1_BASE 0x7FFCCE5000ull 1315#define NIC0_QPC1_MAX_OFFSET 0x7140 1316#define NIC0_QPC1_SECTION 0x3000 1317#define mmNIC0_RXB_BASE 0x7FFCCE8000ull 1318#define NIC0_RXB_MAX_OFFSET 0x6040 1319#define NIC0_RXB_SECTION 0x1000 1320#define mmNIC0_RXE0_BASE 0x7FFCCE9000ull 1321#define NIC0_RXE0_MAX_OFFSET 0x2FC0 1322#define NIC0_RXE0_SECTION 0x1000 1323#define mmNIC0_RXE1_BASE 0x7FFCCEA000ull 1324#define NIC0_RXE1_MAX_OFFSET 0x2FC0 1325#define NIC0_RXE1_SECTION 0x1000 1326#define mmNIC0_RX_GW_BASE 0x7FFCCEB000ull 1327#define NIC0_RX_GW_MAX_OFFSET 0x4540 1328#define NIC0_RX_GW_SECTION 0x5000 1329#define mmNIC0_TXS0_BASE 0x7FFCCF0000ull 1330#define NIC0_TXS0_MAX_OFFSET 0x19C0 1331#define NIC0_TXS0_SECTION 0x1000 1332#define mmNIC0_TXS1_BASE 0x7FFCCF1000ull 1333#define NIC0_TXS1_MAX_OFFSET 0x19C0 1334#define NIC0_TXS1_SECTION 0x1000 1335#define mmNIC0_TXE0_BASE 0x7FFCCF2000ull 1336#define NIC0_TXE0_MAX_OFFSET 0x2040 1337#define NIC0_TXE0_SECTION 0x1000 1338#define mmNIC0_TXE1_BASE 0x7FFCCF3000ull 1339#define NIC0_TXE1_MAX_OFFSET 0x2040 1340#define NIC0_TXE1_SECTION 0x1000 1341#define mmNIC0_TXB_BASE 0x7FFCCF4000ull 1342#define NIC0_TXB_MAX_OFFSET 0xD400 1343#define NIC0_TXB_SECTION 0x1000 1344#define mmNIC0_TMR_BASE 0x7FFCCF5000ull 1345#define NIC0_TMR_MAX_OFFSET 0x1600 1346#define NIC0_TMR_SECTION 0x1000 1347#define mmNIC0_TX_GW_BASE 0x7FFCCF6000ull 1348#define NIC0_TX_GW_MAX_OFFSET 0x1400 1349#define NIC0_TX_GW_SECTION 0x2000 1350#define mmNIC0_TS_BASE 0x7FFCCF8000ull 1351#define NIC0_TS_MAX_OFFSET 0xE640 1352#define NIC0_TS_SECTION 0x1000 1353#define mmNIC0_PLL_BASE 0x7FFCCF9000ull 1354#define NIC0_PLL_MAX_OFFSET 0x5200 1355#define NIC0_PLL_SECTION 0x1000 1356#define mmNIC0_PM_BASE 0x7FFCCFA000ull 1357#define NIC0_PM_MAX_OFFSET 0x1F00 1358#define NIC0_PM_SECTION 0x6000 1359#define mmNIC1_MAC_CH0_BASE 0x7FFCD00000ull 1360#define NIC1_MAC_CH0_MAX_OFFSET 0x8400 1361#define NIC1_MAC_CH0_SECTION 0x1000 1362#define mmNIC1_MAC_CH1_BASE 0x7FFCD01000ull 1363#define NIC1_MAC_CH1_MAX_OFFSET 0x8400 1364#define NIC1_MAC_CH1_SECTION 0x1000 1365#define mmNIC1_MAC_CH2_BASE 0x7FFCD02000ull 1366#define NIC1_MAC_CH2_MAX_OFFSET 0x8400 1367#define NIC1_MAC_CH2_SECTION 0x1000 1368#define mmNIC1_MAC_CH3_BASE 0x7FFCD03000ull 1369#define NIC1_MAC_CH3_MAX_OFFSET 0x8400 1370#define NIC1_MAC_CH3_SECTION 0x1000 1371#define mmNIC1_STAT_BASE 0x7FFCD04000ull 1372#define NIC1_STAT_MAX_OFFSET 0x4D00 1373#define NIC1_STAT_SECTION 0x1000 1374#define mmNIC1_MAC_XPCS91_BASE 0x7FFCD05000ull 1375#define NIC1_MAC_XPCS91_MAX_OFFSET 0x2380 1376#define NIC1_MAC_XPCS91_SECTION 0x3000 1377#define mmNIC1_MAC_CORE_BASE 0x7FFCD08000ull 1378#define NIC1_MAC_CORE_MAX_OFFSET 0x5400 1379#define NIC1_MAC_CORE_SECTION 0x1000 1380#define mmNIC1_MAC_AUX_BASE 0x7FFCD09000ull 1381#define NIC1_MAC_AUX_MAX_OFFSET 0x3000 1382#define NIC1_MAC_AUX_SECTION 0xF000 1383#define mmNIC1_PHY_BASE 0x7FFCD18000ull 1384#define NIC1_PHY_MAX_OFFSET 0x3400 1385#define NIC1_PHY_SECTION 0x8000 1386#define mmNIC1_QM0_BASE 0x7FFCD20000ull 1387#define NIC1_QM0_MAX_OFFSET 0xD040 1388#define NIC1_QM0_SECTION 0x2000 1389#define mmNIC1_QM1_BASE 0x7FFCD22000ull 1390#define NIC1_QM1_MAX_OFFSET 0xD040 1391#define NIC1_QM1_SECTION 0x2000 1392#define mmNIC1_QPC0_BASE 0x7FFCD24000ull 1393#define NIC1_QPC0_MAX_OFFSET 0x7140 1394#define NIC1_QPC0_SECTION 0x1000 1395#define mmNIC1_QPC1_BASE 0x7FFCD25000ull 1396#define NIC1_QPC1_MAX_OFFSET 0x7140 1397#define NIC1_QPC1_SECTION 0x3000 1398#define mmNIC1_RXB_BASE 0x7FFCD28000ull 1399#define NIC1_RXB_MAX_OFFSET 0x6040 1400#define NIC1_RXB_SECTION 0x1000 1401#define mmNIC1_RXE0_BASE 0x7FFCD29000ull 1402#define NIC1_RXE0_MAX_OFFSET 0x2FC0 1403#define NIC1_RXE0_SECTION 0x1000 1404#define mmNIC1_RXE1_BASE 0x7FFCD2A000ull 1405#define NIC1_RXE1_MAX_OFFSET 0x2FC0 1406#define NIC1_RXE1_SECTION 0x1000 1407#define mmNIC1_RX_GW_BASE 0x7FFCD2B000ull 1408#define NIC1_RX_GW_MAX_OFFSET 0x4540 1409#define NIC1_RX_GW_SECTION 0x5000 1410#define mmNIC1_TXS0_BASE 0x7FFCD30000ull 1411#define NIC1_TXS0_MAX_OFFSET 0x19C0 1412#define NIC1_TXS0_SECTION 0x1000 1413#define mmNIC1_TXS1_BASE 0x7FFCD31000ull 1414#define NIC1_TXS1_MAX_OFFSET 0x19C0 1415#define NIC1_TXS1_SECTION 0x1000 1416#define mmNIC1_TXE0_BASE 0x7FFCD32000ull 1417#define NIC1_TXE0_MAX_OFFSET 0x2040 1418#define NIC1_TXE0_SECTION 0x1000 1419#define mmNIC1_TXE1_BASE 0x7FFCD33000ull 1420#define NIC1_TXE1_MAX_OFFSET 0x2040 1421#define NIC1_TXE1_SECTION 0x1000 1422#define mmNIC1_TXB_BASE 0x7FFCD34000ull 1423#define NIC1_TXB_MAX_OFFSET 0xD400 1424#define NIC1_TXB_SECTION 0x1000 1425#define mmNIC1_TMR_BASE 0x7FFCD35000ull 1426#define NIC1_TMR_MAX_OFFSET 0x1600 1427#define NIC1_TMR_SECTION 0x1000 1428#define mmNIC1_TX_GW_BASE 0x7FFCD36000ull 1429#define NIC1_TX_GW_MAX_OFFSET 0x1400 1430#define NIC1_TX_GW_SECTION 0x2000 1431#define mmNIC1_TS_BASE 0x7FFCD38000ull 1432#define NIC1_TS_MAX_OFFSET 0xE640 1433#define NIC1_TS_SECTION 0x1000 1434#define mmNIC1_PLL_BASE 0x7FFCD39000ull 1435#define NIC1_PLL_MAX_OFFSET 0x5200 1436#define NIC1_PLL_SECTION 0x1000 1437#define mmNIC1_PM_BASE 0x7FFCD3A000ull 1438#define NIC1_PM_MAX_OFFSET 0x1F00 1439#define NIC1_PM_SECTION 0x6000 1440#define mmNIC2_MAC_CH0_BASE 0x7FFCD40000ull 1441#define NIC2_MAC_CH0_MAX_OFFSET 0x8400 1442#define NIC2_MAC_CH0_SECTION 0x1000 1443#define mmNIC2_MAC_CH1_BASE 0x7FFCD41000ull 1444#define NIC2_MAC_CH1_MAX_OFFSET 0x8400 1445#define NIC2_MAC_CH1_SECTION 0x1000 1446#define mmNIC2_MAC_CH2_BASE 0x7FFCD42000ull 1447#define NIC2_MAC_CH2_MAX_OFFSET 0x8400 1448#define NIC2_MAC_CH2_SECTION 0x1000 1449#define mmNIC2_MAC_CH3_BASE 0x7FFCD43000ull 1450#define NIC2_MAC_CH3_MAX_OFFSET 0x8400 1451#define NIC2_MAC_CH3_SECTION 0x1000 1452#define mmNIC2_STAT_BASE 0x7FFCD44000ull 1453#define NIC2_STAT_MAX_OFFSET 0x4D00 1454#define NIC2_STAT_SECTION 0x1000 1455#define mmNIC2_MAC_XPCS91_BASE 0x7FFCD45000ull 1456#define NIC2_MAC_XPCS91_MAX_OFFSET 0x2380 1457#define NIC2_MAC_XPCS91_SECTION 0x3000 1458#define mmNIC2_MAC_CORE_BASE 0x7FFCD48000ull 1459#define NIC2_MAC_CORE_MAX_OFFSET 0x5400 1460#define NIC2_MAC_CORE_SECTION 0x1000 1461#define mmNIC2_MAC_AUX_BASE 0x7FFCD49000ull 1462#define NIC2_MAC_AUX_MAX_OFFSET 0x3000 1463#define NIC2_MAC_AUX_SECTION 0xF000 1464#define mmNIC2_PHY_BASE 0x7FFCD58000ull 1465#define NIC2_PHY_MAX_OFFSET 0x3400 1466#define NIC2_PHY_SECTION 0x8000 1467#define mmNIC2_QM0_BASE 0x7FFCD60000ull 1468#define NIC2_QM0_MAX_OFFSET 0xD040 1469#define NIC2_QM0_SECTION 0x2000 1470#define mmNIC2_QM1_BASE 0x7FFCD62000ull 1471#define NIC2_QM1_MAX_OFFSET 0xD040 1472#define NIC2_QM1_SECTION 0x2000 1473#define mmNIC2_QPC0_BASE 0x7FFCD64000ull 1474#define NIC2_QPC0_MAX_OFFSET 0x7140 1475#define NIC2_QPC0_SECTION 0x1000 1476#define mmNIC2_QPC1_BASE 0x7FFCD65000ull 1477#define NIC2_QPC1_MAX_OFFSET 0x7140 1478#define NIC2_QPC1_SECTION 0x3000 1479#define mmNIC2_RXB_BASE 0x7FFCD68000ull 1480#define NIC2_RXB_MAX_OFFSET 0x6040 1481#define NIC2_RXB_SECTION 0x1000 1482#define mmNIC2_RXE0_BASE 0x7FFCD69000ull 1483#define NIC2_RXE0_MAX_OFFSET 0x2FC0 1484#define NIC2_RXE0_SECTION 0x1000 1485#define mmNIC2_RXE1_BASE 0x7FFCD6A000ull 1486#define NIC2_RXE1_MAX_OFFSET 0x2FC0 1487#define NIC2_RXE1_SECTION 0x1000 1488#define mmNIC2_RX_GW_BASE 0x7FFCD6B000ull 1489#define NIC2_RX_GW_MAX_OFFSET 0x4540 1490#define NIC2_RX_GW_SECTION 0x5000 1491#define mmNIC2_TXS0_BASE 0x7FFCD70000ull 1492#define NIC2_TXS0_MAX_OFFSET 0x19C0 1493#define NIC2_TXS0_SECTION 0x1000 1494#define mmNIC2_TXS1_BASE 0x7FFCD71000ull 1495#define NIC2_TXS1_MAX_OFFSET 0x19C0 1496#define NIC2_TXS1_SECTION 0x1000 1497#define mmNIC2_TXE0_BASE 0x7FFCD72000ull 1498#define NIC2_TXE0_MAX_OFFSET 0x2040 1499#define NIC2_TXE0_SECTION 0x1000 1500#define mmNIC2_TXE1_BASE 0x7FFCD73000ull 1501#define NIC2_TXE1_MAX_OFFSET 0x2040 1502#define NIC2_TXE1_SECTION 0x1000 1503#define mmNIC2_TXB_BASE 0x7FFCD74000ull 1504#define NIC2_TXB_MAX_OFFSET 0xD400 1505#define NIC2_TXB_SECTION 0x1000 1506#define mmNIC2_TMR_BASE 0x7FFCD75000ull 1507#define NIC2_TMR_MAX_OFFSET 0x1600 1508#define NIC2_TMR_SECTION 0x1000 1509#define mmNIC2_TX_GW_BASE 0x7FFCD76000ull 1510#define NIC2_TX_GW_MAX_OFFSET 0x1400 1511#define NIC2_TX_GW_SECTION 0x2000 1512#define mmNIC2_HBM_PLL_BASE 0x7FFCD78000ull 1513#define NIC2_HBM_PLL_MAX_OFFSET 0x5200 1514#define NIC2_HBM_PLL_SECTION 0x1000 1515#define mmNIC2_MME_PLL_BASE 0x7FFCD79000ull 1516#define NIC2_MME_PLL_MAX_OFFSET 0x5200 1517#define NIC2_MME_PLL_SECTION 0x1000 1518#define mmNIC2_TPC_PLL_BASE 0x7FFCD7A000ull 1519#define NIC2_TPC_PLL_MAX_OFFSET 0x5200 1520#define NIC2_TPC_PLL_SECTION 0x6000 1521#define mmNIC3_MAC_CH0_BASE 0x7FFCD80000ull 1522#define NIC3_MAC_CH0_MAX_OFFSET 0x8400 1523#define NIC3_MAC_CH0_SECTION 0x1000 1524#define mmNIC3_MAC_CH1_BASE 0x7FFCD81000ull 1525#define NIC3_MAC_CH1_MAX_OFFSET 0x8400 1526#define NIC3_MAC_CH1_SECTION 0x1000 1527#define mmNIC3_MAC_CH2_BASE 0x7FFCD82000ull 1528#define NIC3_MAC_CH2_MAX_OFFSET 0x8400 1529#define NIC3_MAC_CH2_SECTION 0x1000 1530#define mmNIC3_MAC_CH3_BASE 0x7FFCD83000ull 1531#define NIC3_MAC_CH3_MAX_OFFSET 0x8400 1532#define NIC3_MAC_CH3_SECTION 0x1000 1533#define mmNIC3_STAT_BASE 0x7FFCD84000ull 1534#define NIC3_STAT_MAX_OFFSET 0x4D00 1535#define NIC3_STAT_SECTION 0x1000 1536#define mmNIC3_MAC_XPCS91_BASE 0x7FFCD85000ull 1537#define NIC3_MAC_XPCS91_MAX_OFFSET 0x2380 1538#define NIC3_MAC_XPCS91_SECTION 0x3000 1539#define mmNIC3_MAC_CORE_BASE 0x7FFCD88000ull 1540#define NIC3_MAC_CORE_MAX_OFFSET 0x5400 1541#define NIC3_MAC_CORE_SECTION 0x1000 1542#define mmNIC3_MAC_AUX_BASE 0x7FFCD89000ull 1543#define NIC3_MAC_AUX_MAX_OFFSET 0x3000 1544#define NIC3_MAC_AUX_SECTION 0xF000 1545#define mmNIC3_PHY_BASE 0x7FFCD98000ull 1546#define NIC3_PHY_MAX_OFFSET 0x3400 1547#define NIC3_PHY_SECTION 0x8000 1548#define mmNIC3_QM0_BASE 0x7FFCDA0000ull 1549#define NIC3_QM0_MAX_OFFSET 0xD040 1550#define NIC3_QM0_SECTION 0x2000 1551#define mmNIC3_QM1_BASE 0x7FFCDA2000ull 1552#define NIC3_QM1_MAX_OFFSET 0xD040 1553#define NIC3_QM1_SECTION 0x2000 1554#define mmNIC3_QPC0_BASE 0x7FFCDA4000ull 1555#define NIC3_QPC0_MAX_OFFSET 0x7140 1556#define NIC3_QPC0_SECTION 0x1000 1557#define mmNIC3_QPC1_BASE 0x7FFCDA5000ull 1558#define NIC3_QPC1_MAX_OFFSET 0x7140 1559#define NIC3_QPC1_SECTION 0x3000 1560#define mmNIC3_RXB_BASE 0x7FFCDA8000ull 1561#define NIC3_RXB_MAX_OFFSET 0x6040 1562#define NIC3_RXB_SECTION 0x1000 1563#define mmNIC3_RXE0_BASE 0x7FFCDA9000ull 1564#define NIC3_RXE0_MAX_OFFSET 0x2FC0 1565#define NIC3_RXE0_SECTION 0x1000 1566#define mmNIC3_RXE1_BASE 0x7FFCDAA000ull 1567#define NIC3_RXE1_MAX_OFFSET 0x2FC0 1568#define NIC3_RXE1_SECTION 0x1000 1569#define mmNIC3_RX_GW_BASE 0x7FFCDAB000ull 1570#define NIC3_RX_GW_MAX_OFFSET 0x4540 1571#define NIC3_RX_GW_SECTION 0x5000 1572#define mmNIC3_TXS0_BASE 0x7FFCDB0000ull 1573#define NIC3_TXS0_MAX_OFFSET 0x19C0 1574#define NIC3_TXS0_SECTION 0x1000 1575#define mmNIC3_TXS1_BASE 0x7FFCDB1000ull 1576#define NIC3_TXS1_MAX_OFFSET 0x19C0 1577#define NIC3_TXS1_SECTION 0x1000 1578#define mmNIC3_TXE0_BASE 0x7FFCDB2000ull 1579#define NIC3_TXE0_MAX_OFFSET 0x2040 1580#define NIC3_TXE0_SECTION 0x1000 1581#define mmNIC3_TXE1_BASE 0x7FFCDB3000ull 1582#define NIC3_TXE1_MAX_OFFSET 0x2040 1583#define NIC3_TXE1_SECTION 0x1000 1584#define mmNIC3_TXB_BASE 0x7FFCDB4000ull 1585#define NIC3_TXB_MAX_OFFSET 0xD400 1586#define NIC3_TXB_SECTION 0x1000 1587#define mmNIC3_TMR_BASE 0x7FFCDB5000ull 1588#define NIC3_TMR_MAX_OFFSET 0x1600 1589#define NIC3_TMR_SECTION 0x1000 1590#define mmNIC3_TX_GW_BASE 0x7FFCDB6000ull 1591#define NIC3_TX_GW_MAX_OFFSET 0x1400 1592#define NIC3_TX_GW_SECTION 0x2000 1593#define mmNIC3_TS_BASE 0x7FFCDB8000ull 1594#define NIC3_TS_MAX_OFFSET 0xE640 1595#define NIC3_TS_SECTION 0x2000 1596#define mmNIC3_PM_BASE 0x7FFCDBA000ull 1597#define NIC3_PM_MAX_OFFSET 0x1F00 1598#define NIC3_PM_SECTION 0x6000 1599#define mmNIC4_MAC_CH0_BASE 0x7FFCDC0000ull 1600#define NIC4_MAC_CH0_MAX_OFFSET 0x8400 1601#define NIC4_MAC_CH0_SECTION 0x1000 1602#define mmNIC4_MAC_CH1_BASE 0x7FFCDC1000ull 1603#define NIC4_MAC_CH1_MAX_OFFSET 0x8400 1604#define NIC4_MAC_CH1_SECTION 0x1000 1605#define mmNIC4_MAC_CH2_BASE 0x7FFCDC2000ull 1606#define NIC4_MAC_CH2_MAX_OFFSET 0x8400 1607#define NIC4_MAC_CH2_SECTION 0x1000 1608#define mmNIC4_MAC_CH3_BASE 0x7FFCDC3000ull 1609#define NIC4_MAC_CH3_MAX_OFFSET 0x8400 1610#define NIC4_MAC_CH3_SECTION 0x1000 1611#define mmNIC4_STAT_BASE 0x7FFCDC4000ull 1612#define NIC4_STAT_MAX_OFFSET 0x4D00 1613#define NIC4_STAT_SECTION 0x1000 1614#define mmNIC4_MAC_XPCS91_BASE 0x7FFCDC5000ull 1615#define NIC4_MAC_XPCS91_MAX_OFFSET 0x2380 1616#define NIC4_MAC_XPCS91_SECTION 0x3000 1617#define mmNIC4_MAC_CORE_BASE 0x7FFCDC8000ull 1618#define NIC4_MAC_CORE_MAX_OFFSET 0x5400 1619#define NIC4_MAC_CORE_SECTION 0x1000 1620#define mmNIC4_MAC_AUX_BASE 0x7FFCDC9000ull 1621#define NIC4_MAC_AUX_MAX_OFFSET 0x3000 1622#define NIC4_MAC_AUX_SECTION 0xF000 1623#define mmNIC4_PHY_BASE 0x7FFCDD8000ull 1624#define NIC4_PHY_MAX_OFFSET 0x3400 1625#define NIC4_PHY_SECTION 0x8000 1626#define mmNIC4_QM0_BASE 0x7FFCDE0000ull 1627#define NIC4_QM0_MAX_OFFSET 0xD040 1628#define NIC4_QM0_SECTION 0x2000 1629#define mmNIC4_QM1_BASE 0x7FFCDE2000ull 1630#define NIC4_QM1_MAX_OFFSET 0xD040 1631#define NIC4_QM1_SECTION 0x2000 1632#define mmNIC4_QPC0_BASE 0x7FFCDE4000ull 1633#define NIC4_QPC0_MAX_OFFSET 0x7140 1634#define NIC4_QPC0_SECTION 0x1000 1635#define mmNIC4_QPC1_BASE 0x7FFCDE5000ull 1636#define NIC4_QPC1_MAX_OFFSET 0x7140 1637#define NIC4_QPC1_SECTION 0x3000 1638#define mmNIC4_RXB_BASE 0x7FFCDE8000ull 1639#define NIC4_RXB_MAX_OFFSET 0x6040 1640#define NIC4_RXB_SECTION 0x1000 1641#define mmNIC4_RXE0_BASE 0x7FFCDE9000ull 1642#define NIC4_RXE0_MAX_OFFSET 0x2FC0 1643#define NIC4_RXE0_SECTION 0x1000 1644#define mmNIC4_RXE1_BASE 0x7FFCDEA000ull 1645#define NIC4_RXE1_MAX_OFFSET 0x2FC0 1646#define NIC4_RXE1_SECTION 0x1000 1647#define mmNIC4_RX_GW_BASE 0x7FFCDEB000ull 1648#define NIC4_RX_GW_MAX_OFFSET 0x4540 1649#define NIC4_RX_GW_SECTION 0x5000 1650#define mmNIC4_TXS0_BASE 0x7FFCDF0000ull 1651#define NIC4_TXS0_MAX_OFFSET 0x19C0 1652#define NIC4_TXS0_SECTION 0x1000 1653#define mmNIC4_TXS1_BASE 0x7FFCDF1000ull 1654#define NIC4_TXS1_MAX_OFFSET 0x19C0 1655#define NIC4_TXS1_SECTION 0x1000 1656#define mmNIC4_TXE0_BASE 0x7FFCDF2000ull 1657#define NIC4_TXE0_MAX_OFFSET 0x2040 1658#define NIC4_TXE0_SECTION 0x1000 1659#define mmNIC4_TXE1_BASE 0x7FFCDF3000ull 1660#define NIC4_TXE1_MAX_OFFSET 0x2040 1661#define NIC4_TXE1_SECTION 0x1000 1662#define mmNIC4_TXB_BASE 0x7FFCDF4000ull 1663#define NIC4_TXB_MAX_OFFSET 0xD400 1664#define NIC4_TXB_SECTION 0x1000 1665#define mmNIC4_TMR_BASE 0x7FFCDF5000ull 1666#define NIC4_TMR_MAX_OFFSET 0x1600 1667#define NIC4_TMR_SECTION 0x1000 1668#define mmNIC4_TX_GW_BASE 0x7FFCDF6000ull 1669#define NIC4_TX_GW_MAX_OFFSET 0x1400 1670#define NIC4_TX_GW_SECTION 0x10000 1671#define mmTPC0_CFG_BASE 0x7FFCE06000ull 1672#define TPC0_CFG_MAX_OFFSET 0xE400 1673#define TPC0_CFG_SECTION 0x4000 1674#define mmKERNEL_TENSOR_0_TPC0_CFG_BASE 0x7FFCE06400ull 1675#define KERNEL_TENSOR_0_TPC0_CFG_MAX_OFFSET 0x3800 1676#define KERNEL_TENSOR_0_TPC0_CFG_SECTION 0x3800 1677#define mmKERNEL_TENSOR_1_TPC0_CFG_BASE 0x7FFCE06438ull 1678#define KERNEL_TENSOR_1_TPC0_CFG_MAX_OFFSET 0x3800 1679#define KERNEL_TENSOR_1_TPC0_CFG_SECTION 0x3800 1680#define mmKERNEL_TENSOR_2_TPC0_CFG_BASE 0x7FFCE06470ull 1681#define KERNEL_TENSOR_2_TPC0_CFG_MAX_OFFSET 0x3800 1682#define KERNEL_TENSOR_2_TPC0_CFG_SECTION 0x3800 1683#define mmKERNEL_TENSOR_3_TPC0_CFG_BASE 0x7FFCE064A8ull 1684#define KERNEL_TENSOR_3_TPC0_CFG_MAX_OFFSET 0x3800 1685#define KERNEL_TENSOR_3_TPC0_CFG_SECTION 0x3800 1686#define mmKERNEL_TENSOR_4_TPC0_CFG_BASE 0x7FFCE064E0ull 1687#define KERNEL_TENSOR_4_TPC0_CFG_MAX_OFFSET 0x3800 1688#define KERNEL_TENSOR_4_TPC0_CFG_SECTION 0x3800 1689#define mmKERNEL_TENSOR_5_TPC0_CFG_BASE 0x7FFCE06518ull 1690#define KERNEL_TENSOR_5_TPC0_CFG_MAX_OFFSET 0x3800 1691#define KERNEL_TENSOR_5_TPC0_CFG_SECTION 0x3800 1692#define mmKERNEL_TENSOR_6_TPC0_CFG_BASE 0x7FFCE06550ull 1693#define KERNEL_TENSOR_6_TPC0_CFG_MAX_OFFSET 0x3800 1694#define KERNEL_TENSOR_6_TPC0_CFG_SECTION 0x3800 1695#define mmKERNEL_TENSOR_7_TPC0_CFG_BASE 0x7FFCE06588ull 1696#define KERNEL_TENSOR_7_TPC0_CFG_MAX_OFFSET 0x3800 1697#define KERNEL_TENSOR_7_TPC0_CFG_SECTION 0x3800 1698#define mmKERNEL_TENSOR_8_TPC0_CFG_BASE 0x7FFCE065C0ull 1699#define KERNEL_TENSOR_8_TPC0_CFG_MAX_OFFSET 0x3800 1700#define KERNEL_TENSOR_8_TPC0_CFG_SECTION 0x3800 1701#define mmKERNEL_TENSOR_9_TPC0_CFG_BASE 0x7FFCE065F8ull 1702#define KERNEL_TENSOR_9_TPC0_CFG_MAX_OFFSET 0x3800 1703#define KERNEL_TENSOR_9_TPC0_CFG_SECTION 0x3800 1704#define mmKERNEL_TENSOR_10_TPC0_CFG_BASE 0x7FFCE06630ull 1705#define KERNEL_TENSOR_10_TPC0_CFG_MAX_OFFSET 0x3800 1706#define KERNEL_TENSOR_10_TPC0_CFG_SECTION 0x3800 1707#define mmKERNEL_TENSOR_11_TPC0_CFG_BASE 0x7FFCE06668ull 1708#define KERNEL_TENSOR_11_TPC0_CFG_MAX_OFFSET 0x3800 1709#define KERNEL_TENSOR_11_TPC0_CFG_SECTION 0x3800 1710#define mmKERNEL_TENSOR_12_TPC0_CFG_BASE 0x7FFCE066A0ull 1711#define KERNEL_TENSOR_12_TPC0_CFG_MAX_OFFSET 0x3800 1712#define KERNEL_TENSOR_12_TPC0_CFG_SECTION 0x3800 1713#define mmKERNEL_TENSOR_13_TPC0_CFG_BASE 0x7FFCE066D8ull 1714#define KERNEL_TENSOR_13_TPC0_CFG_MAX_OFFSET 0x3800 1715#define KERNEL_TENSOR_13_TPC0_CFG_SECTION 0x3800 1716#define mmKERNEL_TENSOR_14_TPC0_CFG_BASE 0x7FFCE06710ull 1717#define KERNEL_TENSOR_14_TPC0_CFG_MAX_OFFSET 0x3800 1718#define KERNEL_TENSOR_14_TPC0_CFG_SECTION 0x3800 1719#define mmKERNEL_TENSOR_15_TPC0_CFG_BASE 0x7FFCE06748ull 1720#define KERNEL_TENSOR_15_TPC0_CFG_MAX_OFFSET 0x3800 1721#define KERNEL_TENSOR_15_TPC0_CFG_SECTION 0x3800 1722#define mmKERNEL_SYNC_OBJECT_TPC0_CFG_BASE 0x7FFCE06780ull 1723#define KERNEL_SYNC_OBJECT_TPC0_CFG_MAX_OFFSET 0x8000 1724#define KERNEL_SYNC_OBJECT_TPC0_CFG_SECTION 0x8000 1725#define mmKERNEL_TPC0_CFG_BASE 0x7FFCE06788ull 1726#define KERNEL_TPC0_CFG_MAX_OFFSET 0xB800 1727#define KERNEL_TPC0_CFG_SECTION 0x2780 1728#define mmQM_TENSOR_0_TPC0_CFG_BASE 0x7FFCE06A00ull 1729#define QM_TENSOR_0_TPC0_CFG_MAX_OFFSET 0x3800 1730#define QM_TENSOR_0_TPC0_CFG_SECTION 0x3800 1731#define mmQM_TENSOR_1_TPC0_CFG_BASE 0x7FFCE06A38ull 1732#define QM_TENSOR_1_TPC0_CFG_MAX_OFFSET 0x3800 1733#define QM_TENSOR_1_TPC0_CFG_SECTION 0x3800 1734#define mmQM_TENSOR_2_TPC0_CFG_BASE 0x7FFCE06A70ull 1735#define QM_TENSOR_2_TPC0_CFG_MAX_OFFSET 0x3800 1736#define QM_TENSOR_2_TPC0_CFG_SECTION 0x3800 1737#define mmQM_TENSOR_3_TPC0_CFG_BASE 0x7FFCE06AA8ull 1738#define QM_TENSOR_3_TPC0_CFG_MAX_OFFSET 0x3800 1739#define QM_TENSOR_3_TPC0_CFG_SECTION 0x3800 1740#define mmQM_TENSOR_4_TPC0_CFG_BASE 0x7FFCE06AE0ull 1741#define QM_TENSOR_4_TPC0_CFG_MAX_OFFSET 0x3800 1742#define QM_TENSOR_4_TPC0_CFG_SECTION 0x3800 1743#define mmQM_TENSOR_5_TPC0_CFG_BASE 0x7FFCE06B18ull 1744#define QM_TENSOR_5_TPC0_CFG_MAX_OFFSET 0x3800 1745#define QM_TENSOR_5_TPC0_CFG_SECTION 0x3800 1746#define mmQM_TENSOR_6_TPC0_CFG_BASE 0x7FFCE06B50ull 1747#define QM_TENSOR_6_TPC0_CFG_MAX_OFFSET 0x3800 1748#define QM_TENSOR_6_TPC0_CFG_SECTION 0x3800 1749#define mmQM_TENSOR_7_TPC0_CFG_BASE 0x7FFCE06B88ull 1750#define QM_TENSOR_7_TPC0_CFG_MAX_OFFSET 0x3800 1751#define QM_TENSOR_7_TPC0_CFG_SECTION 0x3800 1752#define mmQM_TENSOR_8_TPC0_CFG_BASE 0x7FFCE06BC0ull 1753#define QM_TENSOR_8_TPC0_CFG_MAX_OFFSET 0x3800 1754#define QM_TENSOR_8_TPC0_CFG_SECTION 0x3800 1755#define mmQM_TENSOR_9_TPC0_CFG_BASE 0x7FFCE06BF8ull 1756#define QM_TENSOR_9_TPC0_CFG_MAX_OFFSET 0x3800 1757#define QM_TENSOR_9_TPC0_CFG_SECTION 0x3800 1758#define mmQM_TENSOR_10_TPC0_CFG_BASE 0x7FFCE06C30ull 1759#define QM_TENSOR_10_TPC0_CFG_MAX_OFFSET 0x3800 1760#define QM_TENSOR_10_TPC0_CFG_SECTION 0x3800 1761#define mmQM_TENSOR_11_TPC0_CFG_BASE 0x7FFCE06C68ull 1762#define QM_TENSOR_11_TPC0_CFG_MAX_OFFSET 0x3800 1763#define QM_TENSOR_11_TPC0_CFG_SECTION 0x3800 1764#define mmQM_TENSOR_12_TPC0_CFG_BASE 0x7FFCE06CA0ull 1765#define QM_TENSOR_12_TPC0_CFG_MAX_OFFSET 0x3800 1766#define QM_TENSOR_12_TPC0_CFG_SECTION 0x3800 1767#define mmQM_TENSOR_13_TPC0_CFG_BASE 0x7FFCE06CD8ull 1768#define QM_TENSOR_13_TPC0_CFG_MAX_OFFSET 0x3800 1769#define QM_TENSOR_13_TPC0_CFG_SECTION 0x3800 1770#define mmQM_TENSOR_14_TPC0_CFG_BASE 0x7FFCE06D10ull 1771#define QM_TENSOR_14_TPC0_CFG_MAX_OFFSET 0x3800 1772#define QM_TENSOR_14_TPC0_CFG_SECTION 0x3800 1773#define mmQM_TENSOR_15_TPC0_CFG_BASE 0x7FFCE06D48ull 1774#define QM_TENSOR_15_TPC0_CFG_MAX_OFFSET 0x3800 1775#define QM_TENSOR_15_TPC0_CFG_SECTION 0x3800 1776#define mmQM_SYNC_OBJECT_TPC0_CFG_BASE 0x7FFCE06D80ull 1777#define QM_SYNC_OBJECT_TPC0_CFG_MAX_OFFSET 0x8000 1778#define QM_SYNC_OBJECT_TPC0_CFG_SECTION 0x8000 1779#define mmQM_TPC0_CFG_BASE 0x7FFCE06D88ull 1780#define QM_TPC0_CFG_MAX_OFFSET 0xB800 1781#define QM_TPC0_CFG_SECTION 0x2780 1782#define mmTPC0_E2E_CRED_BASE 0x7FFCE07000ull 1783#define TPC0_E2E_CRED_MAX_OFFSET 0x1680 1784#define TPC0_E2E_CRED_SECTION 0x1000 1785#define mmTPC0_QM_BASE 0x7FFCE08000ull 1786#define TPC0_QM_MAX_OFFSET 0xD040 1787#define TPC0_QM_SECTION 0x3E000 1788#define mmTPC1_CFG_BASE 0x7FFCE46000ull 1789#define TPC1_CFG_MAX_OFFSET 0xE400 1790#define TPC1_CFG_SECTION 0x4000 1791#define mmKERNEL_TENSOR_0_TPC1_CFG_BASE 0x7FFCE46400ull 1792#define KERNEL_TENSOR_0_TPC1_CFG_MAX_OFFSET 0x3800 1793#define KERNEL_TENSOR_0_TPC1_CFG_SECTION 0x3800 1794#define mmKERNEL_TENSOR_1_TPC1_CFG_BASE 0x7FFCE46438ull 1795#define KERNEL_TENSOR_1_TPC1_CFG_MAX_OFFSET 0x3800 1796#define KERNEL_TENSOR_1_TPC1_CFG_SECTION 0x3800 1797#define mmKERNEL_TENSOR_2_TPC1_CFG_BASE 0x7FFCE46470ull 1798#define KERNEL_TENSOR_2_TPC1_CFG_MAX_OFFSET 0x3800 1799#define KERNEL_TENSOR_2_TPC1_CFG_SECTION 0x3800 1800#define mmKERNEL_TENSOR_3_TPC1_CFG_BASE 0x7FFCE464A8ull 1801#define KERNEL_TENSOR_3_TPC1_CFG_MAX_OFFSET 0x3800 1802#define KERNEL_TENSOR_3_TPC1_CFG_SECTION 0x3800 1803#define mmKERNEL_TENSOR_4_TPC1_CFG_BASE 0x7FFCE464E0ull 1804#define KERNEL_TENSOR_4_TPC1_CFG_MAX_OFFSET 0x3800 1805#define KERNEL_TENSOR_4_TPC1_CFG_SECTION 0x3800 1806#define mmKERNEL_TENSOR_5_TPC1_CFG_BASE 0x7FFCE46518ull 1807#define KERNEL_TENSOR_5_TPC1_CFG_MAX_OFFSET 0x3800 1808#define KERNEL_TENSOR_5_TPC1_CFG_SECTION 0x3800 1809#define mmKERNEL_TENSOR_6_TPC1_CFG_BASE 0x7FFCE46550ull 1810#define KERNEL_TENSOR_6_TPC1_CFG_MAX_OFFSET 0x3800 1811#define KERNEL_TENSOR_6_TPC1_CFG_SECTION 0x3800 1812#define mmKERNEL_TENSOR_7_TPC1_CFG_BASE 0x7FFCE46588ull 1813#define KERNEL_TENSOR_7_TPC1_CFG_MAX_OFFSET 0x3800 1814#define KERNEL_TENSOR_7_TPC1_CFG_SECTION 0x3800 1815#define mmKERNEL_TENSOR_8_TPC1_CFG_BASE 0x7FFCE465C0ull 1816#define KERNEL_TENSOR_8_TPC1_CFG_MAX_OFFSET 0x3800 1817#define KERNEL_TENSOR_8_TPC1_CFG_SECTION 0x3800 1818#define mmKERNEL_TENSOR_9_TPC1_CFG_BASE 0x7FFCE465F8ull 1819#define KERNEL_TENSOR_9_TPC1_CFG_MAX_OFFSET 0x3800 1820#define KERNEL_TENSOR_9_TPC1_CFG_SECTION 0x3800 1821#define mmKERNEL_TENSOR_10_TPC1_CFG_BASE 0x7FFCE46630ull 1822#define KERNEL_TENSOR_10_TPC1_CFG_MAX_OFFSET 0x3800 1823#define KERNEL_TENSOR_10_TPC1_CFG_SECTION 0x3800 1824#define mmKERNEL_TENSOR_11_TPC1_CFG_BASE 0x7FFCE46668ull 1825#define KERNEL_TENSOR_11_TPC1_CFG_MAX_OFFSET 0x3800 1826#define KERNEL_TENSOR_11_TPC1_CFG_SECTION 0x3800 1827#define mmKERNEL_TENSOR_12_TPC1_CFG_BASE 0x7FFCE466A0ull 1828#define KERNEL_TENSOR_12_TPC1_CFG_MAX_OFFSET 0x3800 1829#define KERNEL_TENSOR_12_TPC1_CFG_SECTION 0x3800 1830#define mmKERNEL_TENSOR_13_TPC1_CFG_BASE 0x7FFCE466D8ull 1831#define KERNEL_TENSOR_13_TPC1_CFG_MAX_OFFSET 0x3800 1832#define KERNEL_TENSOR_13_TPC1_CFG_SECTION 0x3800 1833#define mmKERNEL_TENSOR_14_TPC1_CFG_BASE 0x7FFCE46710ull 1834#define KERNEL_TENSOR_14_TPC1_CFG_MAX_OFFSET 0x3800 1835#define KERNEL_TENSOR_14_TPC1_CFG_SECTION 0x3800 1836#define mmKERNEL_TENSOR_15_TPC1_CFG_BASE 0x7FFCE46748ull 1837#define KERNEL_TENSOR_15_TPC1_CFG_MAX_OFFSET 0x3800 1838#define KERNEL_TENSOR_15_TPC1_CFG_SECTION 0x3800 1839#define mmKERNEL_SYNC_OBJECT_TPC1_CFG_BASE 0x7FFCE46780ull 1840#define KERNEL_SYNC_OBJECT_TPC1_CFG_MAX_OFFSET 0x8000 1841#define KERNEL_SYNC_OBJECT_TPC1_CFG_SECTION 0x8000 1842#define mmKERNEL_TPC1_CFG_BASE 0x7FFCE46788ull 1843#define KERNEL_TPC1_CFG_MAX_OFFSET 0xB800 1844#define KERNEL_TPC1_CFG_SECTION 0x2780 1845#define mmQM_TENSOR_0_TPC1_CFG_BASE 0x7FFCE46A00ull 1846#define QM_TENSOR_0_TPC1_CFG_MAX_OFFSET 0x3800 1847#define QM_TENSOR_0_TPC1_CFG_SECTION 0x3800 1848#define mmQM_TENSOR_1_TPC1_CFG_BASE 0x7FFCE46A38ull 1849#define QM_TENSOR_1_TPC1_CFG_MAX_OFFSET 0x3800 1850#define QM_TENSOR_1_TPC1_CFG_SECTION 0x3800 1851#define mmQM_TENSOR_2_TPC1_CFG_BASE 0x7FFCE46A70ull 1852#define QM_TENSOR_2_TPC1_CFG_MAX_OFFSET 0x3800 1853#define QM_TENSOR_2_TPC1_CFG_SECTION 0x3800 1854#define mmQM_TENSOR_3_TPC1_CFG_BASE 0x7FFCE46AA8ull 1855#define QM_TENSOR_3_TPC1_CFG_MAX_OFFSET 0x3800 1856#define QM_TENSOR_3_TPC1_CFG_SECTION 0x3800 1857#define mmQM_TENSOR_4_TPC1_CFG_BASE 0x7FFCE46AE0ull 1858#define QM_TENSOR_4_TPC1_CFG_MAX_OFFSET 0x3800 1859#define QM_TENSOR_4_TPC1_CFG_SECTION 0x3800 1860#define mmQM_TENSOR_5_TPC1_CFG_BASE 0x7FFCE46B18ull 1861#define QM_TENSOR_5_TPC1_CFG_MAX_OFFSET 0x3800 1862#define QM_TENSOR_5_TPC1_CFG_SECTION 0x3800 1863#define mmQM_TENSOR_6_TPC1_CFG_BASE 0x7FFCE46B50ull 1864#define QM_TENSOR_6_TPC1_CFG_MAX_OFFSET 0x3800 1865#define QM_TENSOR_6_TPC1_CFG_SECTION 0x3800 1866#define mmQM_TENSOR_7_TPC1_CFG_BASE 0x7FFCE46B88ull 1867#define QM_TENSOR_7_TPC1_CFG_MAX_OFFSET 0x3800 1868#define QM_TENSOR_7_TPC1_CFG_SECTION 0x3800 1869#define mmQM_TENSOR_8_TPC1_CFG_BASE 0x7FFCE46BC0ull 1870#define QM_TENSOR_8_TPC1_CFG_MAX_OFFSET 0x3800 1871#define QM_TENSOR_8_TPC1_CFG_SECTION 0x3800 1872#define mmQM_TENSOR_9_TPC1_CFG_BASE 0x7FFCE46BF8ull 1873#define QM_TENSOR_9_TPC1_CFG_MAX_OFFSET 0x3800 1874#define QM_TENSOR_9_TPC1_CFG_SECTION 0x3800 1875#define mmQM_TENSOR_10_TPC1_CFG_BASE 0x7FFCE46C30ull 1876#define QM_TENSOR_10_TPC1_CFG_MAX_OFFSET 0x3800 1877#define QM_TENSOR_10_TPC1_CFG_SECTION 0x3800 1878#define mmQM_TENSOR_11_TPC1_CFG_BASE 0x7FFCE46C68ull 1879#define QM_TENSOR_11_TPC1_CFG_MAX_OFFSET 0x3800 1880#define QM_TENSOR_11_TPC1_CFG_SECTION 0x3800 1881#define mmQM_TENSOR_12_TPC1_CFG_BASE 0x7FFCE46CA0ull 1882#define QM_TENSOR_12_TPC1_CFG_MAX_OFFSET 0x3800 1883#define QM_TENSOR_12_TPC1_CFG_SECTION 0x3800 1884#define mmQM_TENSOR_13_TPC1_CFG_BASE 0x7FFCE46CD8ull 1885#define QM_TENSOR_13_TPC1_CFG_MAX_OFFSET 0x3800 1886#define QM_TENSOR_13_TPC1_CFG_SECTION 0x3800 1887#define mmQM_TENSOR_14_TPC1_CFG_BASE 0x7FFCE46D10ull 1888#define QM_TENSOR_14_TPC1_CFG_MAX_OFFSET 0x3800 1889#define QM_TENSOR_14_TPC1_CFG_SECTION 0x3800 1890#define mmQM_TENSOR_15_TPC1_CFG_BASE 0x7FFCE46D48ull 1891#define QM_TENSOR_15_TPC1_CFG_MAX_OFFSET 0x3800 1892#define QM_TENSOR_15_TPC1_CFG_SECTION 0x3800 1893#define mmQM_SYNC_OBJECT_TPC1_CFG_BASE 0x7FFCE46D80ull 1894#define QM_SYNC_OBJECT_TPC1_CFG_MAX_OFFSET 0x8000 1895#define QM_SYNC_OBJECT_TPC1_CFG_SECTION 0x8000 1896#define mmQM_TPC1_CFG_BASE 0x7FFCE46D88ull 1897#define QM_TPC1_CFG_MAX_OFFSET 0xB800 1898#define QM_TPC1_CFG_SECTION 0x2780 1899#define mmTPC1_E2E_CRED_BASE 0x7FFCE47000ull 1900#define TPC1_E2E_CRED_MAX_OFFSET 0x1680 1901#define TPC1_E2E_CRED_SECTION 0x1000 1902#define mmTPC1_QM_BASE 0x7FFCE48000ull 1903#define TPC1_QM_MAX_OFFSET 0xD040 1904#define TPC1_QM_SECTION 0x3E000 1905#define mmTPC2_CFG_BASE 0x7FFCE86000ull 1906#define TPC2_CFG_MAX_OFFSET 0xE400 1907#define TPC2_CFG_SECTION 0x4000 1908#define mmKERNEL_TENSOR_0_TPC2_CFG_BASE 0x7FFCE86400ull 1909#define KERNEL_TENSOR_0_TPC2_CFG_MAX_OFFSET 0x3800 1910#define KERNEL_TENSOR_0_TPC2_CFG_SECTION 0x3800 1911#define mmKERNEL_TENSOR_1_TPC2_CFG_BASE 0x7FFCE86438ull 1912#define KERNEL_TENSOR_1_TPC2_CFG_MAX_OFFSET 0x3800 1913#define KERNEL_TENSOR_1_TPC2_CFG_SECTION 0x3800 1914#define mmKERNEL_TENSOR_2_TPC2_CFG_BASE 0x7FFCE86470ull 1915#define KERNEL_TENSOR_2_TPC2_CFG_MAX_OFFSET 0x3800 1916#define KERNEL_TENSOR_2_TPC2_CFG_SECTION 0x3800 1917#define mmKERNEL_TENSOR_3_TPC2_CFG_BASE 0x7FFCE864A8ull 1918#define KERNEL_TENSOR_3_TPC2_CFG_MAX_OFFSET 0x3800 1919#define KERNEL_TENSOR_3_TPC2_CFG_SECTION 0x3800 1920#define mmKERNEL_TENSOR_4_TPC2_CFG_BASE 0x7FFCE864E0ull 1921#define KERNEL_TENSOR_4_TPC2_CFG_MAX_OFFSET 0x3800 1922#define KERNEL_TENSOR_4_TPC2_CFG_SECTION 0x3800 1923#define mmKERNEL_TENSOR_5_TPC2_CFG_BASE 0x7FFCE86518ull 1924#define KERNEL_TENSOR_5_TPC2_CFG_MAX_OFFSET 0x3800 1925#define KERNEL_TENSOR_5_TPC2_CFG_SECTION 0x3800 1926#define mmKERNEL_TENSOR_6_TPC2_CFG_BASE 0x7FFCE86550ull 1927#define KERNEL_TENSOR_6_TPC2_CFG_MAX_OFFSET 0x3800 1928#define KERNEL_TENSOR_6_TPC2_CFG_SECTION 0x3800 1929#define mmKERNEL_TENSOR_7_TPC2_CFG_BASE 0x7FFCE86588ull 1930#define KERNEL_TENSOR_7_TPC2_CFG_MAX_OFFSET 0x3800 1931#define KERNEL_TENSOR_7_TPC2_CFG_SECTION 0x3800 1932#define mmKERNEL_TENSOR_8_TPC2_CFG_BASE 0x7FFCE865C0ull 1933#define KERNEL_TENSOR_8_TPC2_CFG_MAX_OFFSET 0x3800 1934#define KERNEL_TENSOR_8_TPC2_CFG_SECTION 0x3800 1935#define mmKERNEL_TENSOR_9_TPC2_CFG_BASE 0x7FFCE865F8ull 1936#define KERNEL_TENSOR_9_TPC2_CFG_MAX_OFFSET 0x3800 1937#define KERNEL_TENSOR_9_TPC2_CFG_SECTION 0x3800 1938#define mmKERNEL_TENSOR_10_TPC2_CFG_BASE 0x7FFCE86630ull 1939#define KERNEL_TENSOR_10_TPC2_CFG_MAX_OFFSET 0x3800 1940#define KERNEL_TENSOR_10_TPC2_CFG_SECTION 0x3800 1941#define mmKERNEL_TENSOR_11_TPC2_CFG_BASE 0x7FFCE86668ull 1942#define KERNEL_TENSOR_11_TPC2_CFG_MAX_OFFSET 0x3800 1943#define KERNEL_TENSOR_11_TPC2_CFG_SECTION 0x3800 1944#define mmKERNEL_TENSOR_12_TPC2_CFG_BASE 0x7FFCE866A0ull 1945#define KERNEL_TENSOR_12_TPC2_CFG_MAX_OFFSET 0x3800 1946#define KERNEL_TENSOR_12_TPC2_CFG_SECTION 0x3800 1947#define mmKERNEL_TENSOR_13_TPC2_CFG_BASE 0x7FFCE866D8ull 1948#define KERNEL_TENSOR_13_TPC2_CFG_MAX_OFFSET 0x3800 1949#define KERNEL_TENSOR_13_TPC2_CFG_SECTION 0x3800 1950#define mmKERNEL_TENSOR_14_TPC2_CFG_BASE 0x7FFCE86710ull 1951#define KERNEL_TENSOR_14_TPC2_CFG_MAX_OFFSET 0x3800 1952#define KERNEL_TENSOR_14_TPC2_CFG_SECTION 0x3800 1953#define mmKERNEL_TENSOR_15_TPC2_CFG_BASE 0x7FFCE86748ull 1954#define KERNEL_TENSOR_15_TPC2_CFG_MAX_OFFSET 0x3800 1955#define KERNEL_TENSOR_15_TPC2_CFG_SECTION 0x3800 1956#define mmKERNEL_SYNC_OBJECT_TPC2_CFG_BASE 0x7FFCE86780ull 1957#define KERNEL_SYNC_OBJECT_TPC2_CFG_MAX_OFFSET 0x8000 1958#define KERNEL_SYNC_OBJECT_TPC2_CFG_SECTION 0x8000 1959#define mmKERNEL_TPC2_CFG_BASE 0x7FFCE86788ull 1960#define KERNEL_TPC2_CFG_MAX_OFFSET 0xB800 1961#define KERNEL_TPC2_CFG_SECTION 0x2780 1962#define mmQM_TENSOR_0_TPC2_CFG_BASE 0x7FFCE86A00ull 1963#define QM_TENSOR_0_TPC2_CFG_MAX_OFFSET 0x3800 1964#define QM_TENSOR_0_TPC2_CFG_SECTION 0x3800 1965#define mmQM_TENSOR_1_TPC2_CFG_BASE 0x7FFCE86A38ull 1966#define QM_TENSOR_1_TPC2_CFG_MAX_OFFSET 0x3800 1967#define QM_TENSOR_1_TPC2_CFG_SECTION 0x3800 1968#define mmQM_TENSOR_2_TPC2_CFG_BASE 0x7FFCE86A70ull 1969#define QM_TENSOR_2_TPC2_CFG_MAX_OFFSET 0x3800 1970#define QM_TENSOR_2_TPC2_CFG_SECTION 0x3800 1971#define mmQM_TENSOR_3_TPC2_CFG_BASE 0x7FFCE86AA8ull 1972#define QM_TENSOR_3_TPC2_CFG_MAX_OFFSET 0x3800 1973#define QM_TENSOR_3_TPC2_CFG_SECTION 0x3800 1974#define mmQM_TENSOR_4_TPC2_CFG_BASE 0x7FFCE86AE0ull 1975#define QM_TENSOR_4_TPC2_CFG_MAX_OFFSET 0x3800 1976#define QM_TENSOR_4_TPC2_CFG_SECTION 0x3800 1977#define mmQM_TENSOR_5_TPC2_CFG_BASE 0x7FFCE86B18ull 1978#define QM_TENSOR_5_TPC2_CFG_MAX_OFFSET 0x3800 1979#define QM_TENSOR_5_TPC2_CFG_SECTION 0x3800 1980#define mmQM_TENSOR_6_TPC2_CFG_BASE 0x7FFCE86B50ull 1981#define QM_TENSOR_6_TPC2_CFG_MAX_OFFSET 0x3800 1982#define QM_TENSOR_6_TPC2_CFG_SECTION 0x3800 1983#define mmQM_TENSOR_7_TPC2_CFG_BASE 0x7FFCE86B88ull 1984#define QM_TENSOR_7_TPC2_CFG_MAX_OFFSET 0x3800 1985#define QM_TENSOR_7_TPC2_CFG_SECTION 0x3800 1986#define mmQM_TENSOR_8_TPC2_CFG_BASE 0x7FFCE86BC0ull 1987#define QM_TENSOR_8_TPC2_CFG_MAX_OFFSET 0x3800 1988#define QM_TENSOR_8_TPC2_CFG_SECTION 0x3800 1989#define mmQM_TENSOR_9_TPC2_CFG_BASE 0x7FFCE86BF8ull 1990#define QM_TENSOR_9_TPC2_CFG_MAX_OFFSET 0x3800 1991#define QM_TENSOR_9_TPC2_CFG_SECTION 0x3800 1992#define mmQM_TENSOR_10_TPC2_CFG_BASE 0x7FFCE86C30ull 1993#define QM_TENSOR_10_TPC2_CFG_MAX_OFFSET 0x3800 1994#define QM_TENSOR_10_TPC2_CFG_SECTION 0x3800 1995#define mmQM_TENSOR_11_TPC2_CFG_BASE 0x7FFCE86C68ull 1996#define QM_TENSOR_11_TPC2_CFG_MAX_OFFSET 0x3800 1997#define QM_TENSOR_11_TPC2_CFG_SECTION 0x3800 1998#define mmQM_TENSOR_12_TPC2_CFG_BASE 0x7FFCE86CA0ull 1999#define QM_TENSOR_12_TPC2_CFG_MAX_OFFSET 0x3800 2000#define QM_TENSOR_12_TPC2_CFG_SECTION 0x3800 2001#define mmQM_TENSOR_13_TPC2_CFG_BASE 0x7FFCE86CD8ull 2002#define QM_TENSOR_13_TPC2_CFG_MAX_OFFSET 0x3800 2003#define QM_TENSOR_13_TPC2_CFG_SECTION 0x3800 2004#define mmQM_TENSOR_14_TPC2_CFG_BASE 0x7FFCE86D10ull 2005#define QM_TENSOR_14_TPC2_CFG_MAX_OFFSET 0x3800 2006#define QM_TENSOR_14_TPC2_CFG_SECTION 0x3800 2007#define mmQM_TENSOR_15_TPC2_CFG_BASE 0x7FFCE86D48ull 2008#define QM_TENSOR_15_TPC2_CFG_MAX_OFFSET 0x3800 2009#define QM_TENSOR_15_TPC2_CFG_SECTION 0x3800 2010#define mmQM_SYNC_OBJECT_TPC2_CFG_BASE 0x7FFCE86D80ull 2011#define QM_SYNC_OBJECT_TPC2_CFG_MAX_OFFSET 0x8000 2012#define QM_SYNC_OBJECT_TPC2_CFG_SECTION 0x8000 2013#define mmQM_TPC2_CFG_BASE 0x7FFCE86D88ull 2014#define QM_TPC2_CFG_MAX_OFFSET 0xB800 2015#define QM_TPC2_CFG_SECTION 0x2780 2016#define mmTPC2_E2E_CRED_BASE 0x7FFCE87000ull 2017#define TPC2_E2E_CRED_MAX_OFFSET 0x1680 2018#define TPC2_E2E_CRED_SECTION 0x1000 2019#define mmTPC2_QM_BASE 0x7FFCE88000ull 2020#define TPC2_QM_MAX_OFFSET 0xD040 2021#define TPC2_QM_SECTION 0x3E000 2022#define mmTPC3_CFG_BASE 0x7FFCEC6000ull 2023#define TPC3_CFG_MAX_OFFSET 0xE400 2024#define TPC3_CFG_SECTION 0x4000 2025#define mmKERNEL_TENSOR_0_TPC3_CFG_BASE 0x7FFCEC6400ull 2026#define KERNEL_TENSOR_0_TPC3_CFG_MAX_OFFSET 0x3800 2027#define KERNEL_TENSOR_0_TPC3_CFG_SECTION 0x3800 2028#define mmKERNEL_TENSOR_1_TPC3_CFG_BASE 0x7FFCEC6438ull 2029#define KERNEL_TENSOR_1_TPC3_CFG_MAX_OFFSET 0x3800 2030#define KERNEL_TENSOR_1_TPC3_CFG_SECTION 0x3800 2031#define mmKERNEL_TENSOR_2_TPC3_CFG_BASE 0x7FFCEC6470ull 2032#define KERNEL_TENSOR_2_TPC3_CFG_MAX_OFFSET 0x3800 2033#define KERNEL_TENSOR_2_TPC3_CFG_SECTION 0x3800 2034#define mmKERNEL_TENSOR_3_TPC3_CFG_BASE 0x7FFCEC64A8ull 2035#define KERNEL_TENSOR_3_TPC3_CFG_MAX_OFFSET 0x3800 2036#define KERNEL_TENSOR_3_TPC3_CFG_SECTION 0x3800 2037#define mmKERNEL_TENSOR_4_TPC3_CFG_BASE 0x7FFCEC64E0ull 2038#define KERNEL_TENSOR_4_TPC3_CFG_MAX_OFFSET 0x3800 2039#define KERNEL_TENSOR_4_TPC3_CFG_SECTION 0x3800 2040#define mmKERNEL_TENSOR_5_TPC3_CFG_BASE 0x7FFCEC6518ull 2041#define KERNEL_TENSOR_5_TPC3_CFG_MAX_OFFSET 0x3800 2042#define KERNEL_TENSOR_5_TPC3_CFG_SECTION 0x3800 2043#define mmKERNEL_TENSOR_6_TPC3_CFG_BASE 0x7FFCEC6550ull 2044#define KERNEL_TENSOR_6_TPC3_CFG_MAX_OFFSET 0x3800 2045#define KERNEL_TENSOR_6_TPC3_CFG_SECTION 0x3800 2046#define mmKERNEL_TENSOR_7_TPC3_CFG_BASE 0x7FFCEC6588ull 2047#define KERNEL_TENSOR_7_TPC3_CFG_MAX_OFFSET 0x3800 2048#define KERNEL_TENSOR_7_TPC3_CFG_SECTION 0x3800 2049#define mmKERNEL_TENSOR_8_TPC3_CFG_BASE 0x7FFCEC65C0ull 2050#define KERNEL_TENSOR_8_TPC3_CFG_MAX_OFFSET 0x3800 2051#define KERNEL_TENSOR_8_TPC3_CFG_SECTION 0x3800 2052#define mmKERNEL_TENSOR_9_TPC3_CFG_BASE 0x7FFCEC65F8ull 2053#define KERNEL_TENSOR_9_TPC3_CFG_MAX_OFFSET 0x3800 2054#define KERNEL_TENSOR_9_TPC3_CFG_SECTION 0x3800 2055#define mmKERNEL_TENSOR_10_TPC3_CFG_BASE 0x7FFCEC6630ull 2056#define KERNEL_TENSOR_10_TPC3_CFG_MAX_OFFSET 0x3800 2057#define KERNEL_TENSOR_10_TPC3_CFG_SECTION 0x3800 2058#define mmKERNEL_TENSOR_11_TPC3_CFG_BASE 0x7FFCEC6668ull 2059#define KERNEL_TENSOR_11_TPC3_CFG_MAX_OFFSET 0x3800 2060#define KERNEL_TENSOR_11_TPC3_CFG_SECTION 0x3800 2061#define mmKERNEL_TENSOR_12_TPC3_CFG_BASE 0x7FFCEC66A0ull 2062#define KERNEL_TENSOR_12_TPC3_CFG_MAX_OFFSET 0x3800 2063#define KERNEL_TENSOR_12_TPC3_CFG_SECTION 0x3800 2064#define mmKERNEL_TENSOR_13_TPC3_CFG_BASE 0x7FFCEC66D8ull 2065#define KERNEL_TENSOR_13_TPC3_CFG_MAX_OFFSET 0x3800 2066#define KERNEL_TENSOR_13_TPC3_CFG_SECTION 0x3800 2067#define mmKERNEL_TENSOR_14_TPC3_CFG_BASE 0x7FFCEC6710ull 2068#define KERNEL_TENSOR_14_TPC3_CFG_MAX_OFFSET 0x3800 2069#define KERNEL_TENSOR_14_TPC3_CFG_SECTION 0x3800 2070#define mmKERNEL_TENSOR_15_TPC3_CFG_BASE 0x7FFCEC6748ull 2071#define KERNEL_TENSOR_15_TPC3_CFG_MAX_OFFSET 0x3800 2072#define KERNEL_TENSOR_15_TPC3_CFG_SECTION 0x3800 2073#define mmKERNEL_SYNC_OBJECT_TPC3_CFG_BASE 0x7FFCEC6780ull 2074#define KERNEL_SYNC_OBJECT_TPC3_CFG_MAX_OFFSET 0x8000 2075#define KERNEL_SYNC_OBJECT_TPC3_CFG_SECTION 0x8000 2076#define mmKERNEL_TPC3_CFG_BASE 0x7FFCEC6788ull 2077#define KERNEL_TPC3_CFG_MAX_OFFSET 0xB800 2078#define KERNEL_TPC3_CFG_SECTION 0x2780 2079#define mmQM_TENSOR_0_TPC3_CFG_BASE 0x7FFCEC6A00ull 2080#define QM_TENSOR_0_TPC3_CFG_MAX_OFFSET 0x3800 2081#define QM_TENSOR_0_TPC3_CFG_SECTION 0x3800 2082#define mmQM_TENSOR_1_TPC3_CFG_BASE 0x7FFCEC6A38ull 2083#define QM_TENSOR_1_TPC3_CFG_MAX_OFFSET 0x3800 2084#define QM_TENSOR_1_TPC3_CFG_SECTION 0x3800 2085#define mmQM_TENSOR_2_TPC3_CFG_BASE 0x7FFCEC6A70ull 2086#define QM_TENSOR_2_TPC3_CFG_MAX_OFFSET 0x3800 2087#define QM_TENSOR_2_TPC3_CFG_SECTION 0x3800 2088#define mmQM_TENSOR_3_TPC3_CFG_BASE 0x7FFCEC6AA8ull 2089#define QM_TENSOR_3_TPC3_CFG_MAX_OFFSET 0x3800 2090#define QM_TENSOR_3_TPC3_CFG_SECTION 0x3800 2091#define mmQM_TENSOR_4_TPC3_CFG_BASE 0x7FFCEC6AE0ull 2092#define QM_TENSOR_4_TPC3_CFG_MAX_OFFSET 0x3800 2093#define QM_TENSOR_4_TPC3_CFG_SECTION 0x3800 2094#define mmQM_TENSOR_5_TPC3_CFG_BASE 0x7FFCEC6B18ull 2095#define QM_TENSOR_5_TPC3_CFG_MAX_OFFSET 0x3800 2096#define QM_TENSOR_5_TPC3_CFG_SECTION 0x3800 2097#define mmQM_TENSOR_6_TPC3_CFG_BASE 0x7FFCEC6B50ull 2098#define QM_TENSOR_6_TPC3_CFG_MAX_OFFSET 0x3800 2099#define QM_TENSOR_6_TPC3_CFG_SECTION 0x3800 2100#define mmQM_TENSOR_7_TPC3_CFG_BASE 0x7FFCEC6B88ull 2101#define QM_TENSOR_7_TPC3_CFG_MAX_OFFSET 0x3800 2102#define QM_TENSOR_7_TPC3_CFG_SECTION 0x3800 2103#define mmQM_TENSOR_8_TPC3_CFG_BASE 0x7FFCEC6BC0ull 2104#define QM_TENSOR_8_TPC3_CFG_MAX_OFFSET 0x3800 2105#define QM_TENSOR_8_TPC3_CFG_SECTION 0x3800 2106#define mmQM_TENSOR_9_TPC3_CFG_BASE 0x7FFCEC6BF8ull 2107#define QM_TENSOR_9_TPC3_CFG_MAX_OFFSET 0x3800 2108#define QM_TENSOR_9_TPC3_CFG_SECTION 0x3800 2109#define mmQM_TENSOR_10_TPC3_CFG_BASE 0x7FFCEC6C30ull 2110#define QM_TENSOR_10_TPC3_CFG_MAX_OFFSET 0x3800 2111#define QM_TENSOR_10_TPC3_CFG_SECTION 0x3800 2112#define mmQM_TENSOR_11_TPC3_CFG_BASE 0x7FFCEC6C68ull 2113#define QM_TENSOR_11_TPC3_CFG_MAX_OFFSET 0x3800 2114#define QM_TENSOR_11_TPC3_CFG_SECTION 0x3800 2115#define mmQM_TENSOR_12_TPC3_CFG_BASE 0x7FFCEC6CA0ull 2116#define QM_TENSOR_12_TPC3_CFG_MAX_OFFSET 0x3800 2117#define QM_TENSOR_12_TPC3_CFG_SECTION 0x3800 2118#define mmQM_TENSOR_13_TPC3_CFG_BASE 0x7FFCEC6CD8ull 2119#define QM_TENSOR_13_TPC3_CFG_MAX_OFFSET 0x3800 2120#define QM_TENSOR_13_TPC3_CFG_SECTION 0x3800 2121#define mmQM_TENSOR_14_TPC3_CFG_BASE 0x7FFCEC6D10ull 2122#define QM_TENSOR_14_TPC3_CFG_MAX_OFFSET 0x3800 2123#define QM_TENSOR_14_TPC3_CFG_SECTION 0x3800 2124#define mmQM_TENSOR_15_TPC3_CFG_BASE 0x7FFCEC6D48ull 2125#define QM_TENSOR_15_TPC3_CFG_MAX_OFFSET 0x3800 2126#define QM_TENSOR_15_TPC3_CFG_SECTION 0x3800 2127#define mmQM_SYNC_OBJECT_TPC3_CFG_BASE 0x7FFCEC6D80ull 2128#define QM_SYNC_OBJECT_TPC3_CFG_MAX_OFFSET 0x8000 2129#define QM_SYNC_OBJECT_TPC3_CFG_SECTION 0x8000 2130#define mmQM_TPC3_CFG_BASE 0x7FFCEC6D88ull 2131#define QM_TPC3_CFG_MAX_OFFSET 0xB800 2132#define QM_TPC3_CFG_SECTION 0x2780 2133#define mmTPC3_E2E_CRED_BASE 0x7FFCEC7000ull 2134#define TPC3_E2E_CRED_MAX_OFFSET 0x1680 2135#define TPC3_E2E_CRED_SECTION 0x1000 2136#define mmTPC3_QM_BASE 0x7FFCEC8000ull 2137#define TPC3_QM_MAX_OFFSET 0xD040 2138#define TPC3_QM_SECTION 0x3E000 2139#define mmTPC4_CFG_BASE 0x7FFCF06000ull 2140#define TPC4_CFG_MAX_OFFSET 0xE400 2141#define TPC4_CFG_SECTION 0x4000 2142#define mmKERNEL_TENSOR_0_TPC4_CFG_BASE 0x7FFCF06400ull 2143#define KERNEL_TENSOR_0_TPC4_CFG_MAX_OFFSET 0x3800 2144#define KERNEL_TENSOR_0_TPC4_CFG_SECTION 0x3800 2145#define mmKERNEL_TENSOR_1_TPC4_CFG_BASE 0x7FFCF06438ull 2146#define KERNEL_TENSOR_1_TPC4_CFG_MAX_OFFSET 0x3800 2147#define KERNEL_TENSOR_1_TPC4_CFG_SECTION 0x3800 2148#define mmKERNEL_TENSOR_2_TPC4_CFG_BASE 0x7FFCF06470ull 2149#define KERNEL_TENSOR_2_TPC4_CFG_MAX_OFFSET 0x3800 2150#define KERNEL_TENSOR_2_TPC4_CFG_SECTION 0x3800 2151#define mmKERNEL_TENSOR_3_TPC4_CFG_BASE 0x7FFCF064A8ull 2152#define KERNEL_TENSOR_3_TPC4_CFG_MAX_OFFSET 0x3800 2153#define KERNEL_TENSOR_3_TPC4_CFG_SECTION 0x3800 2154#define mmKERNEL_TENSOR_4_TPC4_CFG_BASE 0x7FFCF064E0ull 2155#define KERNEL_TENSOR_4_TPC4_CFG_MAX_OFFSET 0x3800 2156#define KERNEL_TENSOR_4_TPC4_CFG_SECTION 0x3800 2157#define mmKERNEL_TENSOR_5_TPC4_CFG_BASE 0x7FFCF06518ull 2158#define KERNEL_TENSOR_5_TPC4_CFG_MAX_OFFSET 0x3800 2159#define KERNEL_TENSOR_5_TPC4_CFG_SECTION 0x3800 2160#define mmKERNEL_TENSOR_6_TPC4_CFG_BASE 0x7FFCF06550ull 2161#define KERNEL_TENSOR_6_TPC4_CFG_MAX_OFFSET 0x3800 2162#define KERNEL_TENSOR_6_TPC4_CFG_SECTION 0x3800 2163#define mmKERNEL_TENSOR_7_TPC4_CFG_BASE 0x7FFCF06588ull 2164#define KERNEL_TENSOR_7_TPC4_CFG_MAX_OFFSET 0x3800 2165#define KERNEL_TENSOR_7_TPC4_CFG_SECTION 0x3800 2166#define mmKERNEL_TENSOR_8_TPC4_CFG_BASE 0x7FFCF065C0ull 2167#define KERNEL_TENSOR_8_TPC4_CFG_MAX_OFFSET 0x3800 2168#define KERNEL_TENSOR_8_TPC4_CFG_SECTION 0x3800 2169#define mmKERNEL_TENSOR_9_TPC4_CFG_BASE 0x7FFCF065F8ull 2170#define KERNEL_TENSOR_9_TPC4_CFG_MAX_OFFSET 0x3800 2171#define KERNEL_TENSOR_9_TPC4_CFG_SECTION 0x3800 2172#define mmKERNEL_TENSOR_10_TPC4_CFG_BASE 0x7FFCF06630ull 2173#define KERNEL_TENSOR_10_TPC4_CFG_MAX_OFFSET 0x3800 2174#define KERNEL_TENSOR_10_TPC4_CFG_SECTION 0x3800 2175#define mmKERNEL_TENSOR_11_TPC4_CFG_BASE 0x7FFCF06668ull 2176#define KERNEL_TENSOR_11_TPC4_CFG_MAX_OFFSET 0x3800 2177#define KERNEL_TENSOR_11_TPC4_CFG_SECTION 0x3800 2178#define mmKERNEL_TENSOR_12_TPC4_CFG_BASE 0x7FFCF066A0ull 2179#define KERNEL_TENSOR_12_TPC4_CFG_MAX_OFFSET 0x3800 2180#define KERNEL_TENSOR_12_TPC4_CFG_SECTION 0x3800 2181#define mmKERNEL_TENSOR_13_TPC4_CFG_BASE 0x7FFCF066D8ull 2182#define KERNEL_TENSOR_13_TPC4_CFG_MAX_OFFSET 0x3800 2183#define KERNEL_TENSOR_13_TPC4_CFG_SECTION 0x3800 2184#define mmKERNEL_TENSOR_14_TPC4_CFG_BASE 0x7FFCF06710ull 2185#define KERNEL_TENSOR_14_TPC4_CFG_MAX_OFFSET 0x3800 2186#define KERNEL_TENSOR_14_TPC4_CFG_SECTION 0x3800 2187#define mmKERNEL_TENSOR_15_TPC4_CFG_BASE 0x7FFCF06748ull 2188#define KERNEL_TENSOR_15_TPC4_CFG_MAX_OFFSET 0x3800 2189#define KERNEL_TENSOR_15_TPC4_CFG_SECTION 0x3800 2190#define mmKERNEL_SYNC_OBJECT_TPC4_CFG_BASE 0x7FFCF06780ull 2191#define KERNEL_SYNC_OBJECT_TPC4_CFG_MAX_OFFSET 0x8000 2192#define KERNEL_SYNC_OBJECT_TPC4_CFG_SECTION 0x8000 2193#define mmKERNEL_TPC4_CFG_BASE 0x7FFCF06788ull 2194#define KERNEL_TPC4_CFG_MAX_OFFSET 0xB800 2195#define KERNEL_TPC4_CFG_SECTION 0x2780 2196#define mmQM_TENSOR_0_TPC4_CFG_BASE 0x7FFCF06A00ull 2197#define QM_TENSOR_0_TPC4_CFG_MAX_OFFSET 0x3800 2198#define QM_TENSOR_0_TPC4_CFG_SECTION 0x3800 2199#define mmQM_TENSOR_1_TPC4_CFG_BASE 0x7FFCF06A38ull 2200#define QM_TENSOR_1_TPC4_CFG_MAX_OFFSET 0x3800 2201#define QM_TENSOR_1_TPC4_CFG_SECTION 0x3800 2202#define mmQM_TENSOR_2_TPC4_CFG_BASE 0x7FFCF06A70ull 2203#define QM_TENSOR_2_TPC4_CFG_MAX_OFFSET 0x3800 2204#define QM_TENSOR_2_TPC4_CFG_SECTION 0x3800 2205#define mmQM_TENSOR_3_TPC4_CFG_BASE 0x7FFCF06AA8ull 2206#define QM_TENSOR_3_TPC4_CFG_MAX_OFFSET 0x3800 2207#define QM_TENSOR_3_TPC4_CFG_SECTION 0x3800 2208#define mmQM_TENSOR_4_TPC4_CFG_BASE 0x7FFCF06AE0ull 2209#define QM_TENSOR_4_TPC4_CFG_MAX_OFFSET 0x3800 2210#define QM_TENSOR_4_TPC4_CFG_SECTION 0x3800 2211#define mmQM_TENSOR_5_TPC4_CFG_BASE 0x7FFCF06B18ull 2212#define QM_TENSOR_5_TPC4_CFG_MAX_OFFSET 0x3800 2213#define QM_TENSOR_5_TPC4_CFG_SECTION 0x3800 2214#define mmQM_TENSOR_6_TPC4_CFG_BASE 0x7FFCF06B50ull 2215#define QM_TENSOR_6_TPC4_CFG_MAX_OFFSET 0x3800 2216#define QM_TENSOR_6_TPC4_CFG_SECTION 0x3800 2217#define mmQM_TENSOR_7_TPC4_CFG_BASE 0x7FFCF06B88ull 2218#define QM_TENSOR_7_TPC4_CFG_MAX_OFFSET 0x3800 2219#define QM_TENSOR_7_TPC4_CFG_SECTION 0x3800 2220#define mmQM_TENSOR_8_TPC4_CFG_BASE 0x7FFCF06BC0ull 2221#define QM_TENSOR_8_TPC4_CFG_MAX_OFFSET 0x3800 2222#define QM_TENSOR_8_TPC4_CFG_SECTION 0x3800 2223#define mmQM_TENSOR_9_TPC4_CFG_BASE 0x7FFCF06BF8ull 2224#define QM_TENSOR_9_TPC4_CFG_MAX_OFFSET 0x3800 2225#define QM_TENSOR_9_TPC4_CFG_SECTION 0x3800 2226#define mmQM_TENSOR_10_TPC4_CFG_BASE 0x7FFCF06C30ull 2227#define QM_TENSOR_10_TPC4_CFG_MAX_OFFSET 0x3800 2228#define QM_TENSOR_10_TPC4_CFG_SECTION 0x3800 2229#define mmQM_TENSOR_11_TPC4_CFG_BASE 0x7FFCF06C68ull 2230#define QM_TENSOR_11_TPC4_CFG_MAX_OFFSET 0x3800 2231#define QM_TENSOR_11_TPC4_CFG_SECTION 0x3800 2232#define mmQM_TENSOR_12_TPC4_CFG_BASE 0x7FFCF06CA0ull 2233#define QM_TENSOR_12_TPC4_CFG_MAX_OFFSET 0x3800 2234#define QM_TENSOR_12_TPC4_CFG_SECTION 0x3800 2235#define mmQM_TENSOR_13_TPC4_CFG_BASE 0x7FFCF06CD8ull 2236#define QM_TENSOR_13_TPC4_CFG_MAX_OFFSET 0x3800 2237#define QM_TENSOR_13_TPC4_CFG_SECTION 0x3800 2238#define mmQM_TENSOR_14_TPC4_CFG_BASE 0x7FFCF06D10ull 2239#define QM_TENSOR_14_TPC4_CFG_MAX_OFFSET 0x3800 2240#define QM_TENSOR_14_TPC4_CFG_SECTION 0x3800 2241#define mmQM_TENSOR_15_TPC4_CFG_BASE 0x7FFCF06D48ull 2242#define QM_TENSOR_15_TPC4_CFG_MAX_OFFSET 0x3800 2243#define QM_TENSOR_15_TPC4_CFG_SECTION 0x3800 2244#define mmQM_SYNC_OBJECT_TPC4_CFG_BASE 0x7FFCF06D80ull 2245#define QM_SYNC_OBJECT_TPC4_CFG_MAX_OFFSET 0x8000 2246#define QM_SYNC_OBJECT_TPC4_CFG_SECTION 0x8000 2247#define mmQM_TPC4_CFG_BASE 0x7FFCF06D88ull 2248#define QM_TPC4_CFG_MAX_OFFSET 0xB800 2249#define QM_TPC4_CFG_SECTION 0x2780 2250#define mmTPC4_E2E_CRED_BASE 0x7FFCF07000ull 2251#define TPC4_E2E_CRED_MAX_OFFSET 0x1680 2252#define TPC4_E2E_CRED_SECTION 0x1000 2253#define mmTPC4_QM_BASE 0x7FFCF08000ull 2254#define TPC4_QM_MAX_OFFSET 0xD040 2255#define TPC4_QM_SECTION 0x3E000 2256#define mmTPC5_CFG_BASE 0x7FFCF46000ull 2257#define TPC5_CFG_MAX_OFFSET 0xE400 2258#define TPC5_CFG_SECTION 0x4000 2259#define mmKERNEL_TENSOR_0_TPC5_CFG_BASE 0x7FFCF46400ull 2260#define KERNEL_TENSOR_0_TPC5_CFG_MAX_OFFSET 0x3800 2261#define KERNEL_TENSOR_0_TPC5_CFG_SECTION 0x3800 2262#define mmKERNEL_TENSOR_1_TPC5_CFG_BASE 0x7FFCF46438ull 2263#define KERNEL_TENSOR_1_TPC5_CFG_MAX_OFFSET 0x3800 2264#define KERNEL_TENSOR_1_TPC5_CFG_SECTION 0x3800 2265#define mmKERNEL_TENSOR_2_TPC5_CFG_BASE 0x7FFCF46470ull 2266#define KERNEL_TENSOR_2_TPC5_CFG_MAX_OFFSET 0x3800 2267#define KERNEL_TENSOR_2_TPC5_CFG_SECTION 0x3800 2268#define mmKERNEL_TENSOR_3_TPC5_CFG_BASE 0x7FFCF464A8ull 2269#define KERNEL_TENSOR_3_TPC5_CFG_MAX_OFFSET 0x3800 2270#define KERNEL_TENSOR_3_TPC5_CFG_SECTION 0x3800 2271#define mmKERNEL_TENSOR_4_TPC5_CFG_BASE 0x7FFCF464E0ull 2272#define KERNEL_TENSOR_4_TPC5_CFG_MAX_OFFSET 0x3800 2273#define KERNEL_TENSOR_4_TPC5_CFG_SECTION 0x3800 2274#define mmKERNEL_TENSOR_5_TPC5_CFG_BASE 0x7FFCF46518ull 2275#define KERNEL_TENSOR_5_TPC5_CFG_MAX_OFFSET 0x3800 2276#define KERNEL_TENSOR_5_TPC5_CFG_SECTION 0x3800 2277#define mmKERNEL_TENSOR_6_TPC5_CFG_BASE 0x7FFCF46550ull 2278#define KERNEL_TENSOR_6_TPC5_CFG_MAX_OFFSET 0x3800 2279#define KERNEL_TENSOR_6_TPC5_CFG_SECTION 0x3800 2280#define mmKERNEL_TENSOR_7_TPC5_CFG_BASE 0x7FFCF46588ull 2281#define KERNEL_TENSOR_7_TPC5_CFG_MAX_OFFSET 0x3800 2282#define KERNEL_TENSOR_7_TPC5_CFG_SECTION 0x3800 2283#define mmKERNEL_TENSOR_8_TPC5_CFG_BASE 0x7FFCF465C0ull 2284#define KERNEL_TENSOR_8_TPC5_CFG_MAX_OFFSET 0x3800 2285#define KERNEL_TENSOR_8_TPC5_CFG_SECTION 0x3800 2286#define mmKERNEL_TENSOR_9_TPC5_CFG_BASE 0x7FFCF465F8ull 2287#define KERNEL_TENSOR_9_TPC5_CFG_MAX_OFFSET 0x3800 2288#define KERNEL_TENSOR_9_TPC5_CFG_SECTION 0x3800 2289#define mmKERNEL_TENSOR_10_TPC5_CFG_BASE 0x7FFCF46630ull 2290#define KERNEL_TENSOR_10_TPC5_CFG_MAX_OFFSET 0x3800 2291#define KERNEL_TENSOR_10_TPC5_CFG_SECTION 0x3800 2292#define mmKERNEL_TENSOR_11_TPC5_CFG_BASE 0x7FFCF46668ull 2293#define KERNEL_TENSOR_11_TPC5_CFG_MAX_OFFSET 0x3800 2294#define KERNEL_TENSOR_11_TPC5_CFG_SECTION 0x3800 2295#define mmKERNEL_TENSOR_12_TPC5_CFG_BASE 0x7FFCF466A0ull 2296#define KERNEL_TENSOR_12_TPC5_CFG_MAX_OFFSET 0x3800 2297#define KERNEL_TENSOR_12_TPC5_CFG_SECTION 0x3800 2298#define mmKERNEL_TENSOR_13_TPC5_CFG_BASE 0x7FFCF466D8ull 2299#define KERNEL_TENSOR_13_TPC5_CFG_MAX_OFFSET 0x3800 2300#define KERNEL_TENSOR_13_TPC5_CFG_SECTION 0x3800 2301#define mmKERNEL_TENSOR_14_TPC5_CFG_BASE 0x7FFCF46710ull 2302#define KERNEL_TENSOR_14_TPC5_CFG_MAX_OFFSET 0x3800 2303#define KERNEL_TENSOR_14_TPC5_CFG_SECTION 0x3800 2304#define mmKERNEL_TENSOR_15_TPC5_CFG_BASE 0x7FFCF46748ull 2305#define KERNEL_TENSOR_15_TPC5_CFG_MAX_OFFSET 0x3800 2306#define KERNEL_TENSOR_15_TPC5_CFG_SECTION 0x3800 2307#define mmKERNEL_SYNC_OBJECT_TPC5_CFG_BASE 0x7FFCF46780ull 2308#define KERNEL_SYNC_OBJECT_TPC5_CFG_MAX_OFFSET 0x8000 2309#define KERNEL_SYNC_OBJECT_TPC5_CFG_SECTION 0x8000 2310#define mmKERNEL_TPC5_CFG_BASE 0x7FFCF46788ull 2311#define KERNEL_TPC5_CFG_MAX_OFFSET 0xB800 2312#define KERNEL_TPC5_CFG_SECTION 0x2780 2313#define mmQM_TENSOR_0_TPC5_CFG_BASE 0x7FFCF46A00ull 2314#define QM_TENSOR_0_TPC5_CFG_MAX_OFFSET 0x3800 2315#define QM_TENSOR_0_TPC5_CFG_SECTION 0x3800 2316#define mmQM_TENSOR_1_TPC5_CFG_BASE 0x7FFCF46A38ull 2317#define QM_TENSOR_1_TPC5_CFG_MAX_OFFSET 0x3800 2318#define QM_TENSOR_1_TPC5_CFG_SECTION 0x3800 2319#define mmQM_TENSOR_2_TPC5_CFG_BASE 0x7FFCF46A70ull 2320#define QM_TENSOR_2_TPC5_CFG_MAX_OFFSET 0x3800 2321#define QM_TENSOR_2_TPC5_CFG_SECTION 0x3800 2322#define mmQM_TENSOR_3_TPC5_CFG_BASE 0x7FFCF46AA8ull 2323#define QM_TENSOR_3_TPC5_CFG_MAX_OFFSET 0x3800 2324#define QM_TENSOR_3_TPC5_CFG_SECTION 0x3800 2325#define mmQM_TENSOR_4_TPC5_CFG_BASE 0x7FFCF46AE0ull 2326#define QM_TENSOR_4_TPC5_CFG_MAX_OFFSET 0x3800 2327#define QM_TENSOR_4_TPC5_CFG_SECTION 0x3800 2328#define mmQM_TENSOR_5_TPC5_CFG_BASE 0x7FFCF46B18ull 2329#define QM_TENSOR_5_TPC5_CFG_MAX_OFFSET 0x3800 2330#define QM_TENSOR_5_TPC5_CFG_SECTION 0x3800 2331#define mmQM_TENSOR_6_TPC5_CFG_BASE 0x7FFCF46B50ull 2332#define QM_TENSOR_6_TPC5_CFG_MAX_OFFSET 0x3800 2333#define QM_TENSOR_6_TPC5_CFG_SECTION 0x3800 2334#define mmQM_TENSOR_7_TPC5_CFG_BASE 0x7FFCF46B88ull 2335#define QM_TENSOR_7_TPC5_CFG_MAX_OFFSET 0x3800 2336#define QM_TENSOR_7_TPC5_CFG_SECTION 0x3800 2337#define mmQM_TENSOR_8_TPC5_CFG_BASE 0x7FFCF46BC0ull 2338#define QM_TENSOR_8_TPC5_CFG_MAX_OFFSET 0x3800 2339#define QM_TENSOR_8_TPC5_CFG_SECTION 0x3800 2340#define mmQM_TENSOR_9_TPC5_CFG_BASE 0x7FFCF46BF8ull 2341#define QM_TENSOR_9_TPC5_CFG_MAX_OFFSET 0x3800 2342#define QM_TENSOR_9_TPC5_CFG_SECTION 0x3800 2343#define mmQM_TENSOR_10_TPC5_CFG_BASE 0x7FFCF46C30ull 2344#define QM_TENSOR_10_TPC5_CFG_MAX_OFFSET 0x3800 2345#define QM_TENSOR_10_TPC5_CFG_SECTION 0x3800 2346#define mmQM_TENSOR_11_TPC5_CFG_BASE 0x7FFCF46C68ull 2347#define QM_TENSOR_11_TPC5_CFG_MAX_OFFSET 0x3800 2348#define QM_TENSOR_11_TPC5_CFG_SECTION 0x3800 2349#define mmQM_TENSOR_12_TPC5_CFG_BASE 0x7FFCF46CA0ull 2350#define QM_TENSOR_12_TPC5_CFG_MAX_OFFSET 0x3800 2351#define QM_TENSOR_12_TPC5_CFG_SECTION 0x3800 2352#define mmQM_TENSOR_13_TPC5_CFG_BASE 0x7FFCF46CD8ull 2353#define QM_TENSOR_13_TPC5_CFG_MAX_OFFSET 0x3800 2354#define QM_TENSOR_13_TPC5_CFG_SECTION 0x3800 2355#define mmQM_TENSOR_14_TPC5_CFG_BASE 0x7FFCF46D10ull 2356#define QM_TENSOR_14_TPC5_CFG_MAX_OFFSET 0x3800 2357#define QM_TENSOR_14_TPC5_CFG_SECTION 0x3800 2358#define mmQM_TENSOR_15_TPC5_CFG_BASE 0x7FFCF46D48ull 2359#define QM_TENSOR_15_TPC5_CFG_MAX_OFFSET 0x3800 2360#define QM_TENSOR_15_TPC5_CFG_SECTION 0x3800 2361#define mmQM_SYNC_OBJECT_TPC5_CFG_BASE 0x7FFCF46D80ull 2362#define QM_SYNC_OBJECT_TPC5_CFG_MAX_OFFSET 0x8000 2363#define QM_SYNC_OBJECT_TPC5_CFG_SECTION 0x8000 2364#define mmQM_TPC5_CFG_BASE 0x7FFCF46D88ull 2365#define QM_TPC5_CFG_MAX_OFFSET 0xB800 2366#define QM_TPC5_CFG_SECTION 0x2780 2367#define mmTPC5_E2E_CRED_BASE 0x7FFCF47000ull 2368#define TPC5_E2E_CRED_MAX_OFFSET 0x1680 2369#define TPC5_E2E_CRED_SECTION 0x1000 2370#define mmTPC5_QM_BASE 0x7FFCF48000ull 2371#define TPC5_QM_MAX_OFFSET 0xD040 2372#define TPC5_QM_SECTION 0x3E000 2373#define mmTPC6_CFG_BASE 0x7FFCF86000ull 2374#define TPC6_CFG_MAX_OFFSET 0xE400 2375#define TPC6_CFG_SECTION 0x4000 2376#define mmKERNEL_TENSOR_0_TPC6_CFG_BASE 0x7FFCF86400ull 2377#define KERNEL_TENSOR_0_TPC6_CFG_MAX_OFFSET 0x3800 2378#define KERNEL_TENSOR_0_TPC6_CFG_SECTION 0x3800 2379#define mmKERNEL_TENSOR_1_TPC6_CFG_BASE 0x7FFCF86438ull 2380#define KERNEL_TENSOR_1_TPC6_CFG_MAX_OFFSET 0x3800 2381#define KERNEL_TENSOR_1_TPC6_CFG_SECTION 0x3800 2382#define mmKERNEL_TENSOR_2_TPC6_CFG_BASE 0x7FFCF86470ull 2383#define KERNEL_TENSOR_2_TPC6_CFG_MAX_OFFSET 0x3800 2384#define KERNEL_TENSOR_2_TPC6_CFG_SECTION 0x3800 2385#define mmKERNEL_TENSOR_3_TPC6_CFG_BASE 0x7FFCF864A8ull 2386#define KERNEL_TENSOR_3_TPC6_CFG_MAX_OFFSET 0x3800 2387#define KERNEL_TENSOR_3_TPC6_CFG_SECTION 0x3800 2388#define mmKERNEL_TENSOR_4_TPC6_CFG_BASE 0x7FFCF864E0ull 2389#define KERNEL_TENSOR_4_TPC6_CFG_MAX_OFFSET 0x3800 2390#define KERNEL_TENSOR_4_TPC6_CFG_SECTION 0x3800 2391#define mmKERNEL_TENSOR_5_TPC6_CFG_BASE 0x7FFCF86518ull 2392#define KERNEL_TENSOR_5_TPC6_CFG_MAX_OFFSET 0x3800 2393#define KERNEL_TENSOR_5_TPC6_CFG_SECTION 0x3800 2394#define mmKERNEL_TENSOR_6_TPC6_CFG_BASE 0x7FFCF86550ull 2395#define KERNEL_TENSOR_6_TPC6_CFG_MAX_OFFSET 0x3800 2396#define KERNEL_TENSOR_6_TPC6_CFG_SECTION 0x3800 2397#define mmKERNEL_TENSOR_7_TPC6_CFG_BASE 0x7FFCF86588ull 2398#define KERNEL_TENSOR_7_TPC6_CFG_MAX_OFFSET 0x3800 2399#define KERNEL_TENSOR_7_TPC6_CFG_SECTION 0x3800 2400#define mmKERNEL_TENSOR_8_TPC6_CFG_BASE 0x7FFCF865C0ull 2401#define KERNEL_TENSOR_8_TPC6_CFG_MAX_OFFSET 0x3800 2402#define KERNEL_TENSOR_8_TPC6_CFG_SECTION 0x3800 2403#define mmKERNEL_TENSOR_9_TPC6_CFG_BASE 0x7FFCF865F8ull 2404#define KERNEL_TENSOR_9_TPC6_CFG_MAX_OFFSET 0x3800 2405#define KERNEL_TENSOR_9_TPC6_CFG_SECTION 0x3800 2406#define mmKERNEL_TENSOR_10_TPC6_CFG_BASE 0x7FFCF86630ull 2407#define KERNEL_TENSOR_10_TPC6_CFG_MAX_OFFSET 0x3800 2408#define KERNEL_TENSOR_10_TPC6_CFG_SECTION 0x3800 2409#define mmKERNEL_TENSOR_11_TPC6_CFG_BASE 0x7FFCF86668ull 2410#define KERNEL_TENSOR_11_TPC6_CFG_MAX_OFFSET 0x3800 2411#define KERNEL_TENSOR_11_TPC6_CFG_SECTION 0x3800 2412#define mmKERNEL_TENSOR_12_TPC6_CFG_BASE 0x7FFCF866A0ull 2413#define KERNEL_TENSOR_12_TPC6_CFG_MAX_OFFSET 0x3800 2414#define KERNEL_TENSOR_12_TPC6_CFG_SECTION 0x3800 2415#define mmKERNEL_TENSOR_13_TPC6_CFG_BASE 0x7FFCF866D8ull 2416#define KERNEL_TENSOR_13_TPC6_CFG_MAX_OFFSET 0x3800 2417#define KERNEL_TENSOR_13_TPC6_CFG_SECTION 0x3800 2418#define mmKERNEL_TENSOR_14_TPC6_CFG_BASE 0x7FFCF86710ull 2419#define KERNEL_TENSOR_14_TPC6_CFG_MAX_OFFSET 0x3800 2420#define KERNEL_TENSOR_14_TPC6_CFG_SECTION 0x3800 2421#define mmKERNEL_TENSOR_15_TPC6_CFG_BASE 0x7FFCF86748ull 2422#define KERNEL_TENSOR_15_TPC6_CFG_MAX_OFFSET 0x3800 2423#define KERNEL_TENSOR_15_TPC6_CFG_SECTION 0x3800 2424#define mmKERNEL_SYNC_OBJECT_TPC6_CFG_BASE 0x7FFCF86780ull 2425#define KERNEL_SYNC_OBJECT_TPC6_CFG_MAX_OFFSET 0x8000 2426#define KERNEL_SYNC_OBJECT_TPC6_CFG_SECTION 0x8000 2427#define mmKERNEL_TPC6_CFG_BASE 0x7FFCF86788ull 2428#define KERNEL_TPC6_CFG_MAX_OFFSET 0xB800 2429#define KERNEL_TPC6_CFG_SECTION 0x2780 2430#define mmQM_TENSOR_0_TPC6_CFG_BASE 0x7FFCF86A00ull 2431#define QM_TENSOR_0_TPC6_CFG_MAX_OFFSET 0x3800 2432#define QM_TENSOR_0_TPC6_CFG_SECTION 0x3800 2433#define mmQM_TENSOR_1_TPC6_CFG_BASE 0x7FFCF86A38ull 2434#define QM_TENSOR_1_TPC6_CFG_MAX_OFFSET 0x3800 2435#define QM_TENSOR_1_TPC6_CFG_SECTION 0x3800 2436#define mmQM_TENSOR_2_TPC6_CFG_BASE 0x7FFCF86A70ull 2437#define QM_TENSOR_2_TPC6_CFG_MAX_OFFSET 0x3800 2438#define QM_TENSOR_2_TPC6_CFG_SECTION 0x3800 2439#define mmQM_TENSOR_3_TPC6_CFG_BASE 0x7FFCF86AA8ull 2440#define QM_TENSOR_3_TPC6_CFG_MAX_OFFSET 0x3800 2441#define QM_TENSOR_3_TPC6_CFG_SECTION 0x3800 2442#define mmQM_TENSOR_4_TPC6_CFG_BASE 0x7FFCF86AE0ull 2443#define QM_TENSOR_4_TPC6_CFG_MAX_OFFSET 0x3800 2444#define QM_TENSOR_4_TPC6_CFG_SECTION 0x3800 2445#define mmQM_TENSOR_5_TPC6_CFG_BASE 0x7FFCF86B18ull 2446#define QM_TENSOR_5_TPC6_CFG_MAX_OFFSET 0x3800 2447#define QM_TENSOR_5_TPC6_CFG_SECTION 0x3800 2448#define mmQM_TENSOR_6_TPC6_CFG_BASE 0x7FFCF86B50ull 2449#define QM_TENSOR_6_TPC6_CFG_MAX_OFFSET 0x3800 2450#define QM_TENSOR_6_TPC6_CFG_SECTION 0x3800 2451#define mmQM_TENSOR_7_TPC6_CFG_BASE 0x7FFCF86B88ull 2452#define QM_TENSOR_7_TPC6_CFG_MAX_OFFSET 0x3800 2453#define QM_TENSOR_7_TPC6_CFG_SECTION 0x3800 2454#define mmQM_TENSOR_8_TPC6_CFG_BASE 0x7FFCF86BC0ull 2455#define QM_TENSOR_8_TPC6_CFG_MAX_OFFSET 0x3800 2456#define QM_TENSOR_8_TPC6_CFG_SECTION 0x3800 2457#define mmQM_TENSOR_9_TPC6_CFG_BASE 0x7FFCF86BF8ull 2458#define QM_TENSOR_9_TPC6_CFG_MAX_OFFSET 0x3800 2459#define QM_TENSOR_9_TPC6_CFG_SECTION 0x3800 2460#define mmQM_TENSOR_10_TPC6_CFG_BASE 0x7FFCF86C30ull 2461#define QM_TENSOR_10_TPC6_CFG_MAX_OFFSET 0x3800 2462#define QM_TENSOR_10_TPC6_CFG_SECTION 0x3800 2463#define mmQM_TENSOR_11_TPC6_CFG_BASE 0x7FFCF86C68ull 2464#define QM_TENSOR_11_TPC6_CFG_MAX_OFFSET 0x3800 2465#define QM_TENSOR_11_TPC6_CFG_SECTION 0x3800 2466#define mmQM_TENSOR_12_TPC6_CFG_BASE 0x7FFCF86CA0ull 2467#define QM_TENSOR_12_TPC6_CFG_MAX_OFFSET 0x3800 2468#define QM_TENSOR_12_TPC6_CFG_SECTION 0x3800 2469#define mmQM_TENSOR_13_TPC6_CFG_BASE 0x7FFCF86CD8ull 2470#define QM_TENSOR_13_TPC6_CFG_MAX_OFFSET 0x3800 2471#define QM_TENSOR_13_TPC6_CFG_SECTION 0x3800 2472#define mmQM_TENSOR_14_TPC6_CFG_BASE 0x7FFCF86D10ull 2473#define QM_TENSOR_14_TPC6_CFG_MAX_OFFSET 0x3800 2474#define QM_TENSOR_14_TPC6_CFG_SECTION 0x3800 2475#define mmQM_TENSOR_15_TPC6_CFG_BASE 0x7FFCF86D48ull 2476#define QM_TENSOR_15_TPC6_CFG_MAX_OFFSET 0x3800 2477#define QM_TENSOR_15_TPC6_CFG_SECTION 0x3800 2478#define mmQM_SYNC_OBJECT_TPC6_CFG_BASE 0x7FFCF86D80ull 2479#define QM_SYNC_OBJECT_TPC6_CFG_MAX_OFFSET 0x8000 2480#define QM_SYNC_OBJECT_TPC6_CFG_SECTION 0x8000 2481#define mmQM_TPC6_CFG_BASE 0x7FFCF86D88ull 2482#define QM_TPC6_CFG_MAX_OFFSET 0xB800 2483#define QM_TPC6_CFG_SECTION 0x2780 2484#define mmTPC6_E2E_CRED_BASE 0x7FFCF87000ull 2485#define TPC6_E2E_CRED_MAX_OFFSET 0x1680 2486#define TPC6_E2E_CRED_SECTION 0x1000 2487#define mmTPC6_QM_BASE 0x7FFCF88000ull 2488#define TPC6_QM_MAX_OFFSET 0xD040 2489#define TPC6_QM_SECTION 0x3E000 2490#define mmTPC7_CFG_BASE 0x7FFCFC6000ull 2491#define TPC7_CFG_MAX_OFFSET 0xE400 2492#define TPC7_CFG_SECTION 0x4000 2493#define mmKERNEL_TENSOR_0_TPC7_CFG_BASE 0x7FFCFC6400ull 2494#define KERNEL_TENSOR_0_TPC7_CFG_MAX_OFFSET 0x3800 2495#define KERNEL_TENSOR_0_TPC7_CFG_SECTION 0x3800 2496#define mmKERNEL_TENSOR_1_TPC7_CFG_BASE 0x7FFCFC6438ull 2497#define KERNEL_TENSOR_1_TPC7_CFG_MAX_OFFSET 0x3800 2498#define KERNEL_TENSOR_1_TPC7_CFG_SECTION 0x3800 2499#define mmKERNEL_TENSOR_2_TPC7_CFG_BASE 0x7FFCFC6470ull 2500#define KERNEL_TENSOR_2_TPC7_CFG_MAX_OFFSET 0x3800 2501#define KERNEL_TENSOR_2_TPC7_CFG_SECTION 0x3800 2502#define mmKERNEL_TENSOR_3_TPC7_CFG_BASE 0x7FFCFC64A8ull 2503#define KERNEL_TENSOR_3_TPC7_CFG_MAX_OFFSET 0x3800 2504#define KERNEL_TENSOR_3_TPC7_CFG_SECTION 0x3800 2505#define mmKERNEL_TENSOR_4_TPC7_CFG_BASE 0x7FFCFC64E0ull 2506#define KERNEL_TENSOR_4_TPC7_CFG_MAX_OFFSET 0x3800 2507#define KERNEL_TENSOR_4_TPC7_CFG_SECTION 0x3800 2508#define mmKERNEL_TENSOR_5_TPC7_CFG_BASE 0x7FFCFC6518ull 2509#define KERNEL_TENSOR_5_TPC7_CFG_MAX_OFFSET 0x3800 2510#define KERNEL_TENSOR_5_TPC7_CFG_SECTION 0x3800 2511#define mmKERNEL_TENSOR_6_TPC7_CFG_BASE 0x7FFCFC6550ull 2512#define KERNEL_TENSOR_6_TPC7_CFG_MAX_OFFSET 0x3800 2513#define KERNEL_TENSOR_6_TPC7_CFG_SECTION 0x3800 2514#define mmKERNEL_TENSOR_7_TPC7_CFG_BASE 0x7FFCFC6588ull 2515#define KERNEL_TENSOR_7_TPC7_CFG_MAX_OFFSET 0x3800 2516#define KERNEL_TENSOR_7_TPC7_CFG_SECTION 0x3800 2517#define mmKERNEL_TENSOR_8_TPC7_CFG_BASE 0x7FFCFC65C0ull 2518#define KERNEL_TENSOR_8_TPC7_CFG_MAX_OFFSET 0x3800 2519#define KERNEL_TENSOR_8_TPC7_CFG_SECTION 0x3800 2520#define mmKERNEL_TENSOR_9_TPC7_CFG_BASE 0x7FFCFC65F8ull 2521#define KERNEL_TENSOR_9_TPC7_CFG_MAX_OFFSET 0x3800 2522#define KERNEL_TENSOR_9_TPC7_CFG_SECTION 0x3800 2523#define mmKERNEL_TENSOR_10_TPC7_CFG_BASE 0x7FFCFC6630ull 2524#define KERNEL_TENSOR_10_TPC7_CFG_MAX_OFFSET 0x3800 2525#define KERNEL_TENSOR_10_TPC7_CFG_SECTION 0x3800 2526#define mmKERNEL_TENSOR_11_TPC7_CFG_BASE 0x7FFCFC6668ull 2527#define KERNEL_TENSOR_11_TPC7_CFG_MAX_OFFSET 0x3800 2528#define KERNEL_TENSOR_11_TPC7_CFG_SECTION 0x3800 2529#define mmKERNEL_TENSOR_12_TPC7_CFG_BASE 0x7FFCFC66A0ull 2530#define KERNEL_TENSOR_12_TPC7_CFG_MAX_OFFSET 0x3800 2531#define KERNEL_TENSOR_12_TPC7_CFG_SECTION 0x3800 2532#define mmKERNEL_TENSOR_13_TPC7_CFG_BASE 0x7FFCFC66D8ull 2533#define KERNEL_TENSOR_13_TPC7_CFG_MAX_OFFSET 0x3800 2534#define KERNEL_TENSOR_13_TPC7_CFG_SECTION 0x3800 2535#define mmKERNEL_TENSOR_14_TPC7_CFG_BASE 0x7FFCFC6710ull 2536#define KERNEL_TENSOR_14_TPC7_CFG_MAX_OFFSET 0x3800 2537#define KERNEL_TENSOR_14_TPC7_CFG_SECTION 0x3800 2538#define mmKERNEL_TENSOR_15_TPC7_CFG_BASE 0x7FFCFC6748ull 2539#define KERNEL_TENSOR_15_TPC7_CFG_MAX_OFFSET 0x3800 2540#define KERNEL_TENSOR_15_TPC7_CFG_SECTION 0x3800 2541#define mmKERNEL_SYNC_OBJECT_TPC7_CFG_BASE 0x7FFCFC6780ull 2542#define KERNEL_SYNC_OBJECT_TPC7_CFG_MAX_OFFSET 0x8000 2543#define KERNEL_SYNC_OBJECT_TPC7_CFG_SECTION 0x8000 2544#define mmKERNEL_TPC7_CFG_BASE 0x7FFCFC6788ull 2545#define KERNEL_TPC7_CFG_MAX_OFFSET 0xB800 2546#define KERNEL_TPC7_CFG_SECTION 0x2780 2547#define mmQM_TENSOR_0_TPC7_CFG_BASE 0x7FFCFC6A00ull 2548#define QM_TENSOR_0_TPC7_CFG_MAX_OFFSET 0x3800 2549#define QM_TENSOR_0_TPC7_CFG_SECTION 0x3800 2550#define mmQM_TENSOR_1_TPC7_CFG_BASE 0x7FFCFC6A38ull 2551#define QM_TENSOR_1_TPC7_CFG_MAX_OFFSET 0x3800 2552#define QM_TENSOR_1_TPC7_CFG_SECTION 0x3800 2553#define mmQM_TENSOR_2_TPC7_CFG_BASE 0x7FFCFC6A70ull 2554#define QM_TENSOR_2_TPC7_CFG_MAX_OFFSET 0x3800 2555#define QM_TENSOR_2_TPC7_CFG_SECTION 0x3800 2556#define mmQM_TENSOR_3_TPC7_CFG_BASE 0x7FFCFC6AA8ull 2557#define QM_TENSOR_3_TPC7_CFG_MAX_OFFSET 0x3800 2558#define QM_TENSOR_3_TPC7_CFG_SECTION 0x3800 2559#define mmQM_TENSOR_4_TPC7_CFG_BASE 0x7FFCFC6AE0ull 2560#define QM_TENSOR_4_TPC7_CFG_MAX_OFFSET 0x3800 2561#define QM_TENSOR_4_TPC7_CFG_SECTION 0x3800 2562#define mmQM_TENSOR_5_TPC7_CFG_BASE 0x7FFCFC6B18ull 2563#define QM_TENSOR_5_TPC7_CFG_MAX_OFFSET 0x3800 2564#define QM_TENSOR_5_TPC7_CFG_SECTION 0x3800 2565#define mmQM_TENSOR_6_TPC7_CFG_BASE 0x7FFCFC6B50ull 2566#define QM_TENSOR_6_TPC7_CFG_MAX_OFFSET 0x3800 2567#define QM_TENSOR_6_TPC7_CFG_SECTION 0x3800 2568#define mmQM_TENSOR_7_TPC7_CFG_BASE 0x7FFCFC6B88ull 2569#define QM_TENSOR_7_TPC7_CFG_MAX_OFFSET 0x3800 2570#define QM_TENSOR_7_TPC7_CFG_SECTION 0x3800 2571#define mmQM_TENSOR_8_TPC7_CFG_BASE 0x7FFCFC6BC0ull 2572#define QM_TENSOR_8_TPC7_CFG_MAX_OFFSET 0x3800 2573#define QM_TENSOR_8_TPC7_CFG_SECTION 0x3800 2574#define mmQM_TENSOR_9_TPC7_CFG_BASE 0x7FFCFC6BF8ull 2575#define QM_TENSOR_9_TPC7_CFG_MAX_OFFSET 0x3800 2576#define QM_TENSOR_9_TPC7_CFG_SECTION 0x3800 2577#define mmQM_TENSOR_10_TPC7_CFG_BASE 0x7FFCFC6C30ull 2578#define QM_TENSOR_10_TPC7_CFG_MAX_OFFSET 0x3800 2579#define QM_TENSOR_10_TPC7_CFG_SECTION 0x3800 2580#define mmQM_TENSOR_11_TPC7_CFG_BASE 0x7FFCFC6C68ull 2581#define QM_TENSOR_11_TPC7_CFG_MAX_OFFSET 0x3800 2582#define QM_TENSOR_11_TPC7_CFG_SECTION 0x3800 2583#define mmQM_TENSOR_12_TPC7_CFG_BASE 0x7FFCFC6CA0ull 2584#define QM_TENSOR_12_TPC7_CFG_MAX_OFFSET 0x3800 2585#define QM_TENSOR_12_TPC7_CFG_SECTION 0x3800 2586#define mmQM_TENSOR_13_TPC7_CFG_BASE 0x7FFCFC6CD8ull 2587#define QM_TENSOR_13_TPC7_CFG_MAX_OFFSET 0x3800 2588#define QM_TENSOR_13_TPC7_CFG_SECTION 0x3800 2589#define mmQM_TENSOR_14_TPC7_CFG_BASE 0x7FFCFC6D10ull 2590#define QM_TENSOR_14_TPC7_CFG_MAX_OFFSET 0x3800 2591#define QM_TENSOR_14_TPC7_CFG_SECTION 0x3800 2592#define mmQM_TENSOR_15_TPC7_CFG_BASE 0x7FFCFC6D48ull 2593#define QM_TENSOR_15_TPC7_CFG_MAX_OFFSET 0x3800 2594#define QM_TENSOR_15_TPC7_CFG_SECTION 0x3800 2595#define mmQM_SYNC_OBJECT_TPC7_CFG_BASE 0x7FFCFC6D80ull 2596#define QM_SYNC_OBJECT_TPC7_CFG_MAX_OFFSET 0x8000 2597#define QM_SYNC_OBJECT_TPC7_CFG_SECTION 0x8000 2598#define mmQM_TPC7_CFG_BASE 0x7FFCFC6D88ull 2599#define QM_TPC7_CFG_MAX_OFFSET 0xB800 2600#define QM_TPC7_CFG_SECTION 0x2780 2601#define mmTPC7_E2E_CRED_BASE 0x7FFCFC7000ull 2602#define TPC7_E2E_CRED_MAX_OFFSET 0x1680 2603#define TPC7_E2E_CRED_SECTION 0x1000 2604#define mmTPC7_QM_BASE 0x7FFCFC8000ull 2605#define TPC7_QM_MAX_OFFSET 0xD040 2606#define TPC7_QM_SECTION 0x1038000 2607#define mmMME_S_ROM_TABLE_BASE 0x7FFE000000ull 2608#define MME_S_ROM_TABLE_MAX_OFFSET 0x1000 2609#define MME_S_ROM_TABLE_SECTION 0x21000 2610#define mmMME0_ACC_STM_BASE 0x7FFE021000ull 2611#define MME0_ACC_STM_MAX_OFFSET 0x1000 2612#define MME0_ACC_STM_SECTION 0x1000 2613#define mmMME0_ACC_CTI_BASE 0x7FFE022000ull 2614#define MME0_ACC_CTI_MAX_OFFSET 0x1000 2615#define MME0_ACC_CTI_SECTION 0x1000 2616#define mmMME0_ACC_ETF_BASE 0x7FFE023000ull 2617#define MME0_ACC_ETF_MAX_OFFSET 0x1000 2618#define MME0_ACC_ETF_SECTION 0x1000 2619#define mmMME0_ACC_SPMU_BASE 0x7FFE024000ull 2620#define MME0_ACC_SPMU_MAX_OFFSET 0x1000 2621#define MME0_ACC_SPMU_SECTION 0x1000 2622#define mmMME0_ACC_CTI0_BASE 0x7FFE025000ull 2623#define MME0_ACC_CTI0_MAX_OFFSET 0x1000 2624#define MME0_ACC_CTI0_SECTION 0x1000 2625#define mmMME0_ACC_CTI1_BASE 0x7FFE026000ull 2626#define MME0_ACC_CTI1_MAX_OFFSET 0x1000 2627#define MME0_ACC_CTI1_SECTION 0x1000 2628#define mmMME0_ACC_BMON0_BASE 0x7FFE027000ull 2629#define MME0_ACC_BMON0_MAX_OFFSET 0x1000 2630#define MME0_ACC_BMON0_SECTION 0x9000 2631#define mmMME0_ACC_FUNNEL_BASE 0x7FFE030000ull 2632#define MME0_ACC_FUNNEL_MAX_OFFSET 0x1000 2633#define MME0_ACC_FUNNEL_SECTION 0x11000 2634#define mmMME0_SBAB_STM_BASE 0x7FFE041000ull 2635#define MME0_SBAB_STM_MAX_OFFSET 0x1000 2636#define MME0_SBAB_STM_SECTION 0x1000 2637#define mmMME0_SBAB_CTI_BASE 0x7FFE042000ull 2638#define MME0_SBAB_CTI_MAX_OFFSET 0x1000 2639#define MME0_SBAB_CTI_SECTION 0x1000 2640#define mmMME0_SBAB_ETF_BASE 0x7FFE043000ull 2641#define MME0_SBAB_ETF_MAX_OFFSET 0x1000 2642#define MME0_SBAB_ETF_SECTION 0x1000 2643#define mmMME0_SBAB_SPMU_BASE 0x7FFE044000ull 2644#define MME0_SBAB_SPMU_MAX_OFFSET 0x1000 2645#define MME0_SBAB_SPMU_SECTION 0x1000 2646#define mmMME0_SBAB_CTI0_BASE 0x7FFE045000ull 2647#define MME0_SBAB_CTI0_MAX_OFFSET 0x1000 2648#define MME0_SBAB_CTI0_SECTION 0x1000 2649#define mmMME0_SBAB_CTI1_BASE 0x7FFE046000ull 2650#define MME0_SBAB_CTI1_MAX_OFFSET 0x1000 2651#define MME0_SBAB_CTI1_SECTION 0x1000 2652#define mmMME0_SBAB_BMON0_BASE 0x7FFE047000ull 2653#define MME0_SBAB_BMON0_MAX_OFFSET 0x1000 2654#define MME0_SBAB_BMON0_SECTION 0x1000 2655#define mmMME0_SBAB_BMON1_BASE 0x7FFE048000ull 2656#define MME0_SBAB_BMON1_MAX_OFFSET 0x1000 2657#define MME0_SBAB_BMON1_SECTION 0x19000 2658#define mmMME0_CTRL_STM_BASE 0x7FFE061000ull 2659#define MME0_CTRL_STM_MAX_OFFSET 0x1000 2660#define MME0_CTRL_STM_SECTION 0x1000 2661#define mmMME0_CTRL_CTI_BASE 0x7FFE062000ull 2662#define MME0_CTRL_CTI_MAX_OFFSET 0x1000 2663#define MME0_CTRL_CTI_SECTION 0x1000 2664#define mmMME0_CTRL_ETF_BASE 0x7FFE063000ull 2665#define MME0_CTRL_ETF_MAX_OFFSET 0x1000 2666#define MME0_CTRL_ETF_SECTION 0x1000 2667#define mmMME0_CTRL_SPMU_BASE 0x7FFE064000ull 2668#define MME0_CTRL_SPMU_MAX_OFFSET 0x1000 2669#define MME0_CTRL_SPMU_SECTION 0x1000 2670#define mmMME0_CTRL_CTI0_BASE 0x7FFE065000ull 2671#define MME0_CTRL_CTI0_MAX_OFFSET 0x1000 2672#define MME0_CTRL_CTI0_SECTION 0x1000 2673#define mmMME0_CTRL_CTI1_BASE 0x7FFE066000ull 2674#define MME0_CTRL_CTI1_MAX_OFFSET 0x1000 2675#define MME0_CTRL_CTI1_SECTION 0x1000 2676#define mmMME0_CTRL_BMON0_BASE 0x7FFE067000ull 2677#define MME0_CTRL_BMON0_MAX_OFFSET 0x1000 2678#define MME0_CTRL_BMON0_SECTION 0x1000 2679#define mmMME0_CTRL_BMON1_BASE 0x7FFE068000ull 2680#define MME0_CTRL_BMON1_MAX_OFFSET 0x1000 2681#define MME0_CTRL_BMON1_SECTION 0x39000 2682#define mmMME1_ACC_STM_BASE 0x7FFE0A1000ull 2683#define MME1_ACC_STM_MAX_OFFSET 0x1000 2684#define MME1_ACC_STM_SECTION 0x1000 2685#define mmMME1_ACC_CTI_BASE 0x7FFE0A2000ull 2686#define MME1_ACC_CTI_MAX_OFFSET 0x1000 2687#define MME1_ACC_CTI_SECTION 0x1000 2688#define mmMME1_ACC_ETF_BASE 0x7FFE0A3000ull 2689#define MME1_ACC_ETF_MAX_OFFSET 0x1000 2690#define MME1_ACC_ETF_SECTION 0x1000 2691#define mmMME1_ACC_SPMU_BASE 0x7FFE0A4000ull 2692#define MME1_ACC_SPMU_MAX_OFFSET 0x1000 2693#define MME1_ACC_SPMU_SECTION 0x1000 2694#define mmMME1_ACC_CTI0_BASE 0x7FFE0A5000ull 2695#define MME1_ACC_CTI0_MAX_OFFSET 0x1000 2696#define MME1_ACC_CTI0_SECTION 0x1000 2697#define mmMME1_ACC_CTI1_BASE 0x7FFE0A6000ull 2698#define MME1_ACC_CTI1_MAX_OFFSET 0x1000 2699#define MME1_ACC_CTI1_SECTION 0x1000 2700#define mmMME1_ACC_BMON0_BASE 0x7FFE0A7000ull 2701#define MME1_ACC_BMON0_MAX_OFFSET 0x1000 2702#define MME1_ACC_BMON0_SECTION 0x9000 2703#define mmMME1_ACC_FUNNEL_BASE 0x7FFE0B0000ull 2704#define MME1_ACC_FUNNEL_MAX_OFFSET 0x1000 2705#define MME1_ACC_FUNNEL_SECTION 0x11000 2706#define mmMME1_SBAB_STM_BASE 0x7FFE0C1000ull 2707#define MME1_SBAB_STM_MAX_OFFSET 0x1000 2708#define MME1_SBAB_STM_SECTION 0x1000 2709#define mmMME1_SBAB_CTI_BASE 0x7FFE0C2000ull 2710#define MME1_SBAB_CTI_MAX_OFFSET 0x1000 2711#define MME1_SBAB_CTI_SECTION 0x1000 2712#define mmMME1_SBAB_ETF_BASE 0x7FFE0C3000ull 2713#define MME1_SBAB_ETF_MAX_OFFSET 0x1000 2714#define MME1_SBAB_ETF_SECTION 0x1000 2715#define mmMME1_SBAB_SPMU_BASE 0x7FFE0C4000ull 2716#define MME1_SBAB_SPMU_MAX_OFFSET 0x1000 2717#define MME1_SBAB_SPMU_SECTION 0x1000 2718#define mmMME1_SBAB_CTI0_BASE 0x7FFE0C5000ull 2719#define MME1_SBAB_CTI0_MAX_OFFSET 0x1000 2720#define MME1_SBAB_CTI0_SECTION 0x1000 2721#define mmMME1_SBAB_CTI1_BASE 0x7FFE0C6000ull 2722#define MME1_SBAB_CTI1_MAX_OFFSET 0x1000 2723#define MME1_SBAB_CTI1_SECTION 0x1000 2724#define mmMME1_SBAB_BMON0_BASE 0x7FFE0C7000ull 2725#define MME1_SBAB_BMON0_MAX_OFFSET 0x1000 2726#define MME1_SBAB_BMON0_SECTION 0x1000 2727#define mmMME1_SBAB_BMON1_BASE 0x7FFE0C8000ull 2728#define MME1_SBAB_BMON1_MAX_OFFSET 0x1000 2729#define MME1_SBAB_BMON1_SECTION 0x19000 2730#define mmMME1_CTRL_STM_BASE 0x7FFE0E1000ull 2731#define MME1_CTRL_STM_MAX_OFFSET 0x1000 2732#define MME1_CTRL_STM_SECTION 0x1000 2733#define mmMME1_CTRL_CTI_BASE 0x7FFE0E2000ull 2734#define MME1_CTRL_CTI_MAX_OFFSET 0x1000 2735#define MME1_CTRL_CTI_SECTION 0x1000 2736#define mmMME1_CTRL_ETF_BASE 0x7FFE0E3000ull 2737#define MME1_CTRL_ETF_MAX_OFFSET 0x1000 2738#define MME1_CTRL_ETF_SECTION 0x1000 2739#define mmMME1_CTRL_SPMU_BASE 0x7FFE0E4000ull 2740#define MME1_CTRL_SPMU_MAX_OFFSET 0x1000 2741#define MME1_CTRL_SPMU_SECTION 0x1000 2742#define mmMME1_CTRL_CTI0_BASE 0x7FFE0E5000ull 2743#define MME1_CTRL_CTI0_MAX_OFFSET 0x1000 2744#define MME1_CTRL_CTI0_SECTION 0x1000 2745#define mmMME1_CTRL_CTI1_BASE 0x7FFE0E6000ull 2746#define MME1_CTRL_CTI1_MAX_OFFSET 0x1000 2747#define MME1_CTRL_CTI1_SECTION 0x1000 2748#define mmMME1_CTRL_BMON0_BASE 0x7FFE0E7000ull 2749#define MME1_CTRL_BMON0_MAX_OFFSET 0x1000 2750#define MME1_CTRL_BMON0_SECTION 0x1000 2751#define mmMME1_CTRL_BMON1_BASE 0x7FFE0E8000ull 2752#define MME1_CTRL_BMON1_MAX_OFFSET 0x1000 2753#define MME1_CTRL_BMON1_SECTION 0x18000 2754#define mmMME_N_ROM_TABLE_BASE 0x7FFE100000ull 2755#define MME_N_ROM_TABLE_MAX_OFFSET 0x1000 2756#define MME_N_ROM_TABLE_SECTION 0x21000 2757#define mmMME2_ACC_STM_BASE 0x7FFE121000ull 2758#define MME2_ACC_STM_MAX_OFFSET 0x1000 2759#define MME2_ACC_STM_SECTION 0x1000 2760#define mmMME2_ACC_CTI_BASE 0x7FFE122000ull 2761#define MME2_ACC_CTI_MAX_OFFSET 0x1000 2762#define MME2_ACC_CTI_SECTION 0x1000 2763#define mmMME2_MME2_ACC_ETF_BASE 0x7FFE123000ull 2764#define MME2_MME2_ACC_ETF_MAX_OFFSET 0x1000 2765#define MME2_MME2_ACC_ETF_SECTION 0x1000 2766#define mmMME2_ACC_SPMU_BASE 0x7FFE124000ull 2767#define MME2_ACC_SPMU_MAX_OFFSET 0x1000 2768#define MME2_ACC_SPMU_SECTION 0x1000 2769#define mmMME2_ACC_CTI0_BASE 0x7FFE125000ull 2770#define MME2_ACC_CTI0_MAX_OFFSET 0x1000 2771#define MME2_ACC_CTI0_SECTION 0x1000 2772#define mmMME2_ACC_CTI1_BASE 0x7FFE126000ull 2773#define MME2_ACC_CTI1_MAX_OFFSET 0x1000 2774#define MME2_ACC_CTI1_SECTION 0x1000 2775#define mmMME2_ACC_BMON0_BASE 0x7FFE127000ull 2776#define MME2_ACC_BMON0_MAX_OFFSET 0x1000 2777#define MME2_ACC_BMON0_SECTION 0x9000 2778#define mmMME2_ACC_FUNNEL_BASE 0x7FFE130000ull 2779#define MME2_ACC_FUNNEL_MAX_OFFSET 0x1000 2780#define MME2_ACC_FUNNEL_SECTION 0x11000 2781#define mmMME2_SBAB_STM_BASE 0x7FFE141000ull 2782#define MME2_SBAB_STM_MAX_OFFSET 0x1000 2783#define MME2_SBAB_STM_SECTION 0x1000 2784#define mmMME2_SBAB_CTI_BASE 0x7FFE142000ull 2785#define MME2_SBAB_CTI_MAX_OFFSET 0x1000 2786#define MME2_SBAB_CTI_SECTION 0x1000 2787#define mmMME2_SBAB_ETF_BASE 0x7FFE143000ull 2788#define MME2_SBAB_ETF_MAX_OFFSET 0x1000 2789#define MME2_SBAB_ETF_SECTION 0x1000 2790#define mmMME2_SBAB_SPMU_BASE 0x7FFE144000ull 2791#define MME2_SBAB_SPMU_MAX_OFFSET 0x1000 2792#define MME2_SBAB_SPMU_SECTION 0x1000 2793#define mmMME2_SBAB_CTI0_BASE 0x7FFE145000ull 2794#define MME2_SBAB_CTI0_MAX_OFFSET 0x1000 2795#define MME2_SBAB_CTI0_SECTION 0x1000 2796#define mmMME2_SBAB_CTI1_BASE 0x7FFE146000ull 2797#define MME2_SBAB_CTI1_MAX_OFFSET 0x1000 2798#define MME2_SBAB_CTI1_SECTION 0x1000 2799#define mmMME2_SBAB_BMON0_BASE 0x7FFE147000ull 2800#define MME2_SBAB_BMON0_MAX_OFFSET 0x1000 2801#define MME2_SBAB_BMON0_SECTION 0x1000 2802#define mmMME2_SBAB_BMON1_BASE 0x7FFE148000ull 2803#define MME2_SBAB_BMON1_MAX_OFFSET 0x1000 2804#define MME2_SBAB_BMON1_SECTION 0x19000 2805#define mmMME2_CTRL_STM_BASE 0x7FFE161000ull 2806#define MME2_CTRL_STM_MAX_OFFSET 0x1000 2807#define MME2_CTRL_STM_SECTION 0x1000 2808#define mmMME2_CTRL_CTI_BASE 0x7FFE162000ull 2809#define MME2_CTRL_CTI_MAX_OFFSET 0x1000 2810#define MME2_CTRL_CTI_SECTION 0x1000 2811#define mmMME2_CTRL_ETF_BASE 0x7FFE163000ull 2812#define MME2_CTRL_ETF_MAX_OFFSET 0x1000 2813#define MME2_CTRL_ETF_SECTION 0x1000 2814#define mmMME2_CTRL_SPMU_BASE 0x7FFE164000ull 2815#define MME2_CTRL_SPMU_MAX_OFFSET 0x1000 2816#define MME2_CTRL_SPMU_SECTION 0x1000 2817#define mmMME2_CTRL_CTI0_BASE 0x7FFE165000ull 2818#define MME2_CTRL_CTI0_MAX_OFFSET 0x1000 2819#define MME2_CTRL_CTI0_SECTION 0x1000 2820#define mmMME2_CTRL_CTI1_BASE 0x7FFE166000ull 2821#define MME2_CTRL_CTI1_MAX_OFFSET 0x1000 2822#define MME2_CTRL_CTI1_SECTION 0x1000 2823#define mmMME2_CTRL_BMON0_BASE 0x7FFE167000ull 2824#define MME2_CTRL_BMON0_MAX_OFFSET 0x1000 2825#define MME2_CTRL_BMON0_SECTION 0x1000 2826#define mmMME2_CTRL_BMON1_BASE 0x7FFE168000ull 2827#define MME2_CTRL_BMON1_MAX_OFFSET 0x1000 2828#define MME2_CTRL_BMON1_SECTION 0x39000 2829#define mmMME3_ACC_STM_BASE 0x7FFE1A1000ull 2830#define MME3_ACC_STM_MAX_OFFSET 0x1000 2831#define MME3_ACC_STM_SECTION 0x1000 2832#define mmMME3_ACC_CTI_BASE 0x7FFE1A2000ull 2833#define MME3_ACC_CTI_MAX_OFFSET 0x1000 2834#define MME3_ACC_CTI_SECTION 0x1000 2835#define mmMME3_ACC_ETF_BASE 0x7FFE1A3000ull 2836#define MME3_ACC_ETF_MAX_OFFSET 0x1000 2837#define MME3_ACC_ETF_SECTION 0x1000 2838#define mmMME3_ACC_SPMU_BASE 0x7FFE1A4000ull 2839#define MME3_ACC_SPMU_MAX_OFFSET 0x1000 2840#define MME3_ACC_SPMU_SECTION 0x1000 2841#define mmMME3_ACC_CTI0_BASE 0x7FFE1A5000ull 2842#define MME3_ACC_CTI0_MAX_OFFSET 0x1000 2843#define MME3_ACC_CTI0_SECTION 0x1000 2844#define mmMME3_ACC_CTI1_BASE 0x7FFE1A6000ull 2845#define MME3_ACC_CTI1_MAX_OFFSET 0x1000 2846#define MME3_ACC_CTI1_SECTION 0x1000 2847#define mmMME3_ACC_BMON0_BASE 0x7FFE1A7000ull 2848#define MME3_ACC_BMON0_MAX_OFFSET 0x1000 2849#define MME3_ACC_BMON0_SECTION 0x9000 2850#define mmMME3_ACC_FUNNEL_BASE 0x7FFE1B0000ull 2851#define MME3_ACC_FUNNEL_MAX_OFFSET 0x1000 2852#define MME3_ACC_FUNNEL_SECTION 0x11000 2853#define mmMME3_SBAB_STM_BASE 0x7FFE1C1000ull 2854#define MME3_SBAB_STM_MAX_OFFSET 0x1000 2855#define MME3_SBAB_STM_SECTION 0x1000 2856#define mmMME3_SBAB_CTI_BASE 0x7FFE1C2000ull 2857#define MME3_SBAB_CTI_MAX_OFFSET 0x1000 2858#define MME3_SBAB_CTI_SECTION 0x1000 2859#define mmMME3_SBAB_ETF_BASE 0x7FFE1C3000ull 2860#define MME3_SBAB_ETF_MAX_OFFSET 0x1000 2861#define MME3_SBAB_ETF_SECTION 0x1000 2862#define mmMME3_SBAB_SPMU_BASE 0x7FFE1C4000ull 2863#define MME3_SBAB_SPMU_MAX_OFFSET 0x1000 2864#define MME3_SBAB_SPMU_SECTION 0x1000 2865#define mmMME3_SBAB_CTI0_BASE 0x7FFE1C5000ull 2866#define MME3_SBAB_CTI0_MAX_OFFSET 0x1000 2867#define MME3_SBAB_CTI0_SECTION 0x1000 2868#define mmMME3_SBAB_CTI1_BASE 0x7FFE1C6000ull 2869#define MME3_SBAB_CTI1_MAX_OFFSET 0x1000 2870#define MME3_SBAB_CTI1_SECTION 0x1000 2871#define mmMME3_SBAB_BMON0_BASE 0x7FFE1C7000ull 2872#define MME3_SBAB_BMON0_MAX_OFFSET 0x1000 2873#define MME3_SBAB_BMON0_SECTION 0x1000 2874#define mmMME3_SBAB_BMON1_BASE 0x7FFE1C8000ull 2875#define MME3_SBAB_BMON1_MAX_OFFSET 0x1000 2876#define MME3_SBAB_BMON1_SECTION 0x19000 2877#define mmMME3_CTRL_STM_BASE 0x7FFE1E1000ull 2878#define MME3_CTRL_STM_MAX_OFFSET 0x1000 2879#define MME3_CTRL_STM_SECTION 0x1000 2880#define mmMME3_CTRL_CTI_BASE 0x7FFE1E2000ull 2881#define MME3_CTRL_CTI_MAX_OFFSET 0x1000 2882#define MME3_CTRL_CTI_SECTION 0x1000 2883#define mmMME3_CTRL_ETF_BASE 0x7FFE1E3000ull 2884#define MME3_CTRL_ETF_MAX_OFFSET 0x1000 2885#define MME3_CTRL_ETF_SECTION 0x1000 2886#define mmMME3_CTRL_SPMU_BASE 0x7FFE1E4000ull 2887#define MME3_CTRL_SPMU_MAX_OFFSET 0x1000 2888#define MME3_CTRL_SPMU_SECTION 0x1000 2889#define mmMME3_CTRL_CTI0_BASE 0x7FFE1E5000ull 2890#define MME3_CTRL_CTI0_MAX_OFFSET 0x1000 2891#define MME3_CTRL_CTI0_SECTION 0x1000 2892#define mmMME3_CTRL_CTI1_BASE 0x7FFE1E6000ull 2893#define MME3_CTRL_CTI1_MAX_OFFSET 0x1000 2894#define MME3_CTRL_CTI1_SECTION 0x1000 2895#define mmMME3_CTRL_BMON0_BASE 0x7FFE1E7000ull 2896#define MME3_CTRL_BMON0_MAX_OFFSET 0x1000 2897#define MME3_CTRL_BMON0_SECTION 0x1000 2898#define mmMME3_CTRL_BMON1_BASE 0x7FFE1E8000ull 2899#define MME3_CTRL_BMON1_MAX_OFFSET 0x1000 2900#define MME3_CTRL_BMON1_SECTION 0x18000 2901#define mmIC_ROM_TABLE_BASE 0x7FFE200000ull 2902#define IC_ROM_TABLE_MAX_OFFSET 0x1000 2903#define IC_ROM_TABLE_SECTION 0x1000 2904#define mmSRAM_Y0_X0_FUNNEL_BASE 0x7FFE201000ull 2905#define SRAM_Y0_X0_FUNNEL_MAX_OFFSET 0x1000 2906#define SRAM_Y0_X0_FUNNEL_SECTION 0x8000 2907#define mmSRAM_Y0_X1_FUNNEL_BASE 0x7FFE209000ull 2908#define SRAM_Y0_X1_FUNNEL_MAX_OFFSET 0x1000 2909#define SRAM_Y0_X1_FUNNEL_SECTION 0x8000 2910#define mmSRAM_Y0_X2_FUNNEL_BASE 0x7FFE211000ull 2911#define SRAM_Y0_X2_FUNNEL_MAX_OFFSET 0x1000 2912#define SRAM_Y0_X2_FUNNEL_SECTION 0x8000 2913#define mmSRAM_Y0_X3_FUNNEL_BASE 0x7FFE219000ull 2914#define SRAM_Y0_X3_FUNNEL_MAX_OFFSET 0x1000 2915#define SRAM_Y0_X3_FUNNEL_SECTION 0x8000 2916#define mmSRAM_Y0_X4_FUNNEL_BASE 0x7FFE221000ull 2917#define SRAM_Y0_X4_FUNNEL_MAX_OFFSET 0x1000 2918#define SRAM_Y0_X4_FUNNEL_SECTION 0x8000 2919#define mmSRAM_Y0_X5_FUNNEL_BASE 0x7FFE229000ull 2920#define SRAM_Y0_X5_FUNNEL_MAX_OFFSET 0x1000 2921#define SRAM_Y0_X5_FUNNEL_SECTION 0x8000 2922#define mmSRAM_Y0_X6_FUNNEL_BASE 0x7FFE231000ull 2923#define SRAM_Y0_X6_FUNNEL_MAX_OFFSET 0x1000 2924#define SRAM_Y0_X6_FUNNEL_SECTION 0x8000 2925#define mmSRAM_Y0_X7_FUNNEL_BASE 0x7FFE239000ull 2926#define SRAM_Y0_X7_FUNNEL_MAX_OFFSET 0x1000 2927#define SRAM_Y0_X7_FUNNEL_SECTION 0x8000 2928#define mmSRAM_Y1_X0_FUNNEL_BASE 0x7FFE241000ull 2929#define SRAM_Y1_X0_FUNNEL_MAX_OFFSET 0x1000 2930#define SRAM_Y1_X0_FUNNEL_SECTION 0x8000 2931#define mmSRAM_Y1_X1_FUNNEL_BASE 0x7FFE249000ull 2932#define SRAM_Y1_X1_FUNNEL_MAX_OFFSET 0x1000 2933#define SRAM_Y1_X1_FUNNEL_SECTION 0x8000 2934#define mmSRAM_Y1_X2_FUNNEL_BASE 0x7FFE251000ull 2935#define SRAM_Y1_X2_FUNNEL_MAX_OFFSET 0x1000 2936#define SRAM_Y1_X2_FUNNEL_SECTION 0x8000 2937#define mmSRAM_Y1_X3_FUNNEL_BASE 0x7FFE259000ull 2938#define SRAM_Y1_X3_FUNNEL_MAX_OFFSET 0x1000 2939#define SRAM_Y1_X3_FUNNEL_SECTION 0x8000 2940#define mmSRAM_Y1_X4_FUNNEL_BASE 0x7FFE261000ull 2941#define SRAM_Y1_X4_FUNNEL_MAX_OFFSET 0x1000 2942#define SRAM_Y1_X4_FUNNEL_SECTION 0x8000 2943#define mmSRAM_Y1_X5_FUNNEL_BASE 0x7FFE269000ull 2944#define SRAM_Y1_X5_FUNNEL_MAX_OFFSET 0x1000 2945#define SRAM_Y1_X5_FUNNEL_SECTION 0x8000 2946#define mmSRAM_Y1_X6_FUNNEL_BASE 0x7FFE271000ull 2947#define SRAM_Y1_X6_FUNNEL_MAX_OFFSET 0x1000 2948#define SRAM_Y1_X6_FUNNEL_SECTION 0x8000 2949#define mmSRAM_Y1_X7_FUNNEL_BASE 0x7FFE279000ull 2950#define SRAM_Y1_X7_FUNNEL_MAX_OFFSET 0x1000 2951#define SRAM_Y1_X7_FUNNEL_SECTION 0x8000 2952#define mmSRAM_Y2_X0_FUNNEL_BASE 0x7FFE281000ull 2953#define SRAM_Y2_X0_FUNNEL_MAX_OFFSET 0x1000 2954#define SRAM_Y2_X0_FUNNEL_SECTION 0x8000 2955#define mmSRAM_Y2_X1_FUNNEL_BASE 0x7FFE289000ull 2956#define SRAM_Y2_X1_FUNNEL_MAX_OFFSET 0x1000 2957#define SRAM_Y2_X1_FUNNEL_SECTION 0x8000 2958#define mmSRAM_Y2_X2_FUNNEL_BASE 0x7FFE291000ull 2959#define SRAM_Y2_X2_FUNNEL_MAX_OFFSET 0x1000 2960#define SRAM_Y2_X2_FUNNEL_SECTION 0x8000 2961#define mmSRAM_Y2_X3_FUNNEL_BASE 0x7FFE299000ull 2962#define SRAM_Y2_X3_FUNNEL_MAX_OFFSET 0x1000 2963#define SRAM_Y2_X3_FUNNEL_SECTION 0x8000 2964#define mmSRAM_Y2_X4_FUNNEL_BASE 0x7FFE2A1000ull 2965#define SRAM_Y2_X4_FUNNEL_MAX_OFFSET 0x1000 2966#define SRAM_Y2_X4_FUNNEL_SECTION 0x8000 2967#define mmSRAM_Y2_X5_FUNNEL_BASE 0x7FFE2A9000ull 2968#define SRAM_Y2_X5_FUNNEL_MAX_OFFSET 0x1000 2969#define SRAM_Y2_X5_FUNNEL_SECTION 0x8000 2970#define mmSRAM_Y2_X6_FUNNEL_BASE 0x7FFE2B1000ull 2971#define SRAM_Y2_X6_FUNNEL_MAX_OFFSET 0x1000 2972#define SRAM_Y2_X6_FUNNEL_SECTION 0x8000 2973#define mmSRAM_Y2_X7_FUNNEL_BASE 0x7FFE2B9000ull 2974#define SRAM_Y2_X7_FUNNEL_MAX_OFFSET 0x1000 2975#define SRAM_Y2_X7_FUNNEL_SECTION 0x8000 2976#define mmSRAM_Y3_X0_FUNNEL_BASE 0x7FFE2C1000ull 2977#define SRAM_Y3_X0_FUNNEL_MAX_OFFSET 0x1000 2978#define SRAM_Y3_X0_FUNNEL_SECTION 0x8000 2979#define mmSRAM_Y3_X1_FUNNEL_BASE 0x7FFE2C9000ull 2980#define SRAM_Y3_X1_FUNNEL_MAX_OFFSET 0x1000 2981#define SRAM_Y3_X1_FUNNEL_SECTION 0x8000 2982#define mmSRAM_Y3_X2_FUNNEL_BASE 0x7FFE2D1000ull 2983#define SRAM_Y3_X2_FUNNEL_MAX_OFFSET 0x1000 2984#define SRAM_Y3_X2_FUNNEL_SECTION 0x8000 2985#define mmSRAM_Y3_X4_FUNNEL_BASE 0x7FFE2D9000ull 2986#define SRAM_Y3_X4_FUNNEL_MAX_OFFSET 0x1000 2987#define SRAM_Y3_X4_FUNNEL_SECTION 0x8000 2988#define mmSRAM_Y3_X3_FUNNEL_BASE 0x7FFE2E1000ull 2989#define SRAM_Y3_X3_FUNNEL_MAX_OFFSET 0x1000 2990#define SRAM_Y3_X3_FUNNEL_SECTION 0x8000 2991#define mmSRAM_Y3_X5_FUNNEL_BASE 0x7FFE2E9000ull 2992#define SRAM_Y3_X5_FUNNEL_MAX_OFFSET 0x1000 2993#define SRAM_Y3_X5_FUNNEL_SECTION 0x8000 2994#define mmSRAM_Y3_X6_FUNNEL_BASE 0x7FFE2F1000ull 2995#define SRAM_Y3_X6_FUNNEL_MAX_OFFSET 0x1000 2996#define SRAM_Y3_X6_FUNNEL_SECTION 0x8000 2997#define mmSRAM_Y3_X7_FUNNEL_BASE 0x7FFE2F9000ull 2998#define SRAM_Y3_X7_FUNNEL_MAX_OFFSET 0x1000 2999#define SRAM_Y3_X7_FUNNEL_SECTION 0x7000 3000#define mmIF_ROM_TABLE_BASE 0x7FFE300000ull 3001#define IF_ROM_TABLE_MAX_OFFSET 0x1000 3002#define IF_ROM_TABLE_SECTION 0x1000 3003#define mmSIF_FUNNEL_0_BASE 0x7FFE301000ull 3004#define SIF_FUNNEL_0_MAX_OFFSET 0x1000 3005#define SIF_FUNNEL_0_SECTION 0x10000 3006#define mmSIF_FUNNEL_1_BASE 0x7FFE311000ull 3007#define SIF_FUNNEL_1_MAX_OFFSET 0x1000 3008#define SIF_FUNNEL_1_SECTION 0x10000 3009#define mmSIF_FUNNEL_2_BASE 0x7FFE321000ull 3010#define SIF_FUNNEL_2_MAX_OFFSET 0x1000 3011#define SIF_FUNNEL_2_SECTION 0x10000 3012#define mmSIF_FUNNEL_3_BASE 0x7FFE331000ull 3013#define SIF_FUNNEL_3_MAX_OFFSET 0x1000 3014#define SIF_FUNNEL_3_SECTION 0x10000 3015#define mmSIF_FUNNEL_4_BASE 0x7FFE341000ull 3016#define SIF_FUNNEL_4_MAX_OFFSET 0x1000 3017#define SIF_FUNNEL_4_SECTION 0x10000 3018#define mmSIF_FUNNEL_5_BASE 0x7FFE351000ull 3019#define SIF_FUNNEL_5_MAX_OFFSET 0x1000 3020#define SIF_FUNNEL_5_SECTION 0x10000 3021#define mmSIF_FUNNEL_6_BASE 0x7FFE361000ull 3022#define SIF_FUNNEL_6_MAX_OFFSET 0x1000 3023#define SIF_FUNNEL_6_SECTION 0x10000 3024#define mmSIF_FUNNEL_7_BASE 0x7FFE371000ull 3025#define SIF_FUNNEL_7_MAX_OFFSET 0x1000 3026#define SIF_FUNNEL_7_SECTION 0x10000 3027#define mmNIF_FUNNEL_0_BASE 0x7FFE381000ull 3028#define NIF_FUNNEL_0_MAX_OFFSET 0x1000 3029#define NIF_FUNNEL_0_SECTION 0x10000 3030#define mmNIF_FUNNEL_1_BASE 0x7FFE391000ull 3031#define NIF_FUNNEL_1_MAX_OFFSET 0x1000 3032#define NIF_FUNNEL_1_SECTION 0x10000 3033#define mmNIF_FUNNEL_2_BASE 0x7FFE3A1000ull 3034#define NIF_FUNNEL_2_MAX_OFFSET 0x1000 3035#define NIF_FUNNEL_2_SECTION 0x10000 3036#define mmNIF_FUNNEL_3_BASE 0x7FFE3B1000ull 3037#define NIF_FUNNEL_3_MAX_OFFSET 0x1000 3038#define NIF_FUNNEL_3_SECTION 0x10000 3039#define mmNIF_FUNNEL_4_BASE 0x7FFE3C1000ull 3040#define NIF_FUNNEL_4_MAX_OFFSET 0x1000 3041#define NIF_FUNNEL_4_SECTION 0x10000 3042#define mmNIF_FUNNEL_5_BASE 0x7FFE3D1000ull 3043#define NIF_FUNNEL_5_MAX_OFFSET 0x1000 3044#define NIF_FUNNEL_5_SECTION 0x10000 3045#define mmNIF_FUNNEL_6_BASE 0x7FFE3E1000ull 3046#define NIF_FUNNEL_6_MAX_OFFSET 0x1000 3047#define NIF_FUNNEL_6_SECTION 0x10000 3048#define mmNIF_FUNNEL_7_BASE 0x7FFE3F1000ull 3049#define NIF_FUNNEL_7_MAX_OFFSET 0x1000 3050#define NIF_FUNNEL_7_SECTION 0xF000 3051#define mmDMA_IF_ROM_TABLE_BASE 0x7FFE400000ull 3052#define DMA_IF_ROM_TABLE_MAX_OFFSET 0x1000 3053#define DMA_IF_ROM_TABLE_SECTION 0x1000 3054#define mmDMA_IF_W_S_STM_BASE 0x7FFE401000ull 3055#define DMA_IF_W_S_STM_MAX_OFFSET 0x1000 3056#define DMA_IF_W_S_STM_SECTION 0x1000 3057#define mmDMA_IF_W_S_CTI_BASE 0x7FFE402000ull 3058#define DMA_IF_W_S_CTI_MAX_OFFSET 0x1000 3059#define DMA_IF_W_S_CTI_SECTION 0x1000 3060#define mmDMA_IF_W_S_ETF_BASE 0x7FFE403000ull 3061#define DMA_IF_W_S_ETF_MAX_OFFSET 0x1000 3062#define DMA_IF_W_S_ETF_SECTION 0x2000 3063#define mmDMA_IF_W_S_BMON0_CTI_BASE 0x7FFE405000ull 3064#define DMA_IF_W_S_BMON0_CTI_MAX_OFFSET 0x1000 3065#define DMA_IF_W_S_BMON0_CTI_SECTION 0x1000 3066#define mmDMA_IF_W_S_BMON1_CTI_BASE 0x7FFE406000ull 3067#define DMA_IF_W_S_BMON1_CTI_MAX_OFFSET 0x1000 3068#define DMA_IF_W_S_BMON1_CTI_SECTION 0x1000 3069#define mmDMA_IF_W_S_HBM0_WR_BMON_BASE 0x7FFE407000ull 3070#define DMA_IF_W_S_HBM0_WR_BMON_MAX_OFFSET 0x1000 3071#define DMA_IF_W_S_HBM0_WR_BMON_SECTION 0x1000 3072#define mmDMA_IF_W_S_HBM0_RD_BMON_BASE 0x7FFE408000ull 3073#define DMA_IF_W_S_HBM0_RD_BMON_MAX_OFFSET 0x1000 3074#define DMA_IF_W_S_HBM0_RD_BMON_SECTION 0x1000 3075#define mmDMA_IF_W_S_HBM1_WR_BMON_BASE 0x7FFE409000ull 3076#define DMA_IF_W_S_HBM1_WR_BMON_MAX_OFFSET 0x1000 3077#define DMA_IF_W_S_HBM1_WR_BMON_SECTION 0x1000 3078#define mmDMA_IF_W_S_HBM1_RD_BMON_BASE 0x7FFE40A000ull 3079#define DMA_IF_W_S_HBM1_RD_BMON_MAX_OFFSET 0x1000 3080#define DMA_IF_W_S_HBM1_RD_BMON_SECTION 0x1000 3081#define mmDMA_IF_W_S_SOB_WR_BMON_BASE 0x7FFE40B000ull 3082#define DMA_IF_W_S_SOB_WR_BMON_MAX_OFFSET 0x1000 3083#define DMA_IF_W_S_SOB_WR_BMON_SECTION 0x4000 3084#define mmDMA_IF_W_S_FUNNEL_BASE 0x7FFE40F000ull 3085#define DMA_IF_W_S_FUNNEL_MAX_OFFSET 0x1000 3086#define DMA_IF_W_S_FUNNEL_SECTION 0x12000 3087#define mmDMA_IF_E_S_STM_BASE 0x7FFE421000ull 3088#define DMA_IF_E_S_STM_MAX_OFFSET 0x1000 3089#define DMA_IF_E_S_STM_SECTION 0x1000 3090#define mmDMA_IF_E_S_CTI_BASE 0x7FFE422000ull 3091#define DMA_IF_E_S_CTI_MAX_OFFSET 0x1000 3092#define DMA_IF_E_S_CTI_SECTION 0x1000 3093#define mmDMA_IF_E_S_ETF_BASE 0x7FFE423000ull 3094#define DMA_IF_E_S_ETF_MAX_OFFSET 0x1000 3095#define DMA_IF_E_S_ETF_SECTION 0x2000 3096#define mmDMA_IF_E_S_BMON0_CTI_BASE 0x7FFE425000ull 3097#define DMA_IF_E_S_BMON0_CTI_MAX_OFFSET 0x1000 3098#define DMA_IF_E_S_BMON0_CTI_SECTION 0x1000 3099#define mmDMA_IF_E_S_BMON1_CTI_BASE 0x7FFE426000ull 3100#define DMA_IF_E_S_BMON1_CTI_MAX_OFFSET 0x1000 3101#define DMA_IF_E_S_BMON1_CTI_SECTION 0x1000 3102#define mmDMA_IF_E_S_HBM0_WR_BMON_BASE 0x7FFE427000ull 3103#define DMA_IF_E_S_HBM0_WR_BMON_MAX_OFFSET 0x1000 3104#define DMA_IF_E_S_HBM0_WR_BMON_SECTION 0x1000 3105#define mmDMA_IF_E_S_HBM0_RD_BMON_BASE 0x7FFE428000ull 3106#define DMA_IF_E_S_HBM0_RD_BMON_MAX_OFFSET 0x1000 3107#define DMA_IF_E_S_HBM0_RD_BMON_SECTION 0x1000 3108#define mmDMA_IF_E_S_HBM1_WR_BMON_BASE 0x7FFE429000ull 3109#define DMA_IF_E_S_HBM1_WR_BMON_MAX_OFFSET 0x1000 3110#define DMA_IF_E_S_HBM1_WR_BMON_SECTION 0x1000 3111#define mmDMA_IF_E_S_HBM1_RD_BMON_BASE 0x7FFE42A000ull 3112#define DMA_IF_E_S_HBM1_RD_BMON_MAX_OFFSET 0x1000 3113#define DMA_IF_E_S_HBM1_RD_BMON_SECTION 0x1000 3114#define mmDMA_IF_E_S_SOB_WR_BMON_BASE 0x7FFE42B000ull 3115#define DMA_IF_E_S_SOB_WR_BMON_MAX_OFFSET 0x1000 3116#define DMA_IF_E_S_SOB_WR_BMON_SECTION 0x4000 3117#define mmDMA_IF_E_S_FUNNEL_BASE 0x7FFE42F000ull 3118#define DMA_IF_E_S_FUNNEL_MAX_OFFSET 0x1000 3119#define DMA_IF_E_S_FUNNEL_SECTION 0x12000 3120#define mmDMA_IF_W_N_STM_BASE 0x7FFE441000ull 3121#define DMA_IF_W_N_STM_MAX_OFFSET 0x1000 3122#define DMA_IF_W_N_STM_SECTION 0x1000 3123#define mmDMA_IF_W_N_CTI_BASE 0x7FFE442000ull 3124#define DMA_IF_W_N_CTI_MAX_OFFSET 0x1000 3125#define DMA_IF_W_N_CTI_SECTION 0x1000 3126#define mmDMA_IF_W_N_ETF_BASE 0x7FFE443000ull 3127#define DMA_IF_W_N_ETF_MAX_OFFSET 0x1000 3128#define DMA_IF_W_N_ETF_SECTION 0x2000 3129#define mmDMA_IF_W_N_BMON0_CTI_BASE 0x7FFE445000ull 3130#define DMA_IF_W_N_BMON0_CTI_MAX_OFFSET 0x1000 3131#define DMA_IF_W_N_BMON0_CTI_SECTION 0x1000 3132#define mmDMA_IF_W_N_BMON1_CTI_BASE 0x7FFE446000ull 3133#define DMA_IF_W_N_BMON1_CTI_MAX_OFFSET 0x1000 3134#define DMA_IF_W_N_BMON1_CTI_SECTION 0x1000 3135#define mmDMA_IF_W_N_HBM0_WR_BMON_BASE 0x7FFE447000ull 3136#define DMA_IF_W_N_HBM0_WR_BMON_MAX_OFFSET 0x1000 3137#define DMA_IF_W_N_HBM0_WR_BMON_SECTION 0x1000 3138#define mmDMA_IF_W_N_HBM0_RD_BMON_BASE 0x7FFE448000ull 3139#define DMA_IF_W_N_HBM0_RD_BMON_MAX_OFFSET 0x1000 3140#define DMA_IF_W_N_HBM0_RD_BMON_SECTION 0x1000 3141#define mmDMA_IF_W_N_HBM1_WR_BMON_BASE 0x7FFE449000ull 3142#define DMA_IF_W_N_HBM1_WR_BMON_MAX_OFFSET 0x1000 3143#define DMA_IF_W_N_HBM1_WR_BMON_SECTION 0x1000 3144#define mmDMA_IF_W_N_HBM1_RD_BMON_BASE 0x7FFE44A000ull 3145#define DMA_IF_W_N_HBM1_RD_BMON_MAX_OFFSET 0x1000 3146#define DMA_IF_W_N_HBM1_RD_BMON_SECTION 0x1000 3147#define mmDMA_IF_W_N_SOB_WR_BMON_BASE 0x7FFE44B000ull 3148#define DMA_IF_W_N_SOB_WR_BMON_MAX_OFFSET 0x1000 3149#define DMA_IF_W_N_SOB_WR_BMON_SECTION 0x4000 3150#define mmDMA_IF_W_N_FUNNEL_BASE 0x7FFE44F000ull 3151#define DMA_IF_W_N_FUNNEL_MAX_OFFSET 0x1000 3152#define DMA_IF_W_N_FUNNEL_SECTION 0x12000 3153#define mmDMA_IF_E_N_STM_BASE 0x7FFE461000ull 3154#define DMA_IF_E_N_STM_MAX_OFFSET 0x1000 3155#define DMA_IF_E_N_STM_SECTION 0x1000 3156#define mmDMA_IF_E_N_CTI_BASE 0x7FFE462000ull 3157#define DMA_IF_E_N_CTI_MAX_OFFSET 0x1000 3158#define DMA_IF_E_N_CTI_SECTION 0x1000 3159#define mmDMA_IF_E_N_ETF_BASE 0x7FFE463000ull 3160#define DMA_IF_E_N_ETF_MAX_OFFSET 0x1000 3161#define DMA_IF_E_N_ETF_SECTION 0x2000 3162#define mmDMA_IF_E_N_BMON0_CTI_BASE 0x7FFE465000ull 3163#define DMA_IF_E_N_BMON0_CTI_MAX_OFFSET 0x1000 3164#define DMA_IF_E_N_BMON0_CTI_SECTION 0x1000 3165#define mmDMA_IF_E_N_BMON1_CTI_BASE 0x7FFE466000ull 3166#define DMA_IF_E_N_BMON1_CTI_MAX_OFFSET 0x1000 3167#define DMA_IF_E_N_BMON1_CTI_SECTION 0x1000 3168#define mmDMA_IF_E_N_HBM0_WR_BMON_BASE 0x7FFE467000ull 3169#define DMA_IF_E_N_HBM0_WR_BMON_MAX_OFFSET 0x1000 3170#define DMA_IF_E_N_HBM0_WR_BMON_SECTION 0x1000 3171#define mmDMA_IF_E_N_HBM0_RD_BMON_BASE 0x7FFE468000ull 3172#define DMA_IF_E_N_HBM0_RD_BMON_MAX_OFFSET 0x1000 3173#define DMA_IF_E_N_HBM0_RD_BMON_SECTION 0x1000 3174#define mmDMA_IF_E_N_HBM1_WR_BMON_BASE 0x7FFE469000ull 3175#define DMA_IF_E_N_HBM1_WR_BMON_MAX_OFFSET 0x1000 3176#define DMA_IF_E_N_HBM1_WR_BMON_SECTION 0x1000 3177#define mmDMA_IF_E_N_HBM1_RD_BMON_BASE 0x7FFE46A000ull 3178#define DMA_IF_E_N_HBM1_RD_BMON_MAX_OFFSET 0x1000 3179#define DMA_IF_E_N_HBM1_RD_BMON_SECTION 0x1000 3180#define mmDMA_IF_E_N_SOB_WR_BMON_BASE 0x7FFE46B000ull 3181#define DMA_IF_E_N_SOB_WR_BMON_MAX_OFFSET 0x1000 3182#define DMA_IF_E_N_SOB_WR_BMON_SECTION 0x4000 3183#define mmDMA_IF_E_N_FUNNEL_BASE 0x7FFE46F000ull 3184#define DMA_IF_E_N_FUNNEL_MAX_OFFSET 0x1000 3185#define DMA_IF_E_N_FUNNEL_SECTION 0x11000 3186#define mmCPU_ROM_TABLE_BASE 0x7FFE480000ull 3187#define CPU_ROM_TABLE_MAX_OFFSET 0x1000 3188#define CPU_ROM_TABLE_SECTION 0x1000 3189#define mmCPU_ETF_0_BASE 0x7FFE481000ull 3190#define CPU_ETF_0_MAX_OFFSET 0x1000 3191#define CPU_ETF_0_SECTION 0x1000 3192#define mmCPU_ETF_1_BASE 0x7FFE482000ull 3193#define CPU_ETF_1_MAX_OFFSET 0x1000 3194#define CPU_ETF_1_SECTION 0x2000 3195#define mmCPU_CTI_BASE 0x7FFE484000ull 3196#define CPU_CTI_MAX_OFFSET 0x1000 3197#define CPU_CTI_SECTION 0x1000 3198#define mmCPU_FUNNEL_BASE 0x7FFE485000ull 3199#define CPU_FUNNEL_MAX_OFFSET 0x1000 3200#define CPU_FUNNEL_SECTION 0x1000 3201#define mmCPU_STM_BASE 0x7FFE486000ull 3202#define CPU_STM_MAX_OFFSET 0x1000 3203#define CPU_STM_SECTION 0x1000 3204#define mmCPU_CTI_TRACE_BASE 0x7FFE487000ull 3205#define CPU_CTI_TRACE_MAX_OFFSET 0x1000 3206#define CPU_CTI_TRACE_SECTION 0x1000 3207#define mmCPU_ETF_TRACE_BASE 0x7FFE488000ull 3208#define CPU_ETF_TRACE_MAX_OFFSET 0x1000 3209#define CPU_ETF_TRACE_SECTION 0x1000 3210#define mmCPU_WR_BMON_BASE 0x7FFE489000ull 3211#define CPU_WR_BMON_MAX_OFFSET 0x1000 3212#define CPU_WR_BMON_SECTION 0x1000 3213#define mmCPU_RD_BMON_BASE 0x7FFE48A000ull 3214#define CPU_RD_BMON_MAX_OFFSET 0x1000 3215#define CPU_RD_BMON_SECTION 0x76000 3216#define mmDMA_ROM_TABLE_BASE 0x7FFE500000ull 3217#define DMA_ROM_TABLE_MAX_OFFSET 0x1000 3218#define DMA_ROM_TABLE_SECTION 0x1000 3219#define mmDMA_CH_0_CS_STM_BASE 0x7FFE501000ull 3220#define DMA_CH_0_CS_STM_MAX_OFFSET 0x1000 3221#define DMA_CH_0_CS_STM_SECTION 0x1000 3222#define mmDMA_CH_0_CS_CTI_BASE 0x7FFE502000ull 3223#define DMA_CH_0_CS_CTI_MAX_OFFSET 0x1000 3224#define DMA_CH_0_CS_CTI_SECTION 0x1000 3225#define mmDMA_CH_0_CS_ETF_BASE 0x7FFE503000ull 3226#define DMA_CH_0_CS_ETF_MAX_OFFSET 0x1000 3227#define DMA_CH_0_CS_ETF_SECTION 0x1000 3228#define mmDMA_CH_0_CS_SPMU_BASE 0x7FFE504000ull 3229#define DMA_CH_0_CS_SPMU_MAX_OFFSET 0x1000 3230#define DMA_CH_0_CS_SPMU_SECTION 0x1000 3231#define mmDMA_CH_0_BMON_CTI_BASE 0x7FFE505000ull 3232#define DMA_CH_0_BMON_CTI_MAX_OFFSET 0x1000 3233#define DMA_CH_0_BMON_CTI_SECTION 0x1000 3234#define mmDMA_CH_0_USER_CTI_BASE 0x7FFE506000ull 3235#define DMA_CH_0_USER_CTI_MAX_OFFSET 0x1000 3236#define DMA_CH_0_USER_CTI_SECTION 0x1000 3237#define mmDMA_CH_0_BMON_0_BASE 0x7FFE507000ull 3238#define DMA_CH_0_BMON_0_MAX_OFFSET 0x1000 3239#define DMA_CH_0_BMON_0_SECTION 0x1000 3240#define mmDMA_CH_0_BMON_1_BASE 0x7FFE508000ull 3241#define DMA_CH_0_BMON_1_MAX_OFFSET 0x1000 3242#define DMA_CH_0_BMON_1_SECTION 0x19000 3243#define mmDMA_CH_1_CS_STM_BASE 0x7FFE521000ull 3244#define DMA_CH_1_CS_STM_MAX_OFFSET 0x1000 3245#define DMA_CH_1_CS_STM_SECTION 0x1000 3246#define mmDMA_CH_1_CS_CTI_BASE 0x7FFE522000ull 3247#define DMA_CH_1_CS_CTI_MAX_OFFSET 0x1000 3248#define DMA_CH_1_CS_CTI_SECTION 0x1000 3249#define mmDMA_CH_1_CS_ETF_BASE 0x7FFE523000ull 3250#define DMA_CH_1_CS_ETF_MAX_OFFSET 0x1000 3251#define DMA_CH_1_CS_ETF_SECTION 0x1000 3252#define mmDMA_CH_1_CS_SPMU_BASE 0x7FFE524000ull 3253#define DMA_CH_1_CS_SPMU_MAX_OFFSET 0x1000 3254#define DMA_CH_1_CS_SPMU_SECTION 0x1000 3255#define mmDMA_CH_1_BMON_CTI_BASE 0x7FFE525000ull 3256#define DMA_CH_1_BMON_CTI_MAX_OFFSET 0x1000 3257#define DMA_CH_1_BMON_CTI_SECTION 0x1000 3258#define mmDMA_CH_1_USER_CTI_BASE 0x7FFE526000ull 3259#define DMA_CH_1_USER_CTI_MAX_OFFSET 0x1000 3260#define DMA_CH_1_USER_CTI_SECTION 0x1000 3261#define mmDMA_CH_1_BMON_0_BASE 0x7FFE527000ull 3262#define DMA_CH_1_BMON_0_MAX_OFFSET 0x1000 3263#define DMA_CH_1_BMON_0_SECTION 0x1000 3264#define mmDMA_CH_1_BMON_1_BASE 0x7FFE528000ull 3265#define DMA_CH_1_BMON_1_MAX_OFFSET 0x1000 3266#define DMA_CH_1_BMON_1_SECTION 0x19000 3267#define mmDMA_CH_2_CS_STM_BASE 0x7FFE541000ull 3268#define DMA_CH_2_CS_STM_MAX_OFFSET 0x1000 3269#define DMA_CH_2_CS_STM_SECTION 0x1000 3270#define mmDMA_CH_2_CS_CTI_BASE 0x7FFE542000ull 3271#define DMA_CH_2_CS_CTI_MAX_OFFSET 0x1000 3272#define DMA_CH_2_CS_CTI_SECTION 0x1000 3273#define mmDMA_CH_2_CS_ETF_BASE 0x7FFE543000ull 3274#define DMA_CH_2_CS_ETF_MAX_OFFSET 0x1000 3275#define DMA_CH_2_CS_ETF_SECTION 0x1000 3276#define mmDMA_CH_2_CS_SPMU_BASE 0x7FFE544000ull 3277#define DMA_CH_2_CS_SPMU_MAX_OFFSET 0x1000 3278#define DMA_CH_2_CS_SPMU_SECTION 0x1000 3279#define mmDMA_CH_2_BMON_CTI_BASE 0x7FFE545000ull 3280#define DMA_CH_2_BMON_CTI_MAX_OFFSET 0x1000 3281#define DMA_CH_2_BMON_CTI_SECTION 0x1000 3282#define mmDMA_CH_2_USER_CTI_BASE 0x7FFE546000ull 3283#define DMA_CH_2_USER_CTI_MAX_OFFSET 0x1000 3284#define DMA_CH_2_USER_CTI_SECTION 0x1000 3285#define mmDMA_CH_2_BMON_0_BASE 0x7FFE547000ull 3286#define DMA_CH_2_BMON_0_MAX_OFFSET 0x1000 3287#define DMA_CH_2_BMON_0_SECTION 0x1000 3288#define mmDMA_CH_2_BMON_1_BASE 0x7FFE548000ull 3289#define DMA_CH_2_BMON_1_MAX_OFFSET 0x1000 3290#define DMA_CH_2_BMON_1_SECTION 0x19000 3291#define mmDMA_CH_3_CS_STM_BASE 0x7FFE561000ull 3292#define DMA_CH_3_CS_STM_MAX_OFFSET 0x1000 3293#define DMA_CH_3_CS_STM_SECTION 0x1000 3294#define mmDMA_CH_3_CS_CTI_BASE 0x7FFE562000ull 3295#define DMA_CH_3_CS_CTI_MAX_OFFSET 0x1000 3296#define DMA_CH_3_CS_CTI_SECTION 0x1000 3297#define mmDMA_CH_3_CS_ETF_BASE 0x7FFE563000ull 3298#define DMA_CH_3_CS_ETF_MAX_OFFSET 0x1000 3299#define DMA_CH_3_CS_ETF_SECTION 0x1000 3300#define mmDMA_CH_3_CS_SPMU_BASE 0x7FFE564000ull 3301#define DMA_CH_3_CS_SPMU_MAX_OFFSET 0x1000 3302#define DMA_CH_3_CS_SPMU_SECTION 0x1000 3303#define mmDMA_CH_3_BMON_CTI_BASE 0x7FFE565000ull 3304#define DMA_CH_3_BMON_CTI_MAX_OFFSET 0x1000 3305#define DMA_CH_3_BMON_CTI_SECTION 0x1000 3306#define mmDMA_CH_3_USER_CTI_BASE 0x7FFE566000ull 3307#define DMA_CH_3_USER_CTI_MAX_OFFSET 0x1000 3308#define DMA_CH_3_USER_CTI_SECTION 0x1000 3309#define mmDMA_CH_3_BMON_0_BASE 0x7FFE567000ull 3310#define DMA_CH_3_BMON_0_MAX_OFFSET 0x1000 3311#define DMA_CH_3_BMON_0_SECTION 0x1000 3312#define mmDMA_CH_3_BMON_1_BASE 0x7FFE568000ull 3313#define DMA_CH_3_BMON_1_MAX_OFFSET 0x1000 3314#define DMA_CH_3_BMON_1_SECTION 0x19000 3315#define mmDMA_CH_4_CS_STM_BASE 0x7FFE581000ull 3316#define DMA_CH_4_CS_STM_MAX_OFFSET 0x1000 3317#define DMA_CH_4_CS_STM_SECTION 0x1000 3318#define mmDMA_CH_4_CS_CTI_BASE 0x7FFE582000ull 3319#define DMA_CH_4_CS_CTI_MAX_OFFSET 0x1000 3320#define DMA_CH_4_CS_CTI_SECTION 0x1000 3321#define mmDMA_CH_4_CS_ETF_BASE 0x7FFE583000ull 3322#define DMA_CH_4_CS_ETF_MAX_OFFSET 0x1000 3323#define DMA_CH_4_CS_ETF_SECTION 0x1000 3324#define mmDMA_CH_4_CS_SPMU_BASE 0x7FFE584000ull 3325#define DMA_CH_4_CS_SPMU_MAX_OFFSET 0x1000 3326#define DMA_CH_4_CS_SPMU_SECTION 0x1000 3327#define mmDMA_CH_4_BMON_CTI_BASE 0x7FFE585000ull 3328#define DMA_CH_4_BMON_CTI_MAX_OFFSET 0x1000 3329#define DMA_CH_4_BMON_CTI_SECTION 0x1000 3330#define mmDMA_CH_4_USER_CTI_BASE 0x7FFE586000ull 3331#define DMA_CH_4_USER_CTI_MAX_OFFSET 0x1000 3332#define DMA_CH_4_USER_CTI_SECTION 0x1000 3333#define mmDMA_CH_4_BMON_0_BASE 0x7FFE587000ull 3334#define DMA_CH_4_BMON_0_MAX_OFFSET 0x1000 3335#define DMA_CH_4_BMON_0_SECTION 0x1000 3336#define mmDMA_CH_4_BMON_1_BASE 0x7FFE588000ull 3337#define DMA_CH_4_BMON_1_MAX_OFFSET 0x1000 3338#define DMA_CH_4_BMON_1_SECTION 0x19000 3339#define mmDMA_CH_5_CS_STM_BASE 0x7FFE5A1000ull 3340#define DMA_CH_5_CS_STM_MAX_OFFSET 0x1000 3341#define DMA_CH_5_CS_STM_SECTION 0x1000 3342#define mmDMA_CH_5_CS_CTI_BASE 0x7FFE5A2000ull 3343#define DMA_CH_5_CS_CTI_MAX_OFFSET 0x1000 3344#define DMA_CH_5_CS_CTI_SECTION 0x1000 3345#define mmDMA_CH_5_CS_ETF_BASE 0x7FFE5A3000ull 3346#define DMA_CH_5_CS_ETF_MAX_OFFSET 0x1000 3347#define DMA_CH_5_CS_ETF_SECTION 0x1000 3348#define mmDMA_CH_5_CS_SPMU_BASE 0x7FFE5A4000ull 3349#define DMA_CH_5_CS_SPMU_MAX_OFFSET 0x1000 3350#define DMA_CH_5_CS_SPMU_SECTION 0x1000 3351#define mmDMA_CH_5_BMON_CTI_BASE 0x7FFE5A5000ull 3352#define DMA_CH_5_BMON_CTI_MAX_OFFSET 0x1000 3353#define DMA_CH_5_BMON_CTI_SECTION 0x1000 3354#define mmDMA_CH_5_USER_CTI_BASE 0x7FFE5A6000ull 3355#define DMA_CH_5_USER_CTI_MAX_OFFSET 0x1000 3356#define DMA_CH_5_USER_CTI_SECTION 0x1000 3357#define mmDMA_CH_5_BMON_0_BASE 0x7FFE5A7000ull 3358#define DMA_CH_5_BMON_0_MAX_OFFSET 0x1000 3359#define DMA_CH_5_BMON_0_SECTION 0x1000 3360#define mmDMA_CH_5_BMON_1_BASE 0x7FFE5A8000ull 3361#define DMA_CH_5_BMON_1_MAX_OFFSET 0x1000 3362#define DMA_CH_5_BMON_1_SECTION 0x19000 3363#define mmDMA_CH_6_CS_STM_BASE 0x7FFE5C1000ull 3364#define DMA_CH_6_CS_STM_MAX_OFFSET 0x1000 3365#define DMA_CH_6_CS_STM_SECTION 0x1000 3366#define mmDMA_CH_6_CS_CTI_BASE 0x7FFE5C2000ull 3367#define DMA_CH_6_CS_CTI_MAX_OFFSET 0x1000 3368#define DMA_CH_6_CS_CTI_SECTION 0x1000 3369#define mmDMA_CH_6_CS_ETF_BASE 0x7FFE5C3000ull 3370#define DMA_CH_6_CS_ETF_MAX_OFFSET 0x1000 3371#define DMA_CH_6_CS_ETF_SECTION 0x1000 3372#define mmDMA_CH_6_CS_SPMU_BASE 0x7FFE5C4000ull 3373#define DMA_CH_6_CS_SPMU_MAX_OFFSET 0x1000 3374#define DMA_CH_6_CS_SPMU_SECTION 0x1000 3375#define mmDMA_CH_6_BMON_CTI_BASE 0x7FFE5C5000ull 3376#define DMA_CH_6_BMON_CTI_MAX_OFFSET 0x1000 3377#define DMA_CH_6_BMON_CTI_SECTION 0x1000 3378#define mmDMA_CH_6_USER_CTI_BASE 0x7FFE5C6000ull 3379#define DMA_CH_6_USER_CTI_MAX_OFFSET 0x1000 3380#define DMA_CH_6_USER_CTI_SECTION 0x1000 3381#define mmDMA_CH_6_BMON_0_BASE 0x7FFE5C7000ull 3382#define DMA_CH_6_BMON_0_MAX_OFFSET 0x1000 3383#define DMA_CH_6_BMON_0_SECTION 0x1000 3384#define mmDMA_CH_6_BMON_1_BASE 0x7FFE5C8000ull 3385#define DMA_CH_6_BMON_1_MAX_OFFSET 0x1000 3386#define DMA_CH_6_BMON_1_SECTION 0x19000 3387#define mmDMA_CH_7_CS_STM_BASE 0x7FFE5E1000ull 3388#define DMA_CH_7_CS_STM_MAX_OFFSET 0x1000 3389#define DMA_CH_7_CS_STM_SECTION 0x1000 3390#define mmDMA_CH_7_CS_CTI_BASE 0x7FFE5E2000ull 3391#define DMA_CH_7_CS_CTI_MAX_OFFSET 0x1000 3392#define DMA_CH_7_CS_CTI_SECTION 0x1000 3393#define mmDMA_CH_7_CS_ETF_BASE 0x7FFE5E3000ull 3394#define DMA_CH_7_CS_ETF_MAX_OFFSET 0x1000 3395#define DMA_CH_7_CS_ETF_SECTION 0x1000 3396#define mmDMA_CH_7_CS_SPMU_BASE 0x7FFE5E4000ull 3397#define DMA_CH_7_CS_SPMU_MAX_OFFSET 0x1000 3398#define DMA_CH_7_CS_SPMU_SECTION 0x1000 3399#define mmDMA_CH_7_BMON_CTI_BASE 0x7FFE5E5000ull 3400#define DMA_CH_7_BMON_CTI_MAX_OFFSET 0x1000 3401#define DMA_CH_7_BMON_CTI_SECTION 0x1000 3402#define mmDMA_CH_7_USER_CTI_BASE 0x7FFE5E6000ull 3403#define DMA_CH_7_USER_CTI_MAX_OFFSET 0x1000 3404#define DMA_CH_7_USER_CTI_SECTION 0x1000 3405#define mmDMA_CH_7_BMON_0_BASE 0x7FFE5E7000ull 3406#define DMA_CH_7_BMON_0_MAX_OFFSET 0x1000 3407#define DMA_CH_7_BMON_0_SECTION 0x1000 3408#define mmDMA_CH_7_BMON_1_BASE 0x7FFE5E8000ull 3409#define DMA_CH_7_BMON_1_MAX_OFFSET 0x1000 3410#define DMA_CH_7_BMON_1_SECTION 0x18000 3411#define mmNIC_TPC_FUNNEL_W_S_BASE 0x7FFE600000ull 3412#define NIC_TPC_FUNNEL_W_S_MAX_OFFSET 0x1000 3413#define NIC_TPC_FUNNEL_W_S_SECTION 0x80000 3414#define mmNIC_TPC_FUNNEL_E_S_BASE 0x7FFE680000ull 3415#define NIC_TPC_FUNNEL_E_S_MAX_OFFSET 0x1000 3416#define NIC_TPC_FUNNEL_E_S_SECTION 0x80000 3417#define mmNIC_TPC_FUNNEL_W_N_BASE 0x7FFE700000ull 3418#define NIC_TPC_FUNNEL_W_N_MAX_OFFSET 0x1000 3419#define NIC_TPC_FUNNEL_W_N_SECTION 0x80000 3420#define mmNIC_TPC_FUNNEL_E_N_BASE 0x7FFE780000ull 3421#define NIC_TPC_FUNNEL_E_N_MAX_OFFSET 0x1000 3422#define NIC_TPC_FUNNEL_E_N_SECTION 0x80000 3423#define mmCA53_BASE 0x7FFE800000ull 3424#define CA53_MAX_OFFSET 0x141000 3425#define CA53_SECTION 0x400000 3426#define mmPCI_ROM_TABLE_BASE 0x7FFEC00000ull 3427#define PCI_ROM_TABLE_MAX_OFFSET 0x1000 3428#define PCI_ROM_TABLE_SECTION 0x1000 3429#define mmPCIE_STM_BASE 0x7FFEC01000ull 3430#define PCIE_STM_MAX_OFFSET 0x1000 3431#define PCIE_STM_SECTION 0x1000 3432#define mmPCIE_ETF_BASE 0x7FFEC02000ull 3433#define PCIE_ETF_MAX_OFFSET 0x1000 3434#define PCIE_ETF_SECTION 0x1000 3435#define mmPCIE_CTI_0_BASE 0x7FFEC03000ull 3436#define PCIE_CTI_0_MAX_OFFSET 0x1000 3437#define PCIE_CTI_0_SECTION 0x1000 3438#define mmPCIE_SPMU_BASE 0x7FFEC04000ull 3439#define PCIE_SPMU_MAX_OFFSET 0x1000 3440#define PCIE_SPMU_SECTION 0x1000 3441#define mmPCIE_CTI_1_BASE 0x7FFEC05000ull 3442#define PCIE_CTI_1_MAX_OFFSET 0x1000 3443#define PCIE_CTI_1_SECTION 0x1000 3444#define mmPCIE_FUNNEL_BASE 0x7FFEC06000ull 3445#define PCIE_FUNNEL_MAX_OFFSET 0x1000 3446#define PCIE_FUNNEL_SECTION 0x1000 3447#define mmPCIE_BMON_MSTR_WR_BASE 0x7FFEC07000ull 3448#define PCIE_BMON_MSTR_WR_MAX_OFFSET 0x1000 3449#define PCIE_BMON_MSTR_WR_SECTION 0x1000 3450#define mmPCIE_BMON_MSTR_RD_BASE 0x7FFEC08000ull 3451#define PCIE_BMON_MSTR_RD_MAX_OFFSET 0x1000 3452#define PCIE_BMON_MSTR_RD_SECTION 0x1000 3453#define mmPCIE_BMON_SLV_WR_BASE 0x7FFEC09000ull 3454#define PCIE_BMON_SLV_WR_MAX_OFFSET 0x1000 3455#define PCIE_BMON_SLV_WR_SECTION 0x1000 3456#define mmPCIE_BMON_SLV_RD_BASE 0x7FFEC0A000ull 3457#define PCIE_BMON_SLV_RD_MAX_OFFSET 0x1000 3458#define PCIE_BMON_SLV_RD_SECTION 0x7000 3459#define mmMMU_CS_STM_BASE 0x7FFEC11000ull 3460#define MMU_CS_STM_MAX_OFFSET 0x1000 3461#define MMU_CS_STM_SECTION 0x1000 3462#define mmMMU_CS_CTI_BASE 0x7FFEC12000ull 3463#define MMU_CS_CTI_MAX_OFFSET 0x1000 3464#define MMU_CS_CTI_SECTION 0x1000 3465#define mmMMU_CS_ETF_BASE 0x7FFEC13000ull 3466#define MMU_CS_ETF_MAX_OFFSET 0x1000 3467#define MMU_CS_ETF_SECTION 0x1000 3468#define mmMMU_CS_SPMU_BASE 0x7FFEC14000ull 3469#define MMU_CS_SPMU_MAX_OFFSET 0x1000 3470#define MMU_CS_SPMU_SECTION 0x1000 3471#define mmMMU_BMON_CTI_BASE 0x7FFEC15000ull 3472#define MMU_BMON_CTI_MAX_OFFSET 0x1000 3473#define MMU_BMON_CTI_SECTION 0x1000 3474#define mmMMU_USER_CTI_BASE 0x7FFEC16000ull 3475#define MMU_USER_CTI_MAX_OFFSET 0x1000 3476#define MMU_USER_CTI_SECTION 0x1000 3477#define mmMMU_BMON_0_BASE 0x7FFEC17000ull 3478#define MMU_BMON_0_MAX_OFFSET 0x1000 3479#define MMU_BMON_0_SECTION 0x1000 3480#define mmMMU_BMON_1_BASE 0x7FFEC18000ull 3481#define MMU_BMON_1_MAX_OFFSET 0x1000 3482#define MMU_BMON_1_SECTION 0x28000 3483#define mmPSOC_CTI_BASE 0x7FFEC40000ull 3484#define PSOC_CTI_MAX_OFFSET 0x1000 3485#define PSOC_CTI_SECTION 0x1000 3486#define mmPSOC_STM_BASE 0x7FFEC41000ull 3487#define PSOC_STM_MAX_OFFSET 0x1000 3488#define PSOC_STM_SECTION 0x1000 3489#define mmPSOC_FUNNEL_BASE 0x7FFEC42000ull 3490#define PSOC_FUNNEL_MAX_OFFSET 0x1000 3491#define PSOC_FUNNEL_SECTION 0x1000 3492#define mmPSOC_ETR_BASE 0x7FFEC43000ull 3493#define PSOC_ETR_MAX_OFFSET 0x1000 3494#define PSOC_ETR_SECTION 0x1000 3495#define mmPSOC_ETF_BASE 0x7FFEC44000ull 3496#define PSOC_ETF_MAX_OFFSET 0x1000 3497#define PSOC_ETF_SECTION 0x1000 3498#define mmPSOC_TS_CTI_BASE 0x7FFEC45000ull 3499#define PSOC_TS_CTI_MAX_OFFSET 0x1000 3500#define PSOC_TS_CTI_SECTION 0xB000 3501#define mmTOP_ROM_TABLE_BASE 0x7FFEC50000ull 3502#define TOP_ROM_TABLE_MAX_OFFSET 0x1000 3503#define TOP_ROM_TABLE_SECTION 0x70000 3504#define mmNIC0_ROM_TABLE_BASE 0x7FFECC0000ull 3505#define NIC0_ROM_TABLE_MAX_OFFSET 0x1000 3506#define NIC0_ROM_TABLE_SECTION 0x1000 3507#define mmSTM_0_NIC0_DBG_BASE 0x7FFECC1000ull 3508#define STM_0_NIC0_DBG_MAX_OFFSET 0x21000 3509#define STM_0_NIC0_DBG_SECTION 0x1000 3510#define mmCTI_0_NIC0_DBG_BASE 0x7FFECC2000ull 3511#define CTI_0_NIC0_DBG_MAX_OFFSET 0x1000 3512#define CTI_0_NIC0_DBG_SECTION 0x1000 3513#define mmETF_0_NIC0_DBG_BASE 0x7FFECC3000ull 3514#define ETF_0_NIC0_DBG_MAX_OFFSET 0x1000 3515#define ETF_0_NIC0_DBG_SECTION 0x1000 3516#define mmSPMU_0_NIC0_DBG_BASE 0x7FFECC4000ull 3517#define SPMU_0_NIC0_DBG_MAX_OFFSET 0x1000 3518#define SPMU_0_NIC0_DBG_SECTION 0x2000 3519#define mmUSER_CTI_0_NIC0_DBG_BASE 0x7FFECC6000ull 3520#define USER_CTI_0_NIC0_DBG_MAX_OFFSET 0x1000 3521#define USER_CTI_0_NIC0_DBG_SECTION 0xB000 3522#define mmSTM_1_NIC0_DBG_BASE 0x7FFECD1000ull 3523#define STM_1_NIC0_DBG_MAX_OFFSET 0x1000 3524#define STM_1_NIC0_DBG_SECTION 0x1000 3525#define mmCTI_1_NIC0_DBG_BASE 0x7FFECD2000ull 3526#define CTI_1_NIC0_DBG_MAX_OFFSET 0x1000 3527#define CTI_1_NIC0_DBG_SECTION 0x1000 3528#define mmETF_1_NIC0_DBG_BASE 0x7FFECD3000ull 3529#define ETF_1_NIC0_DBG_MAX_OFFSET 0x1000 3530#define ETF_1_NIC0_DBG_SECTION 0x1000 3531#define mmSPMU_1_NIC0_DBG_BASE 0x7FFECD4000ull 3532#define SPMU_1_NIC0_DBG_MAX_OFFSET 0x1000 3533#define SPMU_1_NIC0_DBG_SECTION 0x1000 3534#define mmBMON_CTI_NIC0_DBG_BASE 0x7FFECD5000ull 3535#define BMON_CTI_NIC0_DBG_MAX_OFFSET 0x1000 3536#define BMON_CTI_NIC0_DBG_SECTION 0x1000 3537#define mmUSER_CTI_1_NIC0_DBG_BASE 0x7FFECD6000ull 3538#define USER_CTI_1_NIC0_DBG_MAX_OFFSET 0x1000 3539#define USER_CTI_1_NIC0_DBG_SECTION 0x1000 3540#define mmBMON0_NIC0_DBG_BASE 0x7FFECD7000ull 3541#define BMON0_NIC0_DBG_MAX_OFFSET 0x1000 3542#define BMON0_NIC0_DBG_SECTION 0x1000 3543#define mmBMON1_NIC0_DBG_BASE 0x7FFECD8000ull 3544#define BMON1_NIC0_DBG_MAX_OFFSET 0x1000 3545#define BMON1_NIC0_DBG_SECTION 0x1000 3546#define mmBMON2_NIC0_DBG_BASE 0x7FFECD9000ull 3547#define BMON2_NIC0_DBG_MAX_OFFSET 0x1000 3548#define BMON2_NIC0_DBG_SECTION 0x1000 3549#define mmBMON3_NIC0_DBG_BASE 0x7FFECDA000ull 3550#define BMON3_NIC0_DBG_MAX_OFFSET 0x1000 3551#define BMON3_NIC0_DBG_SECTION 0x1000 3552#define mmBMON4_NIC0_DBG_BASE 0x7FFECDB000ull 3553#define BMON4_NIC0_DBG_MAX_OFFSET 0x1000 3554#define BMON4_NIC0_DBG_SECTION 0x6000 3555#define mmFUNNEL_NIC0_DBG_BASE 0x7FFECE1000ull 3556#define FUNNEL_NIC0_DBG_MAX_OFFSET 0x1000 3557#define FUNNEL_NIC0_DBG_SECTION 0x1F000 3558#define mmNIC1_ROM_TABLE_BASE 0x7FFED00000ull 3559#define NIC1_ROM_TABLE_MAX_OFFSET 0x1000 3560#define NIC1_ROM_TABLE_SECTION 0x1000 3561#define mmSTM_0_NIC1_DBG_BASE 0x7FFED01000ull 3562#define STM_0_NIC1_DBG_MAX_OFFSET 0x21000 3563#define STM_0_NIC1_DBG_SECTION 0x1000 3564#define mmCTI_0_NIC1_DBG_BASE 0x7FFED02000ull 3565#define CTI_0_NIC1_DBG_MAX_OFFSET 0x1000 3566#define CTI_0_NIC1_DBG_SECTION 0x1000 3567#define mmETF_0_NIC1_DBG_BASE 0x7FFED03000ull 3568#define ETF_0_NIC1_DBG_MAX_OFFSET 0x1000 3569#define ETF_0_NIC1_DBG_SECTION 0x1000 3570#define mmSPMU_0_NIC1_DBG_BASE 0x7FFED04000ull 3571#define SPMU_0_NIC1_DBG_MAX_OFFSET 0x1000 3572#define SPMU_0_NIC1_DBG_SECTION 0x2000 3573#define mmUSER_CTI_0_NIC1_DBG_BASE 0x7FFED06000ull 3574#define USER_CTI_0_NIC1_DBG_MAX_OFFSET 0x1000 3575#define USER_CTI_0_NIC1_DBG_SECTION 0xB000 3576#define mmSTM_1_NIC1_DBG_BASE 0x7FFED11000ull 3577#define STM_1_NIC1_DBG_MAX_OFFSET 0x1000 3578#define STM_1_NIC1_DBG_SECTION 0x1000 3579#define mmCTI_1_NIC1_DBG_BASE 0x7FFED12000ull 3580#define CTI_1_NIC1_DBG_MAX_OFFSET 0x1000 3581#define CTI_1_NIC1_DBG_SECTION 0x1000 3582#define mmETF_1_NIC1_DBG_BASE 0x7FFED13000ull 3583#define ETF_1_NIC1_DBG_MAX_OFFSET 0x1000 3584#define ETF_1_NIC1_DBG_SECTION 0x1000 3585#define mmSPMU_1_NIC1_DBG_BASE 0x7FFED14000ull 3586#define SPMU_1_NIC1_DBG_MAX_OFFSET 0x1000 3587#define SPMU_1_NIC1_DBG_SECTION 0x1000 3588#define mmBMON_CTI_NIC1_DBG_BASE 0x7FFED15000ull 3589#define BMON_CTI_NIC1_DBG_MAX_OFFSET 0x1000 3590#define BMON_CTI_NIC1_DBG_SECTION 0x1000 3591#define mmUSER_CTI_1_NIC1_DBG_BASE 0x7FFED16000ull 3592#define USER_CTI_1_NIC1_DBG_MAX_OFFSET 0x1000 3593#define USER_CTI_1_NIC1_DBG_SECTION 0x1000 3594#define mmBMON0_NIC1_DBG_BASE 0x7FFED17000ull 3595#define BMON0_NIC1_DBG_MAX_OFFSET 0x1000 3596#define BMON0_NIC1_DBG_SECTION 0x1000 3597#define mmBMON1_NIC1_DBG_BASE 0x7FFED18000ull 3598#define BMON1_NIC1_DBG_MAX_OFFSET 0x1000 3599#define BMON1_NIC1_DBG_SECTION 0x1000 3600#define mmBMON2_NIC1_DBG_BASE 0x7FFED19000ull 3601#define BMON2_NIC1_DBG_MAX_OFFSET 0x1000 3602#define BMON2_NIC1_DBG_SECTION 0x1000 3603#define mmBMON3_NIC1_DBG_BASE 0x7FFED1A000ull 3604#define BMON3_NIC1_DBG_MAX_OFFSET 0x1000 3605#define BMON3_NIC1_DBG_SECTION 0x1000 3606#define mmBMON4_NIC1_DBG_BASE 0x7FFED1B000ull 3607#define BMON4_NIC1_DBG_MAX_OFFSET 0x1000 3608#define BMON4_NIC1_DBG_SECTION 0x6000 3609#define mmFUNNEL_NIC1_DBG_BASE 0x7FFED21000ull 3610#define FUNNEL_NIC1_DBG_MAX_OFFSET 0x1000 3611#define FUNNEL_NIC1_DBG_SECTION 0x1F000 3612#define mmNIC2_ROM_TABLE_BASE 0x7FFED40000ull 3613#define NIC2_ROM_TABLE_MAX_OFFSET 0x1000 3614#define NIC2_ROM_TABLE_SECTION 0x1000 3615#define mmSTM_0_NIC2_DBG_BASE 0x7FFED41000ull 3616#define STM_0_NIC2_DBG_MAX_OFFSET 0x21000 3617#define STM_0_NIC2_DBG_SECTION 0x1000 3618#define mmCTI_0_NIC2_DBG_BASE 0x7FFED42000ull 3619#define CTI_0_NIC2_DBG_MAX_OFFSET 0x1000 3620#define CTI_0_NIC2_DBG_SECTION 0x1000 3621#define mmETF_0_NIC2_DBG_BASE 0x7FFED43000ull 3622#define ETF_0_NIC2_DBG_MAX_OFFSET 0x1000 3623#define ETF_0_NIC2_DBG_SECTION 0x1000 3624#define mmSPMU_0_NIC2_DBG_BASE 0x7FFED44000ull 3625#define SPMU_0_NIC2_DBG_MAX_OFFSET 0x1000 3626#define SPMU_0_NIC2_DBG_SECTION 0x2000 3627#define mmUSER_CTI_0_NIC2_DBG_BASE 0x7FFED46000ull 3628#define USER_CTI_0_NIC2_DBG_MAX_OFFSET 0x1000 3629#define USER_CTI_0_NIC2_DBG_SECTION 0xB000 3630#define mmSTM_1_NIC2_DBG_BASE 0x7FFED51000ull 3631#define STM_1_NIC2_DBG_MAX_OFFSET 0x1000 3632#define STM_1_NIC2_DBG_SECTION 0x1000 3633#define mmCTI_1_NIC2_DBG_BASE 0x7FFED52000ull 3634#define CTI_1_NIC2_DBG_MAX_OFFSET 0x1000 3635#define CTI_1_NIC2_DBG_SECTION 0x1000 3636#define mmETF_1_NIC2_DBG_BASE 0x7FFED53000ull 3637#define ETF_1_NIC2_DBG_MAX_OFFSET 0x1000 3638#define ETF_1_NIC2_DBG_SECTION 0x1000 3639#define mmSPMU_1_NIC2_DBG_BASE 0x7FFED54000ull 3640#define SPMU_1_NIC2_DBG_MAX_OFFSET 0x1000 3641#define SPMU_1_NIC2_DBG_SECTION 0x1000 3642#define mmBMON_CTI_NIC2_DBG_BASE 0x7FFED55000ull 3643#define BMON_CTI_NIC2_DBG_MAX_OFFSET 0x1000 3644#define BMON_CTI_NIC2_DBG_SECTION 0x1000 3645#define mmUSER_CTI_1_NIC2_DBG_BASE 0x7FFED56000ull 3646#define USER_CTI_1_NIC2_DBG_MAX_OFFSET 0x1000 3647#define USER_CTI_1_NIC2_DBG_SECTION 0x1000 3648#define mmBMON0_NIC2_DBG_BASE 0x7FFED57000ull 3649#define BMON0_NIC2_DBG_MAX_OFFSET 0x1000 3650#define BMON0_NIC2_DBG_SECTION 0x1000 3651#define mmBMON1_NIC2_DBG_BASE 0x7FFED58000ull 3652#define BMON1_NIC2_DBG_MAX_OFFSET 0x1000 3653#define BMON1_NIC2_DBG_SECTION 0x1000 3654#define mmBMON2_NIC2_DBG_BASE 0x7FFED59000ull 3655#define BMON2_NIC2_DBG_MAX_OFFSET 0x1000 3656#define BMON2_NIC2_DBG_SECTION 0x1000 3657#define mmBMON3_NIC2_DBG_BASE 0x7FFED5A000ull 3658#define BMON3_NIC2_DBG_MAX_OFFSET 0x1000 3659#define BMON3_NIC2_DBG_SECTION 0x1000 3660#define mmBMON4_NIC2_DBG_BASE 0x7FFED5B000ull 3661#define BMON4_NIC2_DBG_MAX_OFFSET 0x1000 3662#define BMON4_NIC2_DBG_SECTION 0x6000 3663#define mmFUNNEL_NIC2_DBG_BASE 0x7FFED61000ull 3664#define FUNNEL_NIC2_DBG_MAX_OFFSET 0x1000 3665#define FUNNEL_NIC2_DBG_SECTION 0x1F000 3666#define mmNIC3_ROM_TABLE_BASE 0x7FFED80000ull 3667#define NIC3_ROM_TABLE_MAX_OFFSET 0x1000 3668#define NIC3_ROM_TABLE_SECTION 0x1000 3669#define mmSTM_0_NIC3_DBG_BASE 0x7FFED81000ull 3670#define STM_0_NIC3_DBG_MAX_OFFSET 0x21000 3671#define STM_0_NIC3_DBG_SECTION 0x1000 3672#define mmCTI_0_NIC3_DBG_BASE 0x7FFED82000ull 3673#define CTI_0_NIC3_DBG_MAX_OFFSET 0x1000 3674#define CTI_0_NIC3_DBG_SECTION 0x1000 3675#define mmETF_0_NIC3_DBG_BASE 0x7FFED83000ull 3676#define ETF_0_NIC3_DBG_MAX_OFFSET 0x1000 3677#define ETF_0_NIC3_DBG_SECTION 0x1000 3678#define mmSPMU_0_NIC3_DBG_BASE 0x7FFED84000ull 3679#define SPMU_0_NIC3_DBG_MAX_OFFSET 0x1000 3680#define SPMU_0_NIC3_DBG_SECTION 0x2000 3681#define mmUSER_CTI_0_NIC3_DBG_BASE 0x7FFED86000ull 3682#define USER_CTI_0_NIC3_DBG_MAX_OFFSET 0x1000 3683#define USER_CTI_0_NIC3_DBG_SECTION 0xB000 3684#define mmSTM_1_NIC3_DBG_BASE 0x7FFED91000ull 3685#define STM_1_NIC3_DBG_MAX_OFFSET 0x1000 3686#define STM_1_NIC3_DBG_SECTION 0x1000 3687#define mmCTI_1_NIC3_DBG_BASE 0x7FFED92000ull 3688#define CTI_1_NIC3_DBG_MAX_OFFSET 0x1000 3689#define CTI_1_NIC3_DBG_SECTION 0x1000 3690#define mmETF_1_NIC3_DBG_BASE 0x7FFED93000ull 3691#define ETF_1_NIC3_DBG_MAX_OFFSET 0x1000 3692#define ETF_1_NIC3_DBG_SECTION 0x1000 3693#define mmSPMU_1_NIC3_DBG_BASE 0x7FFED94000ull 3694#define SPMU_1_NIC3_DBG_MAX_OFFSET 0x1000 3695#define SPMU_1_NIC3_DBG_SECTION 0x1000 3696#define mmBMON_CTI_NIC3_DBG_BASE 0x7FFED95000ull 3697#define BMON_CTI_NIC3_DBG_MAX_OFFSET 0x1000 3698#define BMON_CTI_NIC3_DBG_SECTION 0x1000 3699#define mmUSER_CTI_1_NIC3_DBG_BASE 0x7FFED96000ull 3700#define USER_CTI_1_NIC3_DBG_MAX_OFFSET 0x1000 3701#define USER_CTI_1_NIC3_DBG_SECTION 0x1000 3702#define mmBMON0_NIC3_DBG_BASE 0x7FFED97000ull 3703#define BMON0_NIC3_DBG_MAX_OFFSET 0x1000 3704#define BMON0_NIC3_DBG_SECTION 0x1000 3705#define mmBMON1_NIC3_DBG_BASE 0x7FFED98000ull 3706#define BMON1_NIC3_DBG_MAX_OFFSET 0x1000 3707#define BMON1_NIC3_DBG_SECTION 0x1000 3708#define mmBMON2_NIC3_DBG_BASE 0x7FFED99000ull 3709#define BMON2_NIC3_DBG_MAX_OFFSET 0x1000 3710#define BMON2_NIC3_DBG_SECTION 0x1000 3711#define mmBMON3_NIC3_DBG_BASE 0x7FFED9A000ull 3712#define BMON3_NIC3_DBG_MAX_OFFSET 0x1000 3713#define BMON3_NIC3_DBG_SECTION 0x1000 3714#define mmBMON4_NIC3_DBG_BASE 0x7FFED9B000ull 3715#define BMON4_NIC3_DBG_MAX_OFFSET 0x1000 3716#define BMON4_NIC3_DBG_SECTION 0x6000 3717#define mmFUNNEL_NIC3_DBG_BASE 0x7FFEDA1000ull 3718#define FUNNEL_NIC3_DBG_MAX_OFFSET 0x1000 3719#define FUNNEL_NIC3_DBG_SECTION 0x1F000 3720#define mmNIC4_ROM_TABLE_BASE 0x7FFEDC0000ull 3721#define NIC4_ROM_TABLE_MAX_OFFSET 0x1000 3722#define NIC4_ROM_TABLE_SECTION 0x1000 3723#define mmSTM_0_NIC4_DBG_BASE 0x7FFEDC1000ull 3724#define STM_0_NIC4_DBG_MAX_OFFSET 0x21000 3725#define STM_0_NIC4_DBG_SECTION 0x1000 3726#define mmCTI_0_NIC4_DBG_BASE 0x7FFEDC2000ull 3727#define CTI_0_NIC4_DBG_MAX_OFFSET 0x1000 3728#define CTI_0_NIC4_DBG_SECTION 0x1000 3729#define mmETF_0_NIC4_DBG_BASE 0x7FFEDC3000ull 3730#define ETF_0_NIC4_DBG_MAX_OFFSET 0x1000 3731#define ETF_0_NIC4_DBG_SECTION 0x1000 3732#define mmSPMU_0_NIC4_DBG_BASE 0x7FFEDC4000ull 3733#define SPMU_0_NIC4_DBG_MAX_OFFSET 0x1000 3734#define SPMU_0_NIC4_DBG_SECTION 0x2000 3735#define mmUSER_CTI_0_NIC4_DBG_BASE 0x7FFEDC6000ull 3736#define USER_CTI_0_NIC4_DBG_MAX_OFFSET 0x1000 3737#define USER_CTI_0_NIC4_DBG_SECTION 0xB000 3738#define mmSTM_1_NIC4_DBG_BASE 0x7FFEDD1000ull 3739#define STM_1_NIC4_DBG_MAX_OFFSET 0x1000 3740#define STM_1_NIC4_DBG_SECTION 0x1000 3741#define mmCTI_1_NIC4_DBG_BASE 0x7FFEDD2000ull 3742#define CTI_1_NIC4_DBG_MAX_OFFSET 0x1000 3743#define CTI_1_NIC4_DBG_SECTION 0x1000 3744#define mmETF_1_NIC4_DBG_BASE 0x7FFEDD3000ull 3745#define ETF_1_NIC4_DBG_MAX_OFFSET 0x1000 3746#define ETF_1_NIC4_DBG_SECTION 0x1000 3747#define mmSPMU_1_NIC4_DBG_BASE 0x7FFEDD4000ull 3748#define SPMU_1_NIC4_DBG_MAX_OFFSET 0x1000 3749#define SPMU_1_NIC4_DBG_SECTION 0x1000 3750#define mmBMON_CTI_NIC4_DBG_BASE 0x7FFEDD5000ull 3751#define BMON_CTI_NIC4_DBG_MAX_OFFSET 0x1000 3752#define BMON_CTI_NIC4_DBG_SECTION 0x1000 3753#define mmUSER_CTI_1_NIC4_DBG_BASE 0x7FFEDD6000ull 3754#define USER_CTI_1_NIC4_DBG_MAX_OFFSET 0x1000 3755#define USER_CTI_1_NIC4_DBG_SECTION 0x1000 3756#define mmBMON0_NIC4_DBG_BASE 0x7FFEDD7000ull 3757#define BMON0_NIC4_DBG_MAX_OFFSET 0x1000 3758#define BMON0_NIC4_DBG_SECTION 0x1000 3759#define mmBMON1_NIC4_DBG_BASE 0x7FFEDD8000ull 3760#define BMON1_NIC4_DBG_MAX_OFFSET 0x1000 3761#define BMON1_NIC4_DBG_SECTION 0x1000 3762#define mmBMON2_NIC4_DBG_BASE 0x7FFEDD9000ull 3763#define BMON2_NIC4_DBG_MAX_OFFSET 0x1000 3764#define BMON2_NIC4_DBG_SECTION 0x1000 3765#define mmBMON3_NIC4_DBG_BASE 0x7FFEDDA000ull 3766#define BMON3_NIC4_DBG_MAX_OFFSET 0x1000 3767#define BMON3_NIC4_DBG_SECTION 0x1000 3768#define mmBMON4_NIC4_DBG_BASE 0x7FFEDDB000ull 3769#define BMON4_NIC4_DBG_MAX_OFFSET 0x1000 3770#define BMON4_NIC4_DBG_SECTION 0x6000 3771#define mmFUNNEL_NIC4_DBG_BASE 0x7FFEDE1000ull 3772#define FUNNEL_NIC4_DBG_MAX_OFFSET 0x1000 3773#define FUNNEL_NIC4_DBG_SECTION 0x21F000 3774#define mmTPC0_ROM_TABLE_BASE 0x7FFF000000ull 3775#define TPC0_ROM_TABLE_MAX_OFFSET 0x1000 3776#define TPC0_ROM_TABLE_SECTION 0x1000 3777#define mmTPC0_EML_SPMU_BASE 0x7FFF001000ull 3778#define TPC0_EML_SPMU_MAX_OFFSET 0x1000 3779#define TPC0_EML_SPMU_SECTION 0x1000 3780#define mmTPC0_EML_ETF_BASE 0x7FFF002000ull 3781#define TPC0_EML_ETF_MAX_OFFSET 0x1000 3782#define TPC0_EML_ETF_SECTION 0x1000 3783#define mmTPC0_EML_STM_BASE 0x7FFF003000ull 3784#define TPC0_EML_STM_MAX_OFFSET 0x1000 3785#define TPC0_EML_STM_SECTION 0x2000 3786#define mmTPC0_EML_CTI_BASE 0x7FFF005000ull 3787#define TPC0_EML_CTI_MAX_OFFSET 0x1000 3788#define TPC0_EML_CTI_SECTION 0x1000 3789#define mmTPC0_EML_FUNNEL_BASE 0x7FFF006000ull 3790#define TPC0_EML_FUNNEL_MAX_OFFSET 0x1000 3791#define TPC0_EML_FUNNEL_SECTION 0x1000 3792#define mmTPC0_EML_BUSMON_0_BASE 0x7FFF007000ull 3793#define TPC0_EML_BUSMON_0_MAX_OFFSET 0x1000 3794#define TPC0_EML_BUSMON_0_SECTION 0x1000 3795#define mmTPC0_EML_BUSMON_1_BASE 0x7FFF008000ull 3796#define TPC0_EML_BUSMON_1_MAX_OFFSET 0x1000 3797#define TPC0_EML_BUSMON_1_SECTION 0x1000 3798#define mmTPC0_EML_BUSMON_2_BASE 0x7FFF009000ull 3799#define TPC0_EML_BUSMON_2_MAX_OFFSET 0x1000 3800#define TPC0_EML_BUSMON_2_SECTION 0x1000 3801#define mmTPC0_EML_BUSMON_3_BASE 0x7FFF00A000ull 3802#define TPC0_EML_BUSMON_3_MAX_OFFSET 0x1000 3803#define TPC0_EML_BUSMON_3_SECTION 0x36000 3804#define mmTPC0_EML_CFG_BASE 0x7FFF040000ull 3805#define TPC0_EML_CFG_MAX_OFFSET 0x3380 3806#define TPC0_EML_CFG_SECTION 0x1000 3807#define mmTPC0_EML_TPC_CFG_BASE 0x7FFF041000ull 3808#define TPC0_EML_TPC_CFG_MAX_OFFSET 0xE400 3809#define TPC0_EML_TPC_CFG_SECTION 0x4000 3810#define mmKERNEL_TENSOR_0_TPC0_EML_TPC_CFG_BASE 0x7FFF041400ull 3811#define KERNEL_TENSOR_0_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3812#define KERNEL_TENSOR_0_TPC0_EML_TPC_CFG_SECTION 0x3800 3813#define mmKERNEL_TENSOR_1_TPC0_EML_TPC_CFG_BASE 0x7FFF041438ull 3814#define KERNEL_TENSOR_1_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3815#define KERNEL_TENSOR_1_TPC0_EML_TPC_CFG_SECTION 0x3800 3816#define mmKERNEL_TENSOR_2_TPC0_EML_TPC_CFG_BASE 0x7FFF041470ull 3817#define KERNEL_TENSOR_2_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3818#define KERNEL_TENSOR_2_TPC0_EML_TPC_CFG_SECTION 0x3800 3819#define mmKERNEL_TENSOR_3_TPC0_EML_TPC_CFG_BASE 0x7FFF0414A8ull 3820#define KERNEL_TENSOR_3_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3821#define KERNEL_TENSOR_3_TPC0_EML_TPC_CFG_SECTION 0x3800 3822#define mmKERNEL_TENSOR_4_TPC0_EML_TPC_CFG_BASE 0x7FFF0414E0ull 3823#define KERNEL_TENSOR_4_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3824#define KERNEL_TENSOR_4_TPC0_EML_TPC_CFG_SECTION 0x3800 3825#define mmKERNEL_TENSOR_5_TPC0_EML_TPC_CFG_BASE 0x7FFF041518ull 3826#define KERNEL_TENSOR_5_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3827#define KERNEL_TENSOR_5_TPC0_EML_TPC_CFG_SECTION 0x3800 3828#define mmKERNEL_TENSOR_6_TPC0_EML_TPC_CFG_BASE 0x7FFF041550ull 3829#define KERNEL_TENSOR_6_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3830#define KERNEL_TENSOR_6_TPC0_EML_TPC_CFG_SECTION 0x3800 3831#define mmKERNEL_TENSOR_7_TPC0_EML_TPC_CFG_BASE 0x7FFF041588ull 3832#define KERNEL_TENSOR_7_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3833#define KERNEL_TENSOR_7_TPC0_EML_TPC_CFG_SECTION 0x3800 3834#define mmKERNEL_TENSOR_8_TPC0_EML_TPC_CFG_BASE 0x7FFF0415C0ull 3835#define KERNEL_TENSOR_8_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3836#define KERNEL_TENSOR_8_TPC0_EML_TPC_CFG_SECTION 0x3800 3837#define mmKERNEL_TENSOR_9_TPC0_EML_TPC_CFG_BASE 0x7FFF0415F8ull 3838#define KERNEL_TENSOR_9_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3839#define KERNEL_TENSOR_9_TPC0_EML_TPC_CFG_SECTION 0x3800 3840#define mmKERNEL_TENSOR_10_TPC0_EML_TPC_CFG_BASE 0x7FFF041630ull 3841#define KERNEL_TENSOR_10_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3842#define KERNEL_TENSOR_10_TPC0_EML_TPC_CFG_SECTION 0x3800 3843#define mmKERNEL_TENSOR_11_TPC0_EML_TPC_CFG_BASE 0x7FFF041668ull 3844#define KERNEL_TENSOR_11_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3845#define KERNEL_TENSOR_11_TPC0_EML_TPC_CFG_SECTION 0x3800 3846#define mmKERNEL_TENSOR_12_TPC0_EML_TPC_CFG_BASE 0x7FFF0416A0ull 3847#define KERNEL_TENSOR_12_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3848#define KERNEL_TENSOR_12_TPC0_EML_TPC_CFG_SECTION 0x3800 3849#define mmKERNEL_TENSOR_13_TPC0_EML_TPC_CFG_BASE 0x7FFF0416D8ull 3850#define KERNEL_TENSOR_13_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3851#define KERNEL_TENSOR_13_TPC0_EML_TPC_CFG_SECTION 0x3800 3852#define mmKERNEL_TENSOR_14_TPC0_EML_TPC_CFG_BASE 0x7FFF041710ull 3853#define KERNEL_TENSOR_14_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3854#define KERNEL_TENSOR_14_TPC0_EML_TPC_CFG_SECTION 0x3800 3855#define mmKERNEL_TENSOR_15_TPC0_EML_TPC_CFG_BASE 0x7FFF041748ull 3856#define KERNEL_TENSOR_15_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3857#define KERNEL_TENSOR_15_TPC0_EML_TPC_CFG_SECTION 0x3800 3858#define mmKERNEL_SYNC_OBJECT_TPC0_EML_TPC_CFG_BASE 0x7FFF041780ull 3859#define KERNEL_SYNC_OBJECT_TPC0_EML_TPC_CFG_MAX_OFFSET 0x8000 3860#define KERNEL_SYNC_OBJECT_TPC0_EML_TPC_CFG_SECTION 0x8000 3861#define mmKERNEL_TPC0_EML_TPC_CFG_BASE 0x7FFF041788ull 3862#define KERNEL_TPC0_EML_TPC_CFG_MAX_OFFSET 0xB800 3863#define KERNEL_TPC0_EML_TPC_CFG_SECTION 0x2780 3864#define mmQM_TENSOR_0_TPC0_EML_TPC_CFG_BASE 0x7FFF041A00ull 3865#define QM_TENSOR_0_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3866#define QM_TENSOR_0_TPC0_EML_TPC_CFG_SECTION 0x3800 3867#define mmQM_TENSOR_1_TPC0_EML_TPC_CFG_BASE 0x7FFF041A38ull 3868#define QM_TENSOR_1_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3869#define QM_TENSOR_1_TPC0_EML_TPC_CFG_SECTION 0x3800 3870#define mmQM_TENSOR_2_TPC0_EML_TPC_CFG_BASE 0x7FFF041A70ull 3871#define QM_TENSOR_2_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3872#define QM_TENSOR_2_TPC0_EML_TPC_CFG_SECTION 0x3800 3873#define mmQM_TENSOR_3_TPC0_EML_TPC_CFG_BASE 0x7FFF041AA8ull 3874#define QM_TENSOR_3_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3875#define QM_TENSOR_3_TPC0_EML_TPC_CFG_SECTION 0x3800 3876#define mmQM_TENSOR_4_TPC0_EML_TPC_CFG_BASE 0x7FFF041AE0ull 3877#define QM_TENSOR_4_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3878#define QM_TENSOR_4_TPC0_EML_TPC_CFG_SECTION 0x3800 3879#define mmQM_TENSOR_5_TPC0_EML_TPC_CFG_BASE 0x7FFF041B18ull 3880#define QM_TENSOR_5_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3881#define QM_TENSOR_5_TPC0_EML_TPC_CFG_SECTION 0x3800 3882#define mmQM_TENSOR_6_TPC0_EML_TPC_CFG_BASE 0x7FFF041B50ull 3883#define QM_TENSOR_6_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3884#define QM_TENSOR_6_TPC0_EML_TPC_CFG_SECTION 0x3800 3885#define mmQM_TENSOR_7_TPC0_EML_TPC_CFG_BASE 0x7FFF041B88ull 3886#define QM_TENSOR_7_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3887#define QM_TENSOR_7_TPC0_EML_TPC_CFG_SECTION 0x3800 3888#define mmQM_TENSOR_8_TPC0_EML_TPC_CFG_BASE 0x7FFF041BC0ull 3889#define QM_TENSOR_8_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3890#define QM_TENSOR_8_TPC0_EML_TPC_CFG_SECTION 0x3800 3891#define mmQM_TENSOR_9_TPC0_EML_TPC_CFG_BASE 0x7FFF041BF8ull 3892#define QM_TENSOR_9_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3893#define QM_TENSOR_9_TPC0_EML_TPC_CFG_SECTION 0x3800 3894#define mmQM_TENSOR_10_TPC0_EML_TPC_CFG_BASE 0x7FFF041C30ull 3895#define QM_TENSOR_10_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3896#define QM_TENSOR_10_TPC0_EML_TPC_CFG_SECTION 0x3800 3897#define mmQM_TENSOR_11_TPC0_EML_TPC_CFG_BASE 0x7FFF041C68ull 3898#define QM_TENSOR_11_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3899#define QM_TENSOR_11_TPC0_EML_TPC_CFG_SECTION 0x3800 3900#define mmQM_TENSOR_12_TPC0_EML_TPC_CFG_BASE 0x7FFF041CA0ull 3901#define QM_TENSOR_12_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3902#define QM_TENSOR_12_TPC0_EML_TPC_CFG_SECTION 0x3800 3903#define mmQM_TENSOR_13_TPC0_EML_TPC_CFG_BASE 0x7FFF041CD8ull 3904#define QM_TENSOR_13_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3905#define QM_TENSOR_13_TPC0_EML_TPC_CFG_SECTION 0x3800 3906#define mmQM_TENSOR_14_TPC0_EML_TPC_CFG_BASE 0x7FFF041D10ull 3907#define QM_TENSOR_14_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3908#define QM_TENSOR_14_TPC0_EML_TPC_CFG_SECTION 0x3800 3909#define mmQM_TENSOR_15_TPC0_EML_TPC_CFG_BASE 0x7FFF041D48ull 3910#define QM_TENSOR_15_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3911#define QM_TENSOR_15_TPC0_EML_TPC_CFG_SECTION 0x3800 3912#define mmQM_SYNC_OBJECT_TPC0_EML_TPC_CFG_BASE 0x7FFF041D80ull 3913#define QM_SYNC_OBJECT_TPC0_EML_TPC_CFG_MAX_OFFSET 0x8000 3914#define QM_SYNC_OBJECT_TPC0_EML_TPC_CFG_SECTION 0x8000 3915#define mmQM_TPC0_EML_TPC_CFG_BASE 0x7FFF041D88ull 3916#define QM_TPC0_EML_TPC_CFG_MAX_OFFSET 0xB800 3917#define QM_TPC0_EML_TPC_CFG_SECTION 0x2780 3918#define mmTPC0_EML_TPC_QM_BASE 0x7FFF042000ull 3919#define TPC0_EML_TPC_QM_MAX_OFFSET 0xD040 3920#define TPC0_EML_TPC_QM_SECTION 0x1BD000 3921#define mmTPC0_EML_CS_BASE 0x7FFF1FF000ull 3922#define TPC0_EML_CS_MAX_OFFSET 0x1000 3923#define TPC0_EML_CS_SECTION 0x1000 3924#define mmTPC1_ROM_TABLE_BASE 0x7FFF200000ull 3925#define TPC1_ROM_TABLE_MAX_OFFSET 0x1000 3926#define TPC1_ROM_TABLE_SECTION 0x1000 3927#define mmTPC1_EML_SPMU_BASE 0x7FFF201000ull 3928#define TPC1_EML_SPMU_MAX_OFFSET 0x1000 3929#define TPC1_EML_SPMU_SECTION 0x1000 3930#define mmTPC1_EML_ETF_BASE 0x7FFF202000ull 3931#define TPC1_EML_ETF_MAX_OFFSET 0x1000 3932#define TPC1_EML_ETF_SECTION 0x1000 3933#define mmTPC1_EML_STM_BASE 0x7FFF203000ull 3934#define TPC1_EML_STM_MAX_OFFSET 0x1000 3935#define TPC1_EML_STM_SECTION 0x2000 3936#define mmTPC1_EML_CTI_BASE 0x7FFF205000ull 3937#define TPC1_EML_CTI_MAX_OFFSET 0x1000 3938#define TPC1_EML_CTI_SECTION 0x1000 3939#define mmTPC1_EML_FUNNEL_BASE 0x7FFF206000ull 3940#define TPC1_EML_FUNNEL_MAX_OFFSET 0x1000 3941#define TPC1_EML_FUNNEL_SECTION 0x1000 3942#define mmTPC1_EML_BUSMON_0_BASE 0x7FFF207000ull 3943#define TPC1_EML_BUSMON_0_MAX_OFFSET 0x1000 3944#define TPC1_EML_BUSMON_0_SECTION 0x1000 3945#define mmTPC1_EML_BUSMON_1_BASE 0x7FFF208000ull 3946#define TPC1_EML_BUSMON_1_MAX_OFFSET 0x1000 3947#define TPC1_EML_BUSMON_1_SECTION 0x1000 3948#define mmTPC1_EML_BUSMON_2_BASE 0x7FFF209000ull 3949#define TPC1_EML_BUSMON_2_MAX_OFFSET 0x1000 3950#define TPC1_EML_BUSMON_2_SECTION 0x1000 3951#define mmTPC1_EML_BUSMON_3_BASE 0x7FFF20A000ull 3952#define TPC1_EML_BUSMON_3_MAX_OFFSET 0x1000 3953#define TPC1_EML_BUSMON_3_SECTION 0x36000 3954#define mmTPC1_EML_CFG_BASE 0x7FFF240000ull 3955#define TPC1_EML_CFG_MAX_OFFSET 0x3380 3956#define TPC1_EML_CFG_SECTION 0x1000 3957#define mmTPC1_EML_TPC_CFG_BASE 0x7FFF241000ull 3958#define TPC1_EML_TPC_CFG_MAX_OFFSET 0xE400 3959#define TPC1_EML_TPC_CFG_SECTION 0x4000 3960#define mmKERNEL_TENSOR_0_TPC1_EML_TPC_CFG_BASE 0x7FFF241400ull 3961#define KERNEL_TENSOR_0_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 3962#define KERNEL_TENSOR_0_TPC1_EML_TPC_CFG_SECTION 0x3800 3963#define mmKERNEL_TENSOR_1_TPC1_EML_TPC_CFG_BASE 0x7FFF241438ull 3964#define KERNEL_TENSOR_1_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 3965#define KERNEL_TENSOR_1_TPC1_EML_TPC_CFG_SECTION 0x3800 3966#define mmKERNEL_TENSOR_2_TPC1_EML_TPC_CFG_BASE 0x7FFF241470ull 3967#define KERNEL_TENSOR_2_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 3968#define KERNEL_TENSOR_2_TPC1_EML_TPC_CFG_SECTION 0x3800 3969#define mmKERNEL_TENSOR_3_TPC1_EML_TPC_CFG_BASE 0x7FFF2414A8ull 3970#define KERNEL_TENSOR_3_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 3971#define KERNEL_TENSOR_3_TPC1_EML_TPC_CFG_SECTION 0x3800 3972#define mmKERNEL_TENSOR_4_TPC1_EML_TPC_CFG_BASE 0x7FFF2414E0ull 3973#define KERNEL_TENSOR_4_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 3974#define KERNEL_TENSOR_4_TPC1_EML_TPC_CFG_SECTION 0x3800 3975#define mmKERNEL_TENSOR_5_TPC1_EML_TPC_CFG_BASE 0x7FFF241518ull 3976#define KERNEL_TENSOR_5_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 3977#define KERNEL_TENSOR_5_TPC1_EML_TPC_CFG_SECTION 0x3800 3978#define mmKERNEL_TENSOR_6_TPC1_EML_TPC_CFG_BASE 0x7FFF241550ull 3979#define KERNEL_TENSOR_6_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 3980#define KERNEL_TENSOR_6_TPC1_EML_TPC_CFG_SECTION 0x3800 3981#define mmKERNEL_TENSOR_7_TPC1_EML_TPC_CFG_BASE 0x7FFF241588ull 3982#define KERNEL_TENSOR_7_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 3983#define KERNEL_TENSOR_7_TPC1_EML_TPC_CFG_SECTION 0x3800 3984#define mmKERNEL_TENSOR_8_TPC1_EML_TPC_CFG_BASE 0x7FFF2415C0ull 3985#define KERNEL_TENSOR_8_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 3986#define KERNEL_TENSOR_8_TPC1_EML_TPC_CFG_SECTION 0x3800 3987#define mmKERNEL_TENSOR_9_TPC1_EML_TPC_CFG_BASE 0x7FFF2415F8ull 3988#define KERNEL_TENSOR_9_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 3989#define KERNEL_TENSOR_9_TPC1_EML_TPC_CFG_SECTION 0x3800 3990#define mmKERNEL_TENSOR_10_TPC1_EML_TPC_CFG_BASE 0x7FFF241630ull 3991#define KERNEL_TENSOR_10_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 3992#define KERNEL_TENSOR_10_TPC1_EML_TPC_CFG_SECTION 0x3800 3993#define mmKERNEL_TENSOR_11_TPC1_EML_TPC_CFG_BASE 0x7FFF241668ull 3994#define KERNEL_TENSOR_11_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 3995#define KERNEL_TENSOR_11_TPC1_EML_TPC_CFG_SECTION 0x3800 3996#define mmKERNEL_TENSOR_12_TPC1_EML_TPC_CFG_BASE 0x7FFF2416A0ull 3997#define KERNEL_TENSOR_12_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 3998#define KERNEL_TENSOR_12_TPC1_EML_TPC_CFG_SECTION 0x3800 3999#define mmKERNEL_TENSOR_13_TPC1_EML_TPC_CFG_BASE 0x7FFF2416D8ull 4000#define KERNEL_TENSOR_13_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 4001#define KERNEL_TENSOR_13_TPC1_EML_TPC_CFG_SECTION 0x3800 4002#define mmKERNEL_TENSOR_14_TPC1_EML_TPC_CFG_BASE 0x7FFF241710ull 4003#define KERNEL_TENSOR_14_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 4004#define KERNEL_TENSOR_14_TPC1_EML_TPC_CFG_SECTION 0x3800 4005#define mmKERNEL_TENSOR_15_TPC1_EML_TPC_CFG_BASE 0x7FFF241748ull 4006#define KERNEL_TENSOR_15_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 4007#define KERNEL_TENSOR_15_TPC1_EML_TPC_CFG_SECTION 0x3800 4008#define mmKERNEL_SYNC_OBJECT_TPC1_EML_TPC_CFG_BASE 0x7FFF241780ull 4009#define KERNEL_SYNC_OBJECT_TPC1_EML_TPC_CFG_MAX_OFFSET 0x8000 4010#define KERNEL_SYNC_OBJECT_TPC1_EML_TPC_CFG_SECTION 0x8000 4011#define mmKERNEL_TPC1_EML_TPC_CFG_BASE 0x7FFF241788ull 4012#define KERNEL_TPC1_EML_TPC_CFG_MAX_OFFSET 0xB800 4013#define KERNEL_TPC1_EML_TPC_CFG_SECTION 0x2780 4014#define mmQM_TENSOR_0_TPC1_EML_TPC_CFG_BASE 0x7FFF241A00ull 4015#define QM_TENSOR_0_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 4016#define QM_TENSOR_0_TPC1_EML_TPC_CFG_SECTION 0x3800 4017#define mmQM_TENSOR_1_TPC1_EML_TPC_CFG_BASE 0x7FFF241A38ull 4018#define QM_TENSOR_1_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 4019#define QM_TENSOR_1_TPC1_EML_TPC_CFG_SECTION 0x3800 4020#define mmQM_TENSOR_2_TPC1_EML_TPC_CFG_BASE 0x7FFF241A70ull 4021#define QM_TENSOR_2_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 4022#define QM_TENSOR_2_TPC1_EML_TPC_CFG_SECTION 0x3800 4023#define mmQM_TENSOR_3_TPC1_EML_TPC_CFG_BASE 0x7FFF241AA8ull 4024#define QM_TENSOR_3_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 4025#define QM_TENSOR_3_TPC1_EML_TPC_CFG_SECTION 0x3800 4026#define mmQM_TENSOR_4_TPC1_EML_TPC_CFG_BASE 0x7FFF241AE0ull 4027#define QM_TENSOR_4_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 4028#define QM_TENSOR_4_TPC1_EML_TPC_CFG_SECTION 0x3800 4029#define mmQM_TENSOR_5_TPC1_EML_TPC_CFG_BASE 0x7FFF241B18ull 4030#define QM_TENSOR_5_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 4031#define QM_TENSOR_5_TPC1_EML_TPC_CFG_SECTION 0x3800 4032#define mmQM_TENSOR_6_TPC1_EML_TPC_CFG_BASE 0x7FFF241B50ull 4033#define QM_TENSOR_6_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 4034#define QM_TENSOR_6_TPC1_EML_TPC_CFG_SECTION 0x3800 4035#define mmQM_TENSOR_7_TPC1_EML_TPC_CFG_BASE 0x7FFF241B88ull 4036#define QM_TENSOR_7_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 4037#define QM_TENSOR_7_TPC1_EML_TPC_CFG_SECTION 0x3800 4038#define mmQM_TENSOR_8_TPC1_EML_TPC_CFG_BASE 0x7FFF241BC0ull 4039#define QM_TENSOR_8_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 4040#define QM_TENSOR_8_TPC1_EML_TPC_CFG_SECTION 0x3800 4041#define mmQM_TENSOR_9_TPC1_EML_TPC_CFG_BASE 0x7FFF241BF8ull 4042#define QM_TENSOR_9_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 4043#define QM_TENSOR_9_TPC1_EML_TPC_CFG_SECTION 0x3800 4044#define mmQM_TENSOR_10_TPC1_EML_TPC_CFG_BASE 0x7FFF241C30ull 4045#define QM_TENSOR_10_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 4046#define QM_TENSOR_10_TPC1_EML_TPC_CFG_SECTION 0x3800 4047#define mmQM_TENSOR_11_TPC1_EML_TPC_CFG_BASE 0x7FFF241C68ull 4048#define QM_TENSOR_11_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 4049#define QM_TENSOR_11_TPC1_EML_TPC_CFG_SECTION 0x3800 4050#define mmQM_TENSOR_12_TPC1_EML_TPC_CFG_BASE 0x7FFF241CA0ull 4051#define QM_TENSOR_12_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 4052#define QM_TENSOR_12_TPC1_EML_TPC_CFG_SECTION 0x3800 4053#define mmQM_TENSOR_13_TPC1_EML_TPC_CFG_BASE 0x7FFF241CD8ull 4054#define QM_TENSOR_13_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 4055#define QM_TENSOR_13_TPC1_EML_TPC_CFG_SECTION 0x3800 4056#define mmQM_TENSOR_14_TPC1_EML_TPC_CFG_BASE 0x7FFF241D10ull 4057#define QM_TENSOR_14_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 4058#define QM_TENSOR_14_TPC1_EML_TPC_CFG_SECTION 0x3800 4059#define mmQM_TENSOR_15_TPC1_EML_TPC_CFG_BASE 0x7FFF241D48ull 4060#define QM_TENSOR_15_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 4061#define QM_TENSOR_15_TPC1_EML_TPC_CFG_SECTION 0x3800 4062#define mmQM_SYNC_OBJECT_TPC1_EML_TPC_CFG_BASE 0x7FFF241D80ull 4063#define QM_SYNC_OBJECT_TPC1_EML_TPC_CFG_MAX_OFFSET 0x8000 4064#define QM_SYNC_OBJECT_TPC1_EML_TPC_CFG_SECTION 0x8000 4065#define mmQM_TPC1_EML_TPC_CFG_BASE 0x7FFF241D88ull 4066#define QM_TPC1_EML_TPC_CFG_MAX_OFFSET 0xB800 4067#define QM_TPC1_EML_TPC_CFG_SECTION 0x2780 4068#define mmTPC1_EML_TPC_QM_BASE 0x7FFF242000ull 4069#define TPC1_EML_TPC_QM_MAX_OFFSET 0xD040 4070#define TPC1_EML_TPC_QM_SECTION 0x1BD000 4071#define mmTPC1_EML_CS_BASE 0x7FFF3FF000ull 4072#define TPC1_EML_CS_MAX_OFFSET 0x1000 4073#define TPC1_EML_CS_SECTION 0x1000 4074#define mmTPC2_ROM_TABLE_BASE 0x7FFF400000ull 4075#define TPC2_ROM_TABLE_MAX_OFFSET 0x1000 4076#define TPC2_ROM_TABLE_SECTION 0x1000 4077#define mmTPC2_EML_SPMU_BASE 0x7FFF401000ull 4078#define TPC2_EML_SPMU_MAX_OFFSET 0x1000 4079#define TPC2_EML_SPMU_SECTION 0x1000 4080#define mmTPC2_EML_ETF_BASE 0x7FFF402000ull 4081#define TPC2_EML_ETF_MAX_OFFSET 0x1000 4082#define TPC2_EML_ETF_SECTION 0x1000 4083#define mmTPC2_EML_STM_BASE 0x7FFF403000ull 4084#define TPC2_EML_STM_MAX_OFFSET 0x1000 4085#define TPC2_EML_STM_SECTION 0x2000 4086#define mmTPC2_EML_CTI_BASE 0x7FFF405000ull 4087#define TPC2_EML_CTI_MAX_OFFSET 0x1000 4088#define TPC2_EML_CTI_SECTION 0x1000 4089#define mmTPC2_EML_FUNNEL_BASE 0x7FFF406000ull 4090#define TPC2_EML_FUNNEL_MAX_OFFSET 0x1000 4091#define TPC2_EML_FUNNEL_SECTION 0x1000 4092#define mmTPC2_EML_BUSMON_0_BASE 0x7FFF407000ull 4093#define TPC2_EML_BUSMON_0_MAX_OFFSET 0x1000 4094#define TPC2_EML_BUSMON_0_SECTION 0x1000 4095#define mmTPC2_EML_BUSMON_1_BASE 0x7FFF408000ull 4096#define TPC2_EML_BUSMON_1_MAX_OFFSET 0x1000 4097#define TPC2_EML_BUSMON_1_SECTION 0x1000 4098#define mmTPC2_EML_BUSMON_2_BASE 0x7FFF409000ull 4099#define TPC2_EML_BUSMON_2_MAX_OFFSET 0x1000 4100#define TPC2_EML_BUSMON_2_SECTION 0x1000 4101#define mmTPC2_EML_BUSMON_3_BASE 0x7FFF40A000ull 4102#define TPC2_EML_BUSMON_3_MAX_OFFSET 0x1000 4103#define TPC2_EML_BUSMON_3_SECTION 0x36000 4104#define mmTPC2_EML_CFG_BASE 0x7FFF440000ull 4105#define TPC2_EML_CFG_MAX_OFFSET 0x3380 4106#define TPC2_EML_CFG_SECTION 0x1000 4107#define mmTPC2_EML_TPC_CFG_BASE 0x7FFF441000ull 4108#define TPC2_EML_TPC_CFG_MAX_OFFSET 0xE400 4109#define TPC2_EML_TPC_CFG_SECTION 0x4000 4110#define mmKERNEL_TENSOR_0_TPC2_EML_TPC_CFG_BASE 0x7FFF441400ull 4111#define KERNEL_TENSOR_0_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4112#define KERNEL_TENSOR_0_TPC2_EML_TPC_CFG_SECTION 0x3800 4113#define mmKERNEL_TENSOR_1_TPC2_EML_TPC_CFG_BASE 0x7FFF441438ull 4114#define KERNEL_TENSOR_1_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4115#define KERNEL_TENSOR_1_TPC2_EML_TPC_CFG_SECTION 0x3800 4116#define mmKERNEL_TENSOR_2_TPC2_EML_TPC_CFG_BASE 0x7FFF441470ull 4117#define KERNEL_TENSOR_2_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4118#define KERNEL_TENSOR_2_TPC2_EML_TPC_CFG_SECTION 0x3800 4119#define mmKERNEL_TENSOR_3_TPC2_EML_TPC_CFG_BASE 0x7FFF4414A8ull 4120#define KERNEL_TENSOR_3_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4121#define KERNEL_TENSOR_3_TPC2_EML_TPC_CFG_SECTION 0x3800 4122#define mmKERNEL_TENSOR_4_TPC2_EML_TPC_CFG_BASE 0x7FFF4414E0ull 4123#define KERNEL_TENSOR_4_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4124#define KERNEL_TENSOR_4_TPC2_EML_TPC_CFG_SECTION 0x3800 4125#define mmKERNEL_TENSOR_5_TPC2_EML_TPC_CFG_BASE 0x7FFF441518ull 4126#define KERNEL_TENSOR_5_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4127#define KERNEL_TENSOR_5_TPC2_EML_TPC_CFG_SECTION 0x3800 4128#define mmKERNEL_TENSOR_6_TPC2_EML_TPC_CFG_BASE 0x7FFF441550ull 4129#define KERNEL_TENSOR_6_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4130#define KERNEL_TENSOR_6_TPC2_EML_TPC_CFG_SECTION 0x3800 4131#define mmKERNEL_TENSOR_7_TPC2_EML_TPC_CFG_BASE 0x7FFF441588ull 4132#define KERNEL_TENSOR_7_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4133#define KERNEL_TENSOR_7_TPC2_EML_TPC_CFG_SECTION 0x3800 4134#define mmKERNEL_TENSOR_8_TPC2_EML_TPC_CFG_BASE 0x7FFF4415C0ull 4135#define KERNEL_TENSOR_8_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4136#define KERNEL_TENSOR_8_TPC2_EML_TPC_CFG_SECTION 0x3800 4137#define mmKERNEL_TENSOR_9_TPC2_EML_TPC_CFG_BASE 0x7FFF4415F8ull 4138#define KERNEL_TENSOR_9_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4139#define KERNEL_TENSOR_9_TPC2_EML_TPC_CFG_SECTION 0x3800 4140#define mmKERNEL_TENSOR_10_TPC2_EML_TPC_CFG_BASE 0x7FFF441630ull 4141#define KERNEL_TENSOR_10_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4142#define KERNEL_TENSOR_10_TPC2_EML_TPC_CFG_SECTION 0x3800 4143#define mmKERNEL_TENSOR_11_TPC2_EML_TPC_CFG_BASE 0x7FFF441668ull 4144#define KERNEL_TENSOR_11_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4145#define KERNEL_TENSOR_11_TPC2_EML_TPC_CFG_SECTION 0x3800 4146#define mmKERNEL_TENSOR_12_TPC2_EML_TPC_CFG_BASE 0x7FFF4416A0ull 4147#define KERNEL_TENSOR_12_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4148#define KERNEL_TENSOR_12_TPC2_EML_TPC_CFG_SECTION 0x3800 4149#define mmKERNEL_TENSOR_13_TPC2_EML_TPC_CFG_BASE 0x7FFF4416D8ull 4150#define KERNEL_TENSOR_13_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4151#define KERNEL_TENSOR_13_TPC2_EML_TPC_CFG_SECTION 0x3800 4152#define mmKERNEL_TENSOR_14_TPC2_EML_TPC_CFG_BASE 0x7FFF441710ull 4153#define KERNEL_TENSOR_14_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4154#define KERNEL_TENSOR_14_TPC2_EML_TPC_CFG_SECTION 0x3800 4155#define mmKERNEL_TENSOR_15_TPC2_EML_TPC_CFG_BASE 0x7FFF441748ull 4156#define KERNEL_TENSOR_15_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4157#define KERNEL_TENSOR_15_TPC2_EML_TPC_CFG_SECTION 0x3800 4158#define mmKERNEL_SYNC_OBJECT_TPC2_EML_TPC_CFG_BASE 0x7FFF441780ull 4159#define KERNEL_SYNC_OBJECT_TPC2_EML_TPC_CFG_MAX_OFFSET 0x8000 4160#define KERNEL_SYNC_OBJECT_TPC2_EML_TPC_CFG_SECTION 0x8000 4161#define mmKERNEL_TPC2_EML_TPC_CFG_BASE 0x7FFF441788ull 4162#define KERNEL_TPC2_EML_TPC_CFG_MAX_OFFSET 0xB800 4163#define KERNEL_TPC2_EML_TPC_CFG_SECTION 0x2780 4164#define mmQM_TENSOR_0_TPC2_EML_TPC_CFG_BASE 0x7FFF441A00ull 4165#define QM_TENSOR_0_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4166#define QM_TENSOR_0_TPC2_EML_TPC_CFG_SECTION 0x3800 4167#define mmQM_TENSOR_1_TPC2_EML_TPC_CFG_BASE 0x7FFF441A38ull 4168#define QM_TENSOR_1_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4169#define QM_TENSOR_1_TPC2_EML_TPC_CFG_SECTION 0x3800 4170#define mmQM_TENSOR_2_TPC2_EML_TPC_CFG_BASE 0x7FFF441A70ull 4171#define QM_TENSOR_2_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4172#define QM_TENSOR_2_TPC2_EML_TPC_CFG_SECTION 0x3800 4173#define mmQM_TENSOR_3_TPC2_EML_TPC_CFG_BASE 0x7FFF441AA8ull 4174#define QM_TENSOR_3_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4175#define QM_TENSOR_3_TPC2_EML_TPC_CFG_SECTION 0x3800 4176#define mmQM_TENSOR_4_TPC2_EML_TPC_CFG_BASE 0x7FFF441AE0ull 4177#define QM_TENSOR_4_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4178#define QM_TENSOR_4_TPC2_EML_TPC_CFG_SECTION 0x3800 4179#define mmQM_TENSOR_5_TPC2_EML_TPC_CFG_BASE 0x7FFF441B18ull 4180#define QM_TENSOR_5_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4181#define QM_TENSOR_5_TPC2_EML_TPC_CFG_SECTION 0x3800 4182#define mmQM_TENSOR_6_TPC2_EML_TPC_CFG_BASE 0x7FFF441B50ull 4183#define QM_TENSOR_6_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4184#define QM_TENSOR_6_TPC2_EML_TPC_CFG_SECTION 0x3800 4185#define mmQM_TENSOR_7_TPC2_EML_TPC_CFG_BASE 0x7FFF441B88ull 4186#define QM_TENSOR_7_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4187#define QM_TENSOR_7_TPC2_EML_TPC_CFG_SECTION 0x3800 4188#define mmQM_TENSOR_8_TPC2_EML_TPC_CFG_BASE 0x7FFF441BC0ull 4189#define QM_TENSOR_8_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4190#define QM_TENSOR_8_TPC2_EML_TPC_CFG_SECTION 0x3800 4191#define mmQM_TENSOR_9_TPC2_EML_TPC_CFG_BASE 0x7FFF441BF8ull 4192#define QM_TENSOR_9_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4193#define QM_TENSOR_9_TPC2_EML_TPC_CFG_SECTION 0x3800 4194#define mmQM_TENSOR_10_TPC2_EML_TPC_CFG_BASE 0x7FFF441C30ull 4195#define QM_TENSOR_10_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4196#define QM_TENSOR_10_TPC2_EML_TPC_CFG_SECTION 0x3800 4197#define mmQM_TENSOR_11_TPC2_EML_TPC_CFG_BASE 0x7FFF441C68ull 4198#define QM_TENSOR_11_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4199#define QM_TENSOR_11_TPC2_EML_TPC_CFG_SECTION 0x3800 4200#define mmQM_TENSOR_12_TPC2_EML_TPC_CFG_BASE 0x7FFF441CA0ull 4201#define QM_TENSOR_12_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4202#define QM_TENSOR_12_TPC2_EML_TPC_CFG_SECTION 0x3800 4203#define mmQM_TENSOR_13_TPC2_EML_TPC_CFG_BASE 0x7FFF441CD8ull 4204#define QM_TENSOR_13_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4205#define QM_TENSOR_13_TPC2_EML_TPC_CFG_SECTION 0x3800 4206#define mmQM_TENSOR_14_TPC2_EML_TPC_CFG_BASE 0x7FFF441D10ull 4207#define QM_TENSOR_14_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4208#define QM_TENSOR_14_TPC2_EML_TPC_CFG_SECTION 0x3800 4209#define mmQM_TENSOR_15_TPC2_EML_TPC_CFG_BASE 0x7FFF441D48ull 4210#define QM_TENSOR_15_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4211#define QM_TENSOR_15_TPC2_EML_TPC_CFG_SECTION 0x3800 4212#define mmQM_SYNC_OBJECT_TPC2_EML_TPC_CFG_BASE 0x7FFF441D80ull 4213#define QM_SYNC_OBJECT_TPC2_EML_TPC_CFG_MAX_OFFSET 0x8000 4214#define QM_SYNC_OBJECT_TPC2_EML_TPC_CFG_SECTION 0x8000 4215#define mmQM_TPC2_EML_TPC_CFG_BASE 0x7FFF441D88ull 4216#define QM_TPC2_EML_TPC_CFG_MAX_OFFSET 0xB800 4217#define QM_TPC2_EML_TPC_CFG_SECTION 0x2780 4218#define mmTPC2_EML_TPC_QM_BASE 0x7FFF442000ull 4219#define TPC2_EML_TPC_QM_MAX_OFFSET 0xD040 4220#define TPC2_EML_TPC_QM_SECTION 0x1BD000 4221#define mmTPC2_EML_CS_BASE 0x7FFF5FF000ull 4222#define TPC2_EML_CS_MAX_OFFSET 0x1000 4223#define TPC2_EML_CS_SECTION 0x1000 4224#define mmTPC3_ROM_TABLE_BASE 0x7FFF600000ull 4225#define TPC3_ROM_TABLE_MAX_OFFSET 0x1000 4226#define TPC3_ROM_TABLE_SECTION 0x1000 4227#define mmTPC3_EML_SPMU_BASE 0x7FFF601000ull 4228#define TPC3_EML_SPMU_MAX_OFFSET 0x1000 4229#define TPC3_EML_SPMU_SECTION 0x1000 4230#define mmTPC3_EML_ETF_BASE 0x7FFF602000ull 4231#define TPC3_EML_ETF_MAX_OFFSET 0x1000 4232#define TPC3_EML_ETF_SECTION 0x1000 4233#define mmTPC3_EML_STM_BASE 0x7FFF603000ull 4234#define TPC3_EML_STM_MAX_OFFSET 0x1000 4235#define TPC3_EML_STM_SECTION 0x2000 4236#define mmTPC3_EML_CTI_BASE 0x7FFF605000ull 4237#define TPC3_EML_CTI_MAX_OFFSET 0x1000 4238#define TPC3_EML_CTI_SECTION 0x1000 4239#define mmTPC3_EML_FUNNEL_BASE 0x7FFF606000ull 4240#define TPC3_EML_FUNNEL_MAX_OFFSET 0x1000 4241#define TPC3_EML_FUNNEL_SECTION 0x1000 4242#define mmTPC3_EML_BUSMON_0_BASE 0x7FFF607000ull 4243#define TPC3_EML_BUSMON_0_MAX_OFFSET 0x1000 4244#define TPC3_EML_BUSMON_0_SECTION 0x1000 4245#define mmTPC3_EML_BUSMON_1_BASE 0x7FFF608000ull 4246#define TPC3_EML_BUSMON_1_MAX_OFFSET 0x1000 4247#define TPC3_EML_BUSMON_1_SECTION 0x1000 4248#define mmTPC3_EML_BUSMON_2_BASE 0x7FFF609000ull 4249#define TPC3_EML_BUSMON_2_MAX_OFFSET 0x1000 4250#define TPC3_EML_BUSMON_2_SECTION 0x1000 4251#define mmTPC3_EML_BUSMON_3_BASE 0x7FFF60A000ull 4252#define TPC3_EML_BUSMON_3_MAX_OFFSET 0x1000 4253#define TPC3_EML_BUSMON_3_SECTION 0x36000 4254#define mmTPC3_EML_CFG_BASE 0x7FFF640000ull 4255#define TPC3_EML_CFG_MAX_OFFSET 0x3380 4256#define TPC3_EML_CFG_SECTION 0x1000 4257#define mmTPC3_EML_TPC_CFG_BASE 0x7FFF641000ull 4258#define TPC3_EML_TPC_CFG_MAX_OFFSET 0xE400 4259#define TPC3_EML_TPC_CFG_SECTION 0x4000 4260#define mmKERNEL_TENSOR_0_TPC3_EML_TPC_CFG_BASE 0x7FFF641400ull 4261#define KERNEL_TENSOR_0_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4262#define KERNEL_TENSOR_0_TPC3_EML_TPC_CFG_SECTION 0x3800 4263#define mmKERNEL_TENSOR_1_TPC3_EML_TPC_CFG_BASE 0x7FFF641438ull 4264#define KERNEL_TENSOR_1_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4265#define KERNEL_TENSOR_1_TPC3_EML_TPC_CFG_SECTION 0x3800 4266#define mmKERNEL_TENSOR_2_TPC3_EML_TPC_CFG_BASE 0x7FFF641470ull 4267#define KERNEL_TENSOR_2_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4268#define KERNEL_TENSOR_2_TPC3_EML_TPC_CFG_SECTION 0x3800 4269#define mmKERNEL_TENSOR_3_TPC3_EML_TPC_CFG_BASE 0x7FFF6414A8ull 4270#define KERNEL_TENSOR_3_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4271#define KERNEL_TENSOR_3_TPC3_EML_TPC_CFG_SECTION 0x3800 4272#define mmKERNEL_TENSOR_4_TPC3_EML_TPC_CFG_BASE 0x7FFF6414E0ull 4273#define KERNEL_TENSOR_4_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4274#define KERNEL_TENSOR_4_TPC3_EML_TPC_CFG_SECTION 0x3800 4275#define mmKERNEL_TENSOR_5_TPC3_EML_TPC_CFG_BASE 0x7FFF641518ull 4276#define KERNEL_TENSOR_5_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4277#define KERNEL_TENSOR_5_TPC3_EML_TPC_CFG_SECTION 0x3800 4278#define mmKERNEL_TENSOR_6_TPC3_EML_TPC_CFG_BASE 0x7FFF641550ull 4279#define KERNEL_TENSOR_6_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4280#define KERNEL_TENSOR_6_TPC3_EML_TPC_CFG_SECTION 0x3800 4281#define mmKERNEL_TENSOR_7_TPC3_EML_TPC_CFG_BASE 0x7FFF641588ull 4282#define KERNEL_TENSOR_7_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4283#define KERNEL_TENSOR_7_TPC3_EML_TPC_CFG_SECTION 0x3800 4284#define mmKERNEL_TENSOR_8_TPC3_EML_TPC_CFG_BASE 0x7FFF6415C0ull 4285#define KERNEL_TENSOR_8_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4286#define KERNEL_TENSOR_8_TPC3_EML_TPC_CFG_SECTION 0x3800 4287#define mmKERNEL_TENSOR_9_TPC3_EML_TPC_CFG_BASE 0x7FFF6415F8ull 4288#define KERNEL_TENSOR_9_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4289#define KERNEL_TENSOR_9_TPC3_EML_TPC_CFG_SECTION 0x3800 4290#define mmKERNEL_TENSOR_10_TPC3_EML_TPC_CFG_BASE 0x7FFF641630ull 4291#define KERNEL_TENSOR_10_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4292#define KERNEL_TENSOR_10_TPC3_EML_TPC_CFG_SECTION 0x3800 4293#define mmKERNEL_TENSOR_11_TPC3_EML_TPC_CFG_BASE 0x7FFF641668ull 4294#define KERNEL_TENSOR_11_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4295#define KERNEL_TENSOR_11_TPC3_EML_TPC_CFG_SECTION 0x3800 4296#define mmKERNEL_TENSOR_12_TPC3_EML_TPC_CFG_BASE 0x7FFF6416A0ull 4297#define KERNEL_TENSOR_12_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4298#define KERNEL_TENSOR_12_TPC3_EML_TPC_CFG_SECTION 0x3800 4299#define mmKERNEL_TENSOR_13_TPC3_EML_TPC_CFG_BASE 0x7FFF6416D8ull 4300#define KERNEL_TENSOR_13_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4301#define KERNEL_TENSOR_13_TPC3_EML_TPC_CFG_SECTION 0x3800 4302#define mmKERNEL_TENSOR_14_TPC3_EML_TPC_CFG_BASE 0x7FFF641710ull 4303#define KERNEL_TENSOR_14_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4304#define KERNEL_TENSOR_14_TPC3_EML_TPC_CFG_SECTION 0x3800 4305#define mmKERNEL_TENSOR_15_TPC3_EML_TPC_CFG_BASE 0x7FFF641748ull 4306#define KERNEL_TENSOR_15_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4307#define KERNEL_TENSOR_15_TPC3_EML_TPC_CFG_SECTION 0x3800 4308#define mmKERNEL_SYNC_OBJECT_TPC3_EML_TPC_CFG_BASE 0x7FFF641780ull 4309#define KERNEL_SYNC_OBJECT_TPC3_EML_TPC_CFG_MAX_OFFSET 0x8000 4310#define KERNEL_SYNC_OBJECT_TPC3_EML_TPC_CFG_SECTION 0x8000 4311#define mmKERNEL_TPC3_EML_TPC_CFG_BASE 0x7FFF641788ull 4312#define KERNEL_TPC3_EML_TPC_CFG_MAX_OFFSET 0xB800 4313#define KERNEL_TPC3_EML_TPC_CFG_SECTION 0x2780 4314#define mmQM_TENSOR_0_TPC3_EML_TPC_CFG_BASE 0x7FFF641A00ull 4315#define QM_TENSOR_0_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4316#define QM_TENSOR_0_TPC3_EML_TPC_CFG_SECTION 0x3800 4317#define mmQM_TENSOR_1_TPC3_EML_TPC_CFG_BASE 0x7FFF641A38ull 4318#define QM_TENSOR_1_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4319#define QM_TENSOR_1_TPC3_EML_TPC_CFG_SECTION 0x3800 4320#define mmQM_TENSOR_2_TPC3_EML_TPC_CFG_BASE 0x7FFF641A70ull 4321#define QM_TENSOR_2_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4322#define QM_TENSOR_2_TPC3_EML_TPC_CFG_SECTION 0x3800 4323#define mmQM_TENSOR_3_TPC3_EML_TPC_CFG_BASE 0x7FFF641AA8ull 4324#define QM_TENSOR_3_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4325#define QM_TENSOR_3_TPC3_EML_TPC_CFG_SECTION 0x3800 4326#define mmQM_TENSOR_4_TPC3_EML_TPC_CFG_BASE 0x7FFF641AE0ull 4327#define QM_TENSOR_4_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4328#define QM_TENSOR_4_TPC3_EML_TPC_CFG_SECTION 0x3800 4329#define mmQM_TENSOR_5_TPC3_EML_TPC_CFG_BASE 0x7FFF641B18ull 4330#define QM_TENSOR_5_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4331#define QM_TENSOR_5_TPC3_EML_TPC_CFG_SECTION 0x3800 4332#define mmQM_TENSOR_6_TPC3_EML_TPC_CFG_BASE 0x7FFF641B50ull 4333#define QM_TENSOR_6_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4334#define QM_TENSOR_6_TPC3_EML_TPC_CFG_SECTION 0x3800 4335#define mmQM_TENSOR_7_TPC3_EML_TPC_CFG_BASE 0x7FFF641B88ull 4336#define QM_TENSOR_7_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4337#define QM_TENSOR_7_TPC3_EML_TPC_CFG_SECTION 0x3800 4338#define mmQM_TENSOR_8_TPC3_EML_TPC_CFG_BASE 0x7FFF641BC0ull 4339#define QM_TENSOR_8_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4340#define QM_TENSOR_8_TPC3_EML_TPC_CFG_SECTION 0x3800 4341#define mmQM_TENSOR_9_TPC3_EML_TPC_CFG_BASE 0x7FFF641BF8ull 4342#define QM_TENSOR_9_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4343#define QM_TENSOR_9_TPC3_EML_TPC_CFG_SECTION 0x3800 4344#define mmQM_TENSOR_10_TPC3_EML_TPC_CFG_BASE 0x7FFF641C30ull 4345#define QM_TENSOR_10_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4346#define QM_TENSOR_10_TPC3_EML_TPC_CFG_SECTION 0x3800 4347#define mmQM_TENSOR_11_TPC3_EML_TPC_CFG_BASE 0x7FFF641C68ull 4348#define QM_TENSOR_11_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4349#define QM_TENSOR_11_TPC3_EML_TPC_CFG_SECTION 0x3800 4350#define mmQM_TENSOR_12_TPC3_EML_TPC_CFG_BASE 0x7FFF641CA0ull 4351#define QM_TENSOR_12_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4352#define QM_TENSOR_12_TPC3_EML_TPC_CFG_SECTION 0x3800 4353#define mmQM_TENSOR_13_TPC3_EML_TPC_CFG_BASE 0x7FFF641CD8ull 4354#define QM_TENSOR_13_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4355#define QM_TENSOR_13_TPC3_EML_TPC_CFG_SECTION 0x3800 4356#define mmQM_TENSOR_14_TPC3_EML_TPC_CFG_BASE 0x7FFF641D10ull 4357#define QM_TENSOR_14_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4358#define QM_TENSOR_14_TPC3_EML_TPC_CFG_SECTION 0x3800 4359#define mmQM_TENSOR_15_TPC3_EML_TPC_CFG_BASE 0x7FFF641D48ull 4360#define QM_TENSOR_15_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4361#define QM_TENSOR_15_TPC3_EML_TPC_CFG_SECTION 0x3800 4362#define mmQM_SYNC_OBJECT_TPC3_EML_TPC_CFG_BASE 0x7FFF641D80ull 4363#define QM_SYNC_OBJECT_TPC3_EML_TPC_CFG_MAX_OFFSET 0x8000 4364#define QM_SYNC_OBJECT_TPC3_EML_TPC_CFG_SECTION 0x8000 4365#define mmQM_TPC3_EML_TPC_CFG_BASE 0x7FFF641D88ull 4366#define QM_TPC3_EML_TPC_CFG_MAX_OFFSET 0xB800 4367#define QM_TPC3_EML_TPC_CFG_SECTION 0x2780 4368#define mmTPC3_EML_TPC_QM_BASE 0x7FFF642000ull 4369#define TPC3_EML_TPC_QM_MAX_OFFSET 0xD040 4370#define TPC3_EML_TPC_QM_SECTION 0x1BD000 4371#define mmTPC3_EML_CS_BASE 0x7FFF7FF000ull 4372#define TPC3_EML_CS_MAX_OFFSET 0x1000 4373#define TPC3_EML_CS_SECTION 0x1000 4374#define mmTPC4_ROM_TABLE_BASE 0x7FFF800000ull 4375#define TPC4_ROM_TABLE_MAX_OFFSET 0x1000 4376#define TPC4_ROM_TABLE_SECTION 0x1000 4377#define mmTPC4_EML_SPMU_BASE 0x7FFF801000ull 4378#define TPC4_EML_SPMU_MAX_OFFSET 0x1000 4379#define TPC4_EML_SPMU_SECTION 0x1000 4380#define mmTPC4_EML_ETF_BASE 0x7FFF802000ull 4381#define TPC4_EML_ETF_MAX_OFFSET 0x1000 4382#define TPC4_EML_ETF_SECTION 0x1000 4383#define mmTPC4_EML_STM_BASE 0x7FFF803000ull 4384#define TPC4_EML_STM_MAX_OFFSET 0x1000 4385#define TPC4_EML_STM_SECTION 0x2000 4386#define mmTPC4_EML_CTI_BASE 0x7FFF805000ull 4387#define TPC4_EML_CTI_MAX_OFFSET 0x1000 4388#define TPC4_EML_CTI_SECTION 0x1000 4389#define mmTPC4_EML_FUNNEL_BASE 0x7FFF806000ull 4390#define TPC4_EML_FUNNEL_MAX_OFFSET 0x1000 4391#define TPC4_EML_FUNNEL_SECTION 0x1000 4392#define mmTPC4_EML_BUSMON_0_BASE 0x7FFF807000ull 4393#define TPC4_EML_BUSMON_0_MAX_OFFSET 0x1000 4394#define TPC4_EML_BUSMON_0_SECTION 0x1000 4395#define mmTPC4_EML_BUSMON_1_BASE 0x7FFF808000ull 4396#define TPC4_EML_BUSMON_1_MAX_OFFSET 0x1000 4397#define TPC4_EML_BUSMON_1_SECTION 0x1000 4398#define mmTPC4_EML_BUSMON_2_BASE 0x7FFF809000ull 4399#define TPC4_EML_BUSMON_2_MAX_OFFSET 0x1000 4400#define TPC4_EML_BUSMON_2_SECTION 0x1000 4401#define mmTPC4_EML_BUSMON_3_BASE 0x7FFF80A000ull 4402#define TPC4_EML_BUSMON_3_MAX_OFFSET 0x1000 4403#define TPC4_EML_BUSMON_3_SECTION 0x36000 4404#define mmTPC4_EML_CFG_BASE 0x7FFF840000ull 4405#define TPC4_EML_CFG_MAX_OFFSET 0x3380 4406#define TPC4_EML_CFG_SECTION 0x1000 4407#define mmTPC4_EML_TPC_CFG_BASE 0x7FFF841000ull 4408#define TPC4_EML_TPC_CFG_MAX_OFFSET 0xE400 4409#define TPC4_EML_TPC_CFG_SECTION 0x4000 4410#define mmKERNEL_TENSOR_0_TPC4_EML_TPC_CFG_BASE 0x7FFF841400ull 4411#define KERNEL_TENSOR_0_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4412#define KERNEL_TENSOR_0_TPC4_EML_TPC_CFG_SECTION 0x3800 4413#define mmKERNEL_TENSOR_1_TPC4_EML_TPC_CFG_BASE 0x7FFF841438ull 4414#define KERNEL_TENSOR_1_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4415#define KERNEL_TENSOR_1_TPC4_EML_TPC_CFG_SECTION 0x3800 4416#define mmKERNEL_TENSOR_2_TPC4_EML_TPC_CFG_BASE 0x7FFF841470ull 4417#define KERNEL_TENSOR_2_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4418#define KERNEL_TENSOR_2_TPC4_EML_TPC_CFG_SECTION 0x3800 4419#define mmKERNEL_TENSOR_3_TPC4_EML_TPC_CFG_BASE 0x7FFF8414A8ull 4420#define KERNEL_TENSOR_3_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4421#define KERNEL_TENSOR_3_TPC4_EML_TPC_CFG_SECTION 0x3800 4422#define mmKERNEL_TENSOR_4_TPC4_EML_TPC_CFG_BASE 0x7FFF8414E0ull 4423#define KERNEL_TENSOR_4_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4424#define KERNEL_TENSOR_4_TPC4_EML_TPC_CFG_SECTION 0x3800 4425#define mmKERNEL_TENSOR_5_TPC4_EML_TPC_CFG_BASE 0x7FFF841518ull 4426#define KERNEL_TENSOR_5_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4427#define KERNEL_TENSOR_5_TPC4_EML_TPC_CFG_SECTION 0x3800 4428#define mmKERNEL_TENSOR_6_TPC4_EML_TPC_CFG_BASE 0x7FFF841550ull 4429#define KERNEL_TENSOR_6_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4430#define KERNEL_TENSOR_6_TPC4_EML_TPC_CFG_SECTION 0x3800 4431#define mmKERNEL_TENSOR_7_TPC4_EML_TPC_CFG_BASE 0x7FFF841588ull 4432#define KERNEL_TENSOR_7_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4433#define KERNEL_TENSOR_7_TPC4_EML_TPC_CFG_SECTION 0x3800 4434#define mmKERNEL_TENSOR_8_TPC4_EML_TPC_CFG_BASE 0x7FFF8415C0ull 4435#define KERNEL_TENSOR_8_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4436#define KERNEL_TENSOR_8_TPC4_EML_TPC_CFG_SECTION 0x3800 4437#define mmKERNEL_TENSOR_9_TPC4_EML_TPC_CFG_BASE 0x7FFF8415F8ull 4438#define KERNEL_TENSOR_9_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4439#define KERNEL_TENSOR_9_TPC4_EML_TPC_CFG_SECTION 0x3800 4440#define mmKERNEL_TENSOR_10_TPC4_EML_TPC_CFG_BASE 0x7FFF841630ull 4441#define KERNEL_TENSOR_10_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4442#define KERNEL_TENSOR_10_TPC4_EML_TPC_CFG_SECTION 0x3800 4443#define mmKERNEL_TENSOR_11_TPC4_EML_TPC_CFG_BASE 0x7FFF841668ull 4444#define KERNEL_TENSOR_11_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4445#define KERNEL_TENSOR_11_TPC4_EML_TPC_CFG_SECTION 0x3800 4446#define mmKERNEL_TENSOR_12_TPC4_EML_TPC_CFG_BASE 0x7FFF8416A0ull 4447#define KERNEL_TENSOR_12_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4448#define KERNEL_TENSOR_12_TPC4_EML_TPC_CFG_SECTION 0x3800 4449#define mmKERNEL_TENSOR_13_TPC4_EML_TPC_CFG_BASE 0x7FFF8416D8ull 4450#define KERNEL_TENSOR_13_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4451#define KERNEL_TENSOR_13_TPC4_EML_TPC_CFG_SECTION 0x3800 4452#define mmKERNEL_TENSOR_14_TPC4_EML_TPC_CFG_BASE 0x7FFF841710ull 4453#define KERNEL_TENSOR_14_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4454#define KERNEL_TENSOR_14_TPC4_EML_TPC_CFG_SECTION 0x3800 4455#define mmKERNEL_TENSOR_15_TPC4_EML_TPC_CFG_BASE 0x7FFF841748ull 4456#define KERNEL_TENSOR_15_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4457#define KERNEL_TENSOR_15_TPC4_EML_TPC_CFG_SECTION 0x3800 4458#define mmKERNEL_SYNC_OBJECT_TPC4_EML_TPC_CFG_BASE 0x7FFF841780ull 4459#define KERNEL_SYNC_OBJECT_TPC4_EML_TPC_CFG_MAX_OFFSET 0x8000 4460#define KERNEL_SYNC_OBJECT_TPC4_EML_TPC_CFG_SECTION 0x8000 4461#define mmKERNEL_TPC4_EML_TPC_CFG_BASE 0x7FFF841788ull 4462#define KERNEL_TPC4_EML_TPC_CFG_MAX_OFFSET 0xB800 4463#define KERNEL_TPC4_EML_TPC_CFG_SECTION 0x2780 4464#define mmQM_TENSOR_0_TPC4_EML_TPC_CFG_BASE 0x7FFF841A00ull 4465#define QM_TENSOR_0_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4466#define QM_TENSOR_0_TPC4_EML_TPC_CFG_SECTION 0x3800 4467#define mmQM_TENSOR_1_TPC4_EML_TPC_CFG_BASE 0x7FFF841A38ull 4468#define QM_TENSOR_1_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4469#define QM_TENSOR_1_TPC4_EML_TPC_CFG_SECTION 0x3800 4470#define mmQM_TENSOR_2_TPC4_EML_TPC_CFG_BASE 0x7FFF841A70ull 4471#define QM_TENSOR_2_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4472#define QM_TENSOR_2_TPC4_EML_TPC_CFG_SECTION 0x3800 4473#define mmQM_TENSOR_3_TPC4_EML_TPC_CFG_BASE 0x7FFF841AA8ull 4474#define QM_TENSOR_3_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4475#define QM_TENSOR_3_TPC4_EML_TPC_CFG_SECTION 0x3800 4476#define mmQM_TENSOR_4_TPC4_EML_TPC_CFG_BASE 0x7FFF841AE0ull 4477#define QM_TENSOR_4_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4478#define QM_TENSOR_4_TPC4_EML_TPC_CFG_SECTION 0x3800 4479#define mmQM_TENSOR_5_TPC4_EML_TPC_CFG_BASE 0x7FFF841B18ull 4480#define QM_TENSOR_5_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4481#define QM_TENSOR_5_TPC4_EML_TPC_CFG_SECTION 0x3800 4482#define mmQM_TENSOR_6_TPC4_EML_TPC_CFG_BASE 0x7FFF841B50ull 4483#define QM_TENSOR_6_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4484#define QM_TENSOR_6_TPC4_EML_TPC_CFG_SECTION 0x3800 4485#define mmQM_TENSOR_7_TPC4_EML_TPC_CFG_BASE 0x7FFF841B88ull 4486#define QM_TENSOR_7_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4487#define QM_TENSOR_7_TPC4_EML_TPC_CFG_SECTION 0x3800 4488#define mmQM_TENSOR_8_TPC4_EML_TPC_CFG_BASE 0x7FFF841BC0ull 4489#define QM_TENSOR_8_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4490#define QM_TENSOR_8_TPC4_EML_TPC_CFG_SECTION 0x3800 4491#define mmQM_TENSOR_9_TPC4_EML_TPC_CFG_BASE 0x7FFF841BF8ull 4492#define QM_TENSOR_9_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4493#define QM_TENSOR_9_TPC4_EML_TPC_CFG_SECTION 0x3800 4494#define mmQM_TENSOR_10_TPC4_EML_TPC_CFG_BASE 0x7FFF841C30ull 4495#define QM_TENSOR_10_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4496#define QM_TENSOR_10_TPC4_EML_TPC_CFG_SECTION 0x3800 4497#define mmQM_TENSOR_11_TPC4_EML_TPC_CFG_BASE 0x7FFF841C68ull 4498#define QM_TENSOR_11_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4499#define QM_TENSOR_11_TPC4_EML_TPC_CFG_SECTION 0x3800 4500#define mmQM_TENSOR_12_TPC4_EML_TPC_CFG_BASE 0x7FFF841CA0ull 4501#define QM_TENSOR_12_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4502#define QM_TENSOR_12_TPC4_EML_TPC_CFG_SECTION 0x3800 4503#define mmQM_TENSOR_13_TPC4_EML_TPC_CFG_BASE 0x7FFF841CD8ull 4504#define QM_TENSOR_13_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4505#define QM_TENSOR_13_TPC4_EML_TPC_CFG_SECTION 0x3800 4506#define mmQM_TENSOR_14_TPC4_EML_TPC_CFG_BASE 0x7FFF841D10ull 4507#define QM_TENSOR_14_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4508#define QM_TENSOR_14_TPC4_EML_TPC_CFG_SECTION 0x3800 4509#define mmQM_TENSOR_15_TPC4_EML_TPC_CFG_BASE 0x7FFF841D48ull 4510#define QM_TENSOR_15_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4511#define QM_TENSOR_15_TPC4_EML_TPC_CFG_SECTION 0x3800 4512#define mmQM_SYNC_OBJECT_TPC4_EML_TPC_CFG_BASE 0x7FFF841D80ull 4513#define QM_SYNC_OBJECT_TPC4_EML_TPC_CFG_MAX_OFFSET 0x8000 4514#define QM_SYNC_OBJECT_TPC4_EML_TPC_CFG_SECTION 0x8000 4515#define mmQM_TPC4_EML_TPC_CFG_BASE 0x7FFF841D88ull 4516#define QM_TPC4_EML_TPC_CFG_MAX_OFFSET 0xB800 4517#define QM_TPC4_EML_TPC_CFG_SECTION 0x2780 4518#define mmTPC4_EML_TPC_QM_BASE 0x7FFF842000ull 4519#define TPC4_EML_TPC_QM_MAX_OFFSET 0xD040 4520#define TPC4_EML_TPC_QM_SECTION 0x1BD000 4521#define mmTPC4_EML_CS_BASE 0x7FFF9FF000ull 4522#define TPC4_EML_CS_MAX_OFFSET 0x1000 4523#define TPC4_EML_CS_SECTION 0x1000 4524#define mmTPC5_ROM_TABLE_BASE 0x7FFFA00000ull 4525#define TPC5_ROM_TABLE_MAX_OFFSET 0x1000 4526#define TPC5_ROM_TABLE_SECTION 0x1000 4527#define mmTPC5_EML_SPMU_BASE 0x7FFFA01000ull 4528#define TPC5_EML_SPMU_MAX_OFFSET 0x1000 4529#define TPC5_EML_SPMU_SECTION 0x1000 4530#define mmTPC5_EML_ETF_BASE 0x7FFFA02000ull 4531#define TPC5_EML_ETF_MAX_OFFSET 0x1000 4532#define TPC5_EML_ETF_SECTION 0x1000 4533#define mmTPC5_EML_STM_BASE 0x7FFFA03000ull 4534#define TPC5_EML_STM_MAX_OFFSET 0x1000 4535#define TPC5_EML_STM_SECTION 0x2000 4536#define mmTPC5_EML_CTI_BASE 0x7FFFA05000ull 4537#define TPC5_EML_CTI_MAX_OFFSET 0x1000 4538#define TPC5_EML_CTI_SECTION 0x1000 4539#define mmTPC5_EML_FUNNEL_BASE 0x7FFFA06000ull 4540#define TPC5_EML_FUNNEL_MAX_OFFSET 0x1000 4541#define TPC5_EML_FUNNEL_SECTION 0x1000 4542#define mmTPC5_EML_BUSMON_0_BASE 0x7FFFA07000ull 4543#define TPC5_EML_BUSMON_0_MAX_OFFSET 0x1000 4544#define TPC5_EML_BUSMON_0_SECTION 0x1000 4545#define mmTPC5_EML_BUSMON_1_BASE 0x7FFFA08000ull 4546#define TPC5_EML_BUSMON_1_MAX_OFFSET 0x1000 4547#define TPC5_EML_BUSMON_1_SECTION 0x1000 4548#define mmTPC5_EML_BUSMON_2_BASE 0x7FFFA09000ull 4549#define TPC5_EML_BUSMON_2_MAX_OFFSET 0x1000 4550#define TPC5_EML_BUSMON_2_SECTION 0x1000 4551#define mmTPC5_EML_BUSMON_3_BASE 0x7FFFA0A000ull 4552#define TPC5_EML_BUSMON_3_MAX_OFFSET 0x1000 4553#define TPC5_EML_BUSMON_3_SECTION 0x36000 4554#define mmTPC5_EML_CFG_BASE 0x7FFFA40000ull 4555#define TPC5_EML_CFG_MAX_OFFSET 0x3380 4556#define TPC5_EML_CFG_SECTION 0x1000 4557#define mmTPC5_EML_TPC_CFG_BASE 0x7FFFA41000ull 4558#define TPC5_EML_TPC_CFG_MAX_OFFSET 0xE400 4559#define TPC5_EML_TPC_CFG_SECTION 0x4000 4560#define mmKERNEL_TENSOR_0_TPC5_EML_TPC_CFG_BASE 0x7FFFA41400ull 4561#define KERNEL_TENSOR_0_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4562#define KERNEL_TENSOR_0_TPC5_EML_TPC_CFG_SECTION 0x3800 4563#define mmKERNEL_TENSOR_1_TPC5_EML_TPC_CFG_BASE 0x7FFFA41438ull 4564#define KERNEL_TENSOR_1_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4565#define KERNEL_TENSOR_1_TPC5_EML_TPC_CFG_SECTION 0x3800 4566#define mmKERNEL_TENSOR_2_TPC5_EML_TPC_CFG_BASE 0x7FFFA41470ull 4567#define KERNEL_TENSOR_2_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4568#define KERNEL_TENSOR_2_TPC5_EML_TPC_CFG_SECTION 0x3800 4569#define mmKERNEL_TENSOR_3_TPC5_EML_TPC_CFG_BASE 0x7FFFA414A8ull 4570#define KERNEL_TENSOR_3_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4571#define KERNEL_TENSOR_3_TPC5_EML_TPC_CFG_SECTION 0x3800 4572#define mmKERNEL_TENSOR_4_TPC5_EML_TPC_CFG_BASE 0x7FFFA414E0ull 4573#define KERNEL_TENSOR_4_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4574#define KERNEL_TENSOR_4_TPC5_EML_TPC_CFG_SECTION 0x3800 4575#define mmKERNEL_TENSOR_5_TPC5_EML_TPC_CFG_BASE 0x7FFFA41518ull 4576#define KERNEL_TENSOR_5_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4577#define KERNEL_TENSOR_5_TPC5_EML_TPC_CFG_SECTION 0x3800 4578#define mmKERNEL_TENSOR_6_TPC5_EML_TPC_CFG_BASE 0x7FFFA41550ull 4579#define KERNEL_TENSOR_6_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4580#define KERNEL_TENSOR_6_TPC5_EML_TPC_CFG_SECTION 0x3800 4581#define mmKERNEL_TENSOR_7_TPC5_EML_TPC_CFG_BASE 0x7FFFA41588ull 4582#define KERNEL_TENSOR_7_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4583#define KERNEL_TENSOR_7_TPC5_EML_TPC_CFG_SECTION 0x3800 4584#define mmKERNEL_TENSOR_8_TPC5_EML_TPC_CFG_BASE 0x7FFFA415C0ull 4585#define KERNEL_TENSOR_8_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4586#define KERNEL_TENSOR_8_TPC5_EML_TPC_CFG_SECTION 0x3800 4587#define mmKERNEL_TENSOR_9_TPC5_EML_TPC_CFG_BASE 0x7FFFA415F8ull 4588#define KERNEL_TENSOR_9_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4589#define KERNEL_TENSOR_9_TPC5_EML_TPC_CFG_SECTION 0x3800 4590#define mmKERNEL_TENSOR_10_TPC5_EML_TPC_CFG_BASE 0x7FFFA41630ull 4591#define KERNEL_TENSOR_10_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4592#define KERNEL_TENSOR_10_TPC5_EML_TPC_CFG_SECTION 0x3800 4593#define mmKERNEL_TENSOR_11_TPC5_EML_TPC_CFG_BASE 0x7FFFA41668ull 4594#define KERNEL_TENSOR_11_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4595#define KERNEL_TENSOR_11_TPC5_EML_TPC_CFG_SECTION 0x3800 4596#define mmKERNEL_TENSOR_12_TPC5_EML_TPC_CFG_BASE 0x7FFFA416A0ull 4597#define KERNEL_TENSOR_12_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4598#define KERNEL_TENSOR_12_TPC5_EML_TPC_CFG_SECTION 0x3800 4599#define mmKERNEL_TENSOR_13_TPC5_EML_TPC_CFG_BASE 0x7FFFA416D8ull 4600#define KERNEL_TENSOR_13_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4601#define KERNEL_TENSOR_13_TPC5_EML_TPC_CFG_SECTION 0x3800 4602#define mmKERNEL_TENSOR_14_TPC5_EML_TPC_CFG_BASE 0x7FFFA41710ull 4603#define KERNEL_TENSOR_14_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4604#define KERNEL_TENSOR_14_TPC5_EML_TPC_CFG_SECTION 0x3800 4605#define mmKERNEL_TENSOR_15_TPC5_EML_TPC_CFG_BASE 0x7FFFA41748ull 4606#define KERNEL_TENSOR_15_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4607#define KERNEL_TENSOR_15_TPC5_EML_TPC_CFG_SECTION 0x3800 4608#define mmKERNEL_SYNC_OBJECT_TPC5_EML_TPC_CFG_BASE 0x7FFFA41780ull 4609#define KERNEL_SYNC_OBJECT_TPC5_EML_TPC_CFG_MAX_OFFSET 0x8000 4610#define KERNEL_SYNC_OBJECT_TPC5_EML_TPC_CFG_SECTION 0x8000 4611#define mmKERNEL_TPC5_EML_TPC_CFG_BASE 0x7FFFA41788ull 4612#define KERNEL_TPC5_EML_TPC_CFG_MAX_OFFSET 0xB800 4613#define KERNEL_TPC5_EML_TPC_CFG_SECTION 0x2780 4614#define mmQM_TENSOR_0_TPC5_EML_TPC_CFG_BASE 0x7FFFA41A00ull 4615#define QM_TENSOR_0_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4616#define QM_TENSOR_0_TPC5_EML_TPC_CFG_SECTION 0x3800 4617#define mmQM_TENSOR_1_TPC5_EML_TPC_CFG_BASE 0x7FFFA41A38ull 4618#define QM_TENSOR_1_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4619#define QM_TENSOR_1_TPC5_EML_TPC_CFG_SECTION 0x3800 4620#define mmQM_TENSOR_2_TPC5_EML_TPC_CFG_BASE 0x7FFFA41A70ull 4621#define QM_TENSOR_2_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4622#define QM_TENSOR_2_TPC5_EML_TPC_CFG_SECTION 0x3800 4623#define mmQM_TENSOR_3_TPC5_EML_TPC_CFG_BASE 0x7FFFA41AA8ull 4624#define QM_TENSOR_3_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4625#define QM_TENSOR_3_TPC5_EML_TPC_CFG_SECTION 0x3800 4626#define mmQM_TENSOR_4_TPC5_EML_TPC_CFG_BASE 0x7FFFA41AE0ull 4627#define QM_TENSOR_4_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4628#define QM_TENSOR_4_TPC5_EML_TPC_CFG_SECTION 0x3800 4629#define mmQM_TENSOR_5_TPC5_EML_TPC_CFG_BASE 0x7FFFA41B18ull 4630#define QM_TENSOR_5_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4631#define QM_TENSOR_5_TPC5_EML_TPC_CFG_SECTION 0x3800 4632#define mmQM_TENSOR_6_TPC5_EML_TPC_CFG_BASE 0x7FFFA41B50ull 4633#define QM_TENSOR_6_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4634#define QM_TENSOR_6_TPC5_EML_TPC_CFG_SECTION 0x3800 4635#define mmQM_TENSOR_7_TPC5_EML_TPC_CFG_BASE 0x7FFFA41B88ull 4636#define QM_TENSOR_7_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4637#define QM_TENSOR_7_TPC5_EML_TPC_CFG_SECTION 0x3800 4638#define mmQM_TENSOR_8_TPC5_EML_TPC_CFG_BASE 0x7FFFA41BC0ull 4639#define QM_TENSOR_8_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4640#define QM_TENSOR_8_TPC5_EML_TPC_CFG_SECTION 0x3800 4641#define mmQM_TENSOR_9_TPC5_EML_TPC_CFG_BASE 0x7FFFA41BF8ull 4642#define QM_TENSOR_9_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4643#define QM_TENSOR_9_TPC5_EML_TPC_CFG_SECTION 0x3800 4644#define mmQM_TENSOR_10_TPC5_EML_TPC_CFG_BASE 0x7FFFA41C30ull 4645#define QM_TENSOR_10_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4646#define QM_TENSOR_10_TPC5_EML_TPC_CFG_SECTION 0x3800 4647#define mmQM_TENSOR_11_TPC5_EML_TPC_CFG_BASE 0x7FFFA41C68ull 4648#define QM_TENSOR_11_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4649#define QM_TENSOR_11_TPC5_EML_TPC_CFG_SECTION 0x3800 4650#define mmQM_TENSOR_12_TPC5_EML_TPC_CFG_BASE 0x7FFFA41CA0ull 4651#define QM_TENSOR_12_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4652#define QM_TENSOR_12_TPC5_EML_TPC_CFG_SECTION 0x3800 4653#define mmQM_TENSOR_13_TPC5_EML_TPC_CFG_BASE 0x7FFFA41CD8ull 4654#define QM_TENSOR_13_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4655#define QM_TENSOR_13_TPC5_EML_TPC_CFG_SECTION 0x3800 4656#define mmQM_TENSOR_14_TPC5_EML_TPC_CFG_BASE 0x7FFFA41D10ull 4657#define QM_TENSOR_14_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4658#define QM_TENSOR_14_TPC5_EML_TPC_CFG_SECTION 0x3800 4659#define mmQM_TENSOR_15_TPC5_EML_TPC_CFG_BASE 0x7FFFA41D48ull 4660#define QM_TENSOR_15_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4661#define QM_TENSOR_15_TPC5_EML_TPC_CFG_SECTION 0x3800 4662#define mmQM_SYNC_OBJECT_TPC5_EML_TPC_CFG_BASE 0x7FFFA41D80ull 4663#define QM_SYNC_OBJECT_TPC5_EML_TPC_CFG_MAX_OFFSET 0x8000 4664#define QM_SYNC_OBJECT_TPC5_EML_TPC_CFG_SECTION 0x8000 4665#define mmQM_TPC5_EML_TPC_CFG_BASE 0x7FFFA41D88ull 4666#define QM_TPC5_EML_TPC_CFG_MAX_OFFSET 0xB800 4667#define QM_TPC5_EML_TPC_CFG_SECTION 0x2780 4668#define mmTPC5_EML_TPC_QM_BASE 0x7FFFA42000ull 4669#define TPC5_EML_TPC_QM_MAX_OFFSET 0xD040 4670#define TPC5_EML_TPC_QM_SECTION 0x1BD000 4671#define mmTPC5_EML_CS_BASE 0x7FFFBFF000ull 4672#define TPC5_EML_CS_MAX_OFFSET 0x1000 4673#define TPC5_EML_CS_SECTION 0x1000 4674#define mmTPC6_ROM_TABLE_BASE 0x7FFFC00000ull 4675#define TPC6_ROM_TABLE_MAX_OFFSET 0x1000 4676#define TPC6_ROM_TABLE_SECTION 0x1000 4677#define mmTPC6_EML_SPMU_BASE 0x7FFFC01000ull 4678#define TPC6_EML_SPMU_MAX_OFFSET 0x1000 4679#define TPC6_EML_SPMU_SECTION 0x1000 4680#define mmTPC6_EML_ETF_BASE 0x7FFFC02000ull 4681#define TPC6_EML_ETF_MAX_OFFSET 0x1000 4682#define TPC6_EML_ETF_SECTION 0x1000 4683#define mmTPC6_EML_STM_BASE 0x7FFFC03000ull 4684#define TPC6_EML_STM_MAX_OFFSET 0x1000 4685#define TPC6_EML_STM_SECTION 0x2000 4686#define mmTPC6_EML_CTI_BASE 0x7FFFC05000ull 4687#define TPC6_EML_CTI_MAX_OFFSET 0x1000 4688#define TPC6_EML_CTI_SECTION 0x1000 4689#define mmTPC6_EML_FUNNEL_BASE 0x7FFFC06000ull 4690#define TPC6_EML_FUNNEL_MAX_OFFSET 0x1000 4691#define TPC6_EML_FUNNEL_SECTION 0x1000 4692#define mmTPC6_EML_BUSMON_0_BASE 0x7FFFC07000ull 4693#define TPC6_EML_BUSMON_0_MAX_OFFSET 0x1000 4694#define TPC6_EML_BUSMON_0_SECTION 0x1000 4695#define mmTPC6_EML_BUSMON_1_BASE 0x7FFFC08000ull 4696#define TPC6_EML_BUSMON_1_MAX_OFFSET 0x1000 4697#define TPC6_EML_BUSMON_1_SECTION 0x1000 4698#define mmTPC6_EML_BUSMON_2_BASE 0x7FFFC09000ull 4699#define TPC6_EML_BUSMON_2_MAX_OFFSET 0x1000 4700#define TPC6_EML_BUSMON_2_SECTION 0x1000 4701#define mmTPC6_EML_BUSMON_3_BASE 0x7FFFC0A000ull 4702#define TPC6_EML_BUSMON_3_MAX_OFFSET 0x1000 4703#define TPC6_EML_BUSMON_3_SECTION 0x36000 4704#define mmTPC6_EML_CFG_BASE 0x7FFFC40000ull 4705#define TPC6_EML_CFG_MAX_OFFSET 0x3380 4706#define TPC6_EML_CFG_SECTION 0x1000 4707#define mmTPC6_EML_TPC_CFG_BASE 0x7FFFC41000ull 4708#define TPC6_EML_TPC_CFG_MAX_OFFSET 0xE400 4709#define TPC6_EML_TPC_CFG_SECTION 0x4000 4710#define mmKERNEL_TENSOR_0_TPC6_EML_TPC_CFG_BASE 0x7FFFC41400ull 4711#define KERNEL_TENSOR_0_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4712#define KERNEL_TENSOR_0_TPC6_EML_TPC_CFG_SECTION 0x3800 4713#define mmKERNEL_TENSOR_1_TPC6_EML_TPC_CFG_BASE 0x7FFFC41438ull 4714#define KERNEL_TENSOR_1_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4715#define KERNEL_TENSOR_1_TPC6_EML_TPC_CFG_SECTION 0x3800 4716#define mmKERNEL_TENSOR_2_TPC6_EML_TPC_CFG_BASE 0x7FFFC41470ull 4717#define KERNEL_TENSOR_2_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4718#define KERNEL_TENSOR_2_TPC6_EML_TPC_CFG_SECTION 0x3800 4719#define mmKERNEL_TENSOR_3_TPC6_EML_TPC_CFG_BASE 0x7FFFC414A8ull 4720#define KERNEL_TENSOR_3_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4721#define KERNEL_TENSOR_3_TPC6_EML_TPC_CFG_SECTION 0x3800 4722#define mmKERNEL_TENSOR_4_TPC6_EML_TPC_CFG_BASE 0x7FFFC414E0ull 4723#define KERNEL_TENSOR_4_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4724#define KERNEL_TENSOR_4_TPC6_EML_TPC_CFG_SECTION 0x3800 4725#define mmKERNEL_TENSOR_5_TPC6_EML_TPC_CFG_BASE 0x7FFFC41518ull 4726#define KERNEL_TENSOR_5_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4727#define KERNEL_TENSOR_5_TPC6_EML_TPC_CFG_SECTION 0x3800 4728#define mmKERNEL_TENSOR_6_TPC6_EML_TPC_CFG_BASE 0x7FFFC41550ull 4729#define KERNEL_TENSOR_6_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4730#define KERNEL_TENSOR_6_TPC6_EML_TPC_CFG_SECTION 0x3800 4731#define mmKERNEL_TENSOR_7_TPC6_EML_TPC_CFG_BASE 0x7FFFC41588ull 4732#define KERNEL_TENSOR_7_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4733#define KERNEL_TENSOR_7_TPC6_EML_TPC_CFG_SECTION 0x3800 4734#define mmKERNEL_TENSOR_8_TPC6_EML_TPC_CFG_BASE 0x7FFFC415C0ull 4735#define KERNEL_TENSOR_8_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4736#define KERNEL_TENSOR_8_TPC6_EML_TPC_CFG_SECTION 0x3800 4737#define mmKERNEL_TENSOR_9_TPC6_EML_TPC_CFG_BASE 0x7FFFC415F8ull 4738#define KERNEL_TENSOR_9_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4739#define KERNEL_TENSOR_9_TPC6_EML_TPC_CFG_SECTION 0x3800 4740#define mmKERNEL_TENSOR_10_TPC6_EML_TPC_CFG_BASE 0x7FFFC41630ull 4741#define KERNEL_TENSOR_10_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4742#define KERNEL_TENSOR_10_TPC6_EML_TPC_CFG_SECTION 0x3800 4743#define mmKERNEL_TENSOR_11_TPC6_EML_TPC_CFG_BASE 0x7FFFC41668ull 4744#define KERNEL_TENSOR_11_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4745#define KERNEL_TENSOR_11_TPC6_EML_TPC_CFG_SECTION 0x3800 4746#define mmKERNEL_TENSOR_12_TPC6_EML_TPC_CFG_BASE 0x7FFFC416A0ull 4747#define KERNEL_TENSOR_12_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4748#define KERNEL_TENSOR_12_TPC6_EML_TPC_CFG_SECTION 0x3800 4749#define mmKERNEL_TENSOR_13_TPC6_EML_TPC_CFG_BASE 0x7FFFC416D8ull 4750#define KERNEL_TENSOR_13_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4751#define KERNEL_TENSOR_13_TPC6_EML_TPC_CFG_SECTION 0x3800 4752#define mmKERNEL_TENSOR_14_TPC6_EML_TPC_CFG_BASE 0x7FFFC41710ull 4753#define KERNEL_TENSOR_14_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4754#define KERNEL_TENSOR_14_TPC6_EML_TPC_CFG_SECTION 0x3800 4755#define mmKERNEL_TENSOR_15_TPC6_EML_TPC_CFG_BASE 0x7FFFC41748ull 4756#define KERNEL_TENSOR_15_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4757#define KERNEL_TENSOR_15_TPC6_EML_TPC_CFG_SECTION 0x3800 4758#define mmKERNEL_SYNC_OBJECT_TPC6_EML_TPC_CFG_BASE 0x7FFFC41780ull 4759#define KERNEL_SYNC_OBJECT_TPC6_EML_TPC_CFG_MAX_OFFSET 0x8000 4760#define KERNEL_SYNC_OBJECT_TPC6_EML_TPC_CFG_SECTION 0x8000 4761#define mmKERNEL_TPC6_EML_TPC_CFG_BASE 0x7FFFC41788ull 4762#define KERNEL_TPC6_EML_TPC_CFG_MAX_OFFSET 0xB800 4763#define KERNEL_TPC6_EML_TPC_CFG_SECTION 0x2780 4764#define mmQM_TENSOR_0_TPC6_EML_TPC_CFG_BASE 0x7FFFC41A00ull 4765#define QM_TENSOR_0_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4766#define QM_TENSOR_0_TPC6_EML_TPC_CFG_SECTION 0x3800 4767#define mmQM_TENSOR_1_TPC6_EML_TPC_CFG_BASE 0x7FFFC41A38ull 4768#define QM_TENSOR_1_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4769#define QM_TENSOR_1_TPC6_EML_TPC_CFG_SECTION 0x3800 4770#define mmQM_TENSOR_2_TPC6_EML_TPC_CFG_BASE 0x7FFFC41A70ull 4771#define QM_TENSOR_2_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4772#define QM_TENSOR_2_TPC6_EML_TPC_CFG_SECTION 0x3800 4773#define mmQM_TENSOR_3_TPC6_EML_TPC_CFG_BASE 0x7FFFC41AA8ull 4774#define QM_TENSOR_3_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4775#define QM_TENSOR_3_TPC6_EML_TPC_CFG_SECTION 0x3800 4776#define mmQM_TENSOR_4_TPC6_EML_TPC_CFG_BASE 0x7FFFC41AE0ull 4777#define QM_TENSOR_4_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4778#define QM_TENSOR_4_TPC6_EML_TPC_CFG_SECTION 0x3800 4779#define mmQM_TENSOR_5_TPC6_EML_TPC_CFG_BASE 0x7FFFC41B18ull 4780#define QM_TENSOR_5_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4781#define QM_TENSOR_5_TPC6_EML_TPC_CFG_SECTION 0x3800 4782#define mmQM_TENSOR_6_TPC6_EML_TPC_CFG_BASE 0x7FFFC41B50ull 4783#define QM_TENSOR_6_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4784#define QM_TENSOR_6_TPC6_EML_TPC_CFG_SECTION 0x3800 4785#define mmQM_TENSOR_7_TPC6_EML_TPC_CFG_BASE 0x7FFFC41B88ull 4786#define QM_TENSOR_7_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4787#define QM_TENSOR_7_TPC6_EML_TPC_CFG_SECTION 0x3800 4788#define mmQM_TENSOR_8_TPC6_EML_TPC_CFG_BASE 0x7FFFC41BC0ull 4789#define QM_TENSOR_8_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4790#define QM_TENSOR_8_TPC6_EML_TPC_CFG_SECTION 0x3800 4791#define mmQM_TENSOR_9_TPC6_EML_TPC_CFG_BASE 0x7FFFC41BF8ull 4792#define QM_TENSOR_9_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4793#define QM_TENSOR_9_TPC6_EML_TPC_CFG_SECTION 0x3800 4794#define mmQM_TENSOR_10_TPC6_EML_TPC_CFG_BASE 0x7FFFC41C30ull 4795#define QM_TENSOR_10_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4796#define QM_TENSOR_10_TPC6_EML_TPC_CFG_SECTION 0x3800 4797#define mmQM_TENSOR_11_TPC6_EML_TPC_CFG_BASE 0x7FFFC41C68ull 4798#define QM_TENSOR_11_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4799#define QM_TENSOR_11_TPC6_EML_TPC_CFG_SECTION 0x3800 4800#define mmQM_TENSOR_12_TPC6_EML_TPC_CFG_BASE 0x7FFFC41CA0ull 4801#define QM_TENSOR_12_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4802#define QM_TENSOR_12_TPC6_EML_TPC_CFG_SECTION 0x3800 4803#define mmQM_TENSOR_13_TPC6_EML_TPC_CFG_BASE 0x7FFFC41CD8ull 4804#define QM_TENSOR_13_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4805#define QM_TENSOR_13_TPC6_EML_TPC_CFG_SECTION 0x3800 4806#define mmQM_TENSOR_14_TPC6_EML_TPC_CFG_BASE 0x7FFFC41D10ull 4807#define QM_TENSOR_14_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4808#define QM_TENSOR_14_TPC6_EML_TPC_CFG_SECTION 0x3800 4809#define mmQM_TENSOR_15_TPC6_EML_TPC_CFG_BASE 0x7FFFC41D48ull 4810#define QM_TENSOR_15_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4811#define QM_TENSOR_15_TPC6_EML_TPC_CFG_SECTION 0x3800 4812#define mmQM_SYNC_OBJECT_TPC6_EML_TPC_CFG_BASE 0x7FFFC41D80ull 4813#define QM_SYNC_OBJECT_TPC6_EML_TPC_CFG_MAX_OFFSET 0x8000 4814#define QM_SYNC_OBJECT_TPC6_EML_TPC_CFG_SECTION 0x8000 4815#define mmQM_TPC6_EML_TPC_CFG_BASE 0x7FFFC41D88ull 4816#define QM_TPC6_EML_TPC_CFG_MAX_OFFSET 0xB800 4817#define QM_TPC6_EML_TPC_CFG_SECTION 0x2780 4818#define mmTPC6_EML_TPC_QM_BASE 0x7FFFC42000ull 4819#define TPC6_EML_TPC_QM_MAX_OFFSET 0xD040 4820#define TPC6_EML_TPC_QM_SECTION 0x1BD000 4821#define mmTPC6_EML_CS_BASE 0x7FFFDFF000ull 4822#define TPC6_EML_CS_MAX_OFFSET 0x1000 4823#define TPC6_EML_CS_SECTION 0x1000 4824#define mmTPC7_ROM_TABLE_BASE 0x7FFFE00000ull 4825#define TPC7_ROM_TABLE_MAX_OFFSET 0x1000 4826#define TPC7_ROM_TABLE_SECTION 0x1000 4827#define mmTPC7_EML_SPMU_BASE 0x7FFFE01000ull 4828#define TPC7_EML_SPMU_MAX_OFFSET 0x1000 4829#define TPC7_EML_SPMU_SECTION 0x1000 4830#define mmTPC7_EML_ETF_BASE 0x7FFFE02000ull 4831#define TPC7_EML_ETF_MAX_OFFSET 0x1000 4832#define TPC7_EML_ETF_SECTION 0x1000 4833#define mmTPC7_EML_STM_BASE 0x7FFFE03000ull 4834#define TPC7_EML_STM_MAX_OFFSET 0x1000 4835#define TPC7_EML_STM_SECTION 0x2000 4836#define mmTPC7_EML_CTI_BASE 0x7FFFE05000ull 4837#define TPC7_EML_CTI_MAX_OFFSET 0x1000 4838#define TPC7_EML_CTI_SECTION 0x1000 4839#define mmTPC7_EML_FUNNEL_BASE 0x7FFFE06000ull 4840#define TPC7_EML_FUNNEL_MAX_OFFSET 0x1000 4841#define TPC7_EML_FUNNEL_SECTION 0x1000 4842#define mmTPC7_EML_BUSMON_0_BASE 0x7FFFE07000ull 4843#define TPC7_EML_BUSMON_0_MAX_OFFSET 0x1000 4844#define TPC7_EML_BUSMON_0_SECTION 0x1000 4845#define mmTPC7_EML_BUSMON_1_BASE 0x7FFFE08000ull 4846#define TPC7_EML_BUSMON_1_MAX_OFFSET 0x1000 4847#define TPC7_EML_BUSMON_1_SECTION 0x1000 4848#define mmTPC7_EML_BUSMON_2_BASE 0x7FFFE09000ull 4849#define TPC7_EML_BUSMON_2_MAX_OFFSET 0x1000 4850#define TPC7_EML_BUSMON_2_SECTION 0x1000 4851#define mmTPC7_EML_BUSMON_3_BASE 0x7FFFE0A000ull 4852#define TPC7_EML_BUSMON_3_MAX_OFFSET 0x1000 4853#define TPC7_EML_BUSMON_3_SECTION 0x36000 4854#define mmTPC7_EML_CFG_BASE 0x7FFFE40000ull 4855#define TPC7_EML_CFG_MAX_OFFSET 0x3380 4856#define TPC7_EML_CFG_SECTION 0x1000 4857#define mmTPC7_EML_TPC_CFG_BASE 0x7FFFE41000ull 4858#define TPC7_EML_TPC_CFG_MAX_OFFSET 0xE400 4859#define TPC7_EML_TPC_CFG_SECTION 0x4000 4860#define mmKERNEL_TENSOR_0_TPC7_EML_TPC_CFG_BASE 0x7FFFE41400ull 4861#define KERNEL_TENSOR_0_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4862#define KERNEL_TENSOR_0_TPC7_EML_TPC_CFG_SECTION 0x3800 4863#define mmKERNEL_TENSOR_1_TPC7_EML_TPC_CFG_BASE 0x7FFFE41438ull 4864#define KERNEL_TENSOR_1_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4865#define KERNEL_TENSOR_1_TPC7_EML_TPC_CFG_SECTION 0x3800 4866#define mmKERNEL_TENSOR_2_TPC7_EML_TPC_CFG_BASE 0x7FFFE41470ull 4867#define KERNEL_TENSOR_2_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4868#define KERNEL_TENSOR_2_TPC7_EML_TPC_CFG_SECTION 0x3800 4869#define mmKERNEL_TENSOR_3_TPC7_EML_TPC_CFG_BASE 0x7FFFE414A8ull 4870#define KERNEL_TENSOR_3_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4871#define KERNEL_TENSOR_3_TPC7_EML_TPC_CFG_SECTION 0x3800 4872#define mmKERNEL_TENSOR_4_TPC7_EML_TPC_CFG_BASE 0x7FFFE414E0ull 4873#define KERNEL_TENSOR_4_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4874#define KERNEL_TENSOR_4_TPC7_EML_TPC_CFG_SECTION 0x3800 4875#define mmKERNEL_TENSOR_5_TPC7_EML_TPC_CFG_BASE 0x7FFFE41518ull 4876#define KERNEL_TENSOR_5_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4877#define KERNEL_TENSOR_5_TPC7_EML_TPC_CFG_SECTION 0x3800 4878#define mmKERNEL_TENSOR_6_TPC7_EML_TPC_CFG_BASE 0x7FFFE41550ull 4879#define KERNEL_TENSOR_6_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4880#define KERNEL_TENSOR_6_TPC7_EML_TPC_CFG_SECTION 0x3800 4881#define mmKERNEL_TENSOR_7_TPC7_EML_TPC_CFG_BASE 0x7FFFE41588ull 4882#define KERNEL_TENSOR_7_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4883#define KERNEL_TENSOR_7_TPC7_EML_TPC_CFG_SECTION 0x3800 4884#define mmKERNEL_TENSOR_8_TPC7_EML_TPC_CFG_BASE 0x7FFFE415C0ull 4885#define KERNEL_TENSOR_8_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4886#define KERNEL_TENSOR_8_TPC7_EML_TPC_CFG_SECTION 0x3800 4887#define mmKERNEL_TENSOR_9_TPC7_EML_TPC_CFG_BASE 0x7FFFE415F8ull 4888#define KERNEL_TENSOR_9_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4889#define KERNEL_TENSOR_9_TPC7_EML_TPC_CFG_SECTION 0x3800 4890#define mmKERNEL_TENSOR_10_TPC7_EML_TPC_CFG_BASE 0x7FFFE41630ull 4891#define KERNEL_TENSOR_10_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4892#define KERNEL_TENSOR_10_TPC7_EML_TPC_CFG_SECTION 0x3800 4893#define mmKERNEL_TENSOR_11_TPC7_EML_TPC_CFG_BASE 0x7FFFE41668ull 4894#define KERNEL_TENSOR_11_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4895#define KERNEL_TENSOR_11_TPC7_EML_TPC_CFG_SECTION 0x3800 4896#define mmKERNEL_TENSOR_12_TPC7_EML_TPC_CFG_BASE 0x7FFFE416A0ull 4897#define KERNEL_TENSOR_12_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4898#define KERNEL_TENSOR_12_TPC7_EML_TPC_CFG_SECTION 0x3800 4899#define mmKERNEL_TENSOR_13_TPC7_EML_TPC_CFG_BASE 0x7FFFE416D8ull 4900#define KERNEL_TENSOR_13_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4901#define KERNEL_TENSOR_13_TPC7_EML_TPC_CFG_SECTION 0x3800 4902#define mmKERNEL_TENSOR_14_TPC7_EML_TPC_CFG_BASE 0x7FFFE41710ull 4903#define KERNEL_TENSOR_14_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4904#define KERNEL_TENSOR_14_TPC7_EML_TPC_CFG_SECTION 0x3800 4905#define mmKERNEL_TENSOR_15_TPC7_EML_TPC_CFG_BASE 0x7FFFE41748ull 4906#define KERNEL_TENSOR_15_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4907#define KERNEL_TENSOR_15_TPC7_EML_TPC_CFG_SECTION 0x3800 4908#define mmKERNEL_SYNC_OBJECT_TPC7_EML_TPC_CFG_BASE 0x7FFFE41780ull 4909#define KERNEL_SYNC_OBJECT_TPC7_EML_TPC_CFG_MAX_OFFSET 0x8000 4910#define KERNEL_SYNC_OBJECT_TPC7_EML_TPC_CFG_SECTION 0x8000 4911#define mmKERNEL_TPC7_EML_TPC_CFG_BASE 0x7FFFE41788ull 4912#define KERNEL_TPC7_EML_TPC_CFG_MAX_OFFSET 0xB800 4913#define KERNEL_TPC7_EML_TPC_CFG_SECTION 0x2780 4914#define mmQM_TENSOR_0_TPC7_EML_TPC_CFG_BASE 0x7FFFE41A00ull 4915#define QM_TENSOR_0_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4916#define QM_TENSOR_0_TPC7_EML_TPC_CFG_SECTION 0x3800 4917#define mmQM_TENSOR_1_TPC7_EML_TPC_CFG_BASE 0x7FFFE41A38ull 4918#define QM_TENSOR_1_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4919#define QM_TENSOR_1_TPC7_EML_TPC_CFG_SECTION 0x3800 4920#define mmQM_TENSOR_2_TPC7_EML_TPC_CFG_BASE 0x7FFFE41A70ull 4921#define QM_TENSOR_2_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4922#define QM_TENSOR_2_TPC7_EML_TPC_CFG_SECTION 0x3800 4923#define mmQM_TENSOR_3_TPC7_EML_TPC_CFG_BASE 0x7FFFE41AA8ull 4924#define QM_TENSOR_3_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4925#define QM_TENSOR_3_TPC7_EML_TPC_CFG_SECTION 0x3800 4926#define mmQM_TENSOR_4_TPC7_EML_TPC_CFG_BASE 0x7FFFE41AE0ull 4927#define QM_TENSOR_4_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4928#define QM_TENSOR_4_TPC7_EML_TPC_CFG_SECTION 0x3800 4929#define mmQM_TENSOR_5_TPC7_EML_TPC_CFG_BASE 0x7FFFE41B18ull 4930#define QM_TENSOR_5_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4931#define QM_TENSOR_5_TPC7_EML_TPC_CFG_SECTION 0x3800 4932#define mmQM_TENSOR_6_TPC7_EML_TPC_CFG_BASE 0x7FFFE41B50ull 4933#define QM_TENSOR_6_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4934#define QM_TENSOR_6_TPC7_EML_TPC_CFG_SECTION 0x3800 4935#define mmQM_TENSOR_7_TPC7_EML_TPC_CFG_BASE 0x7FFFE41B88ull 4936#define QM_TENSOR_7_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4937#define QM_TENSOR_7_TPC7_EML_TPC_CFG_SECTION 0x3800 4938#define mmQM_TENSOR_8_TPC7_EML_TPC_CFG_BASE 0x7FFFE41BC0ull 4939#define QM_TENSOR_8_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4940#define QM_TENSOR_8_TPC7_EML_TPC_CFG_SECTION 0x3800 4941#define mmQM_TENSOR_9_TPC7_EML_TPC_CFG_BASE 0x7FFFE41BF8ull 4942#define QM_TENSOR_9_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4943#define QM_TENSOR_9_TPC7_EML_TPC_CFG_SECTION 0x3800 4944#define mmQM_TENSOR_10_TPC7_EML_TPC_CFG_BASE 0x7FFFE41C30ull 4945#define QM_TENSOR_10_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4946#define QM_TENSOR_10_TPC7_EML_TPC_CFG_SECTION 0x3800 4947#define mmQM_TENSOR_11_TPC7_EML_TPC_CFG_BASE 0x7FFFE41C68ull 4948#define QM_TENSOR_11_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4949#define QM_TENSOR_11_TPC7_EML_TPC_CFG_SECTION 0x3800 4950#define mmQM_TENSOR_12_TPC7_EML_TPC_CFG_BASE 0x7FFFE41CA0ull 4951#define QM_TENSOR_12_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4952#define QM_TENSOR_12_TPC7_EML_TPC_CFG_SECTION 0x3800 4953#define mmQM_TENSOR_13_TPC7_EML_TPC_CFG_BASE 0x7FFFE41CD8ull 4954#define QM_TENSOR_13_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4955#define QM_TENSOR_13_TPC7_EML_TPC_CFG_SECTION 0x3800 4956#define mmQM_TENSOR_14_TPC7_EML_TPC_CFG_BASE 0x7FFFE41D10ull 4957#define QM_TENSOR_14_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4958#define QM_TENSOR_14_TPC7_EML_TPC_CFG_SECTION 0x3800 4959#define mmQM_TENSOR_15_TPC7_EML_TPC_CFG_BASE 0x7FFFE41D48ull 4960#define QM_TENSOR_15_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4961#define QM_TENSOR_15_TPC7_EML_TPC_CFG_SECTION 0x3800 4962#define mmQM_SYNC_OBJECT_TPC7_EML_TPC_CFG_BASE 0x7FFFE41D80ull 4963#define QM_SYNC_OBJECT_TPC7_EML_TPC_CFG_MAX_OFFSET 0x8000 4964#define QM_SYNC_OBJECT_TPC7_EML_TPC_CFG_SECTION 0x8000 4965#define mmQM_TPC7_EML_TPC_CFG_BASE 0x7FFFE41D88ull 4966#define QM_TPC7_EML_TPC_CFG_MAX_OFFSET 0xB800 4967#define QM_TPC7_EML_TPC_CFG_SECTION 0x2780 4968#define mmTPC7_EML_TPC_QM_BASE 0x7FFFE42000ull 4969#define TPC7_EML_TPC_QM_MAX_OFFSET 0xD040 4970#define TPC7_EML_TPC_QM_SECTION 0x1BD000 4971#define mmTPC7_EML_CS_BASE 0x7FFFFFF000ull 4972#define TPC7_EML_CS_MAX_OFFSET 0x1000 4973 4974#endif /* GAUDI_BLOCKS_H_ */