nic4_qm1_regs.h (32573B)
1/* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2018 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8/************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13#ifndef ASIC_REG_NIC4_QM1_REGS_H_ 14#define ASIC_REG_NIC4_QM1_REGS_H_ 15 16/* 17 ***************************************** 18 * NIC4_QM1 (Prototype: QMAN) 19 ***************************************** 20 */ 21 22#define mmNIC4_QM1_GLBL_CFG0 0xDE2000 23 24#define mmNIC4_QM1_GLBL_CFG1 0xDE2004 25 26#define mmNIC4_QM1_GLBL_PROT 0xDE2008 27 28#define mmNIC4_QM1_GLBL_ERR_CFG 0xDE200C 29 30#define mmNIC4_QM1_GLBL_SECURE_PROPS_0 0xDE2010 31 32#define mmNIC4_QM1_GLBL_SECURE_PROPS_1 0xDE2014 33 34#define mmNIC4_QM1_GLBL_SECURE_PROPS_2 0xDE2018 35 36#define mmNIC4_QM1_GLBL_SECURE_PROPS_3 0xDE201C 37 38#define mmNIC4_QM1_GLBL_SECURE_PROPS_4 0xDE2020 39 40#define mmNIC4_QM1_GLBL_NON_SECURE_PROPS_0 0xDE2024 41 42#define mmNIC4_QM1_GLBL_NON_SECURE_PROPS_1 0xDE2028 43 44#define mmNIC4_QM1_GLBL_NON_SECURE_PROPS_2 0xDE202C 45 46#define mmNIC4_QM1_GLBL_NON_SECURE_PROPS_3 0xDE2030 47 48#define mmNIC4_QM1_GLBL_NON_SECURE_PROPS_4 0xDE2034 49 50#define mmNIC4_QM1_GLBL_STS0 0xDE2038 51 52#define mmNIC4_QM1_GLBL_STS1_0 0xDE2040 53 54#define mmNIC4_QM1_GLBL_STS1_1 0xDE2044 55 56#define mmNIC4_QM1_GLBL_STS1_2 0xDE2048 57 58#define mmNIC4_QM1_GLBL_STS1_3 0xDE204C 59 60#define mmNIC4_QM1_GLBL_STS1_4 0xDE2050 61 62#define mmNIC4_QM1_GLBL_MSG_EN_0 0xDE2054 63 64#define mmNIC4_QM1_GLBL_MSG_EN_1 0xDE2058 65 66#define mmNIC4_QM1_GLBL_MSG_EN_2 0xDE205C 67 68#define mmNIC4_QM1_GLBL_MSG_EN_3 0xDE2060 69 70#define mmNIC4_QM1_GLBL_MSG_EN_4 0xDE2068 71 72#define mmNIC4_QM1_PQ_BASE_LO_0 0xDE2070 73 74#define mmNIC4_QM1_PQ_BASE_LO_1 0xDE2074 75 76#define mmNIC4_QM1_PQ_BASE_LO_2 0xDE2078 77 78#define mmNIC4_QM1_PQ_BASE_LO_3 0xDE207C 79 80#define mmNIC4_QM1_PQ_BASE_HI_0 0xDE2080 81 82#define mmNIC4_QM1_PQ_BASE_HI_1 0xDE2084 83 84#define mmNIC4_QM1_PQ_BASE_HI_2 0xDE2088 85 86#define mmNIC4_QM1_PQ_BASE_HI_3 0xDE208C 87 88#define mmNIC4_QM1_PQ_SIZE_0 0xDE2090 89 90#define mmNIC4_QM1_PQ_SIZE_1 0xDE2094 91 92#define mmNIC4_QM1_PQ_SIZE_2 0xDE2098 93 94#define mmNIC4_QM1_PQ_SIZE_3 0xDE209C 95 96#define mmNIC4_QM1_PQ_PI_0 0xDE20A0 97 98#define mmNIC4_QM1_PQ_PI_1 0xDE20A4 99 100#define mmNIC4_QM1_PQ_PI_2 0xDE20A8 101 102#define mmNIC4_QM1_PQ_PI_3 0xDE20AC 103 104#define mmNIC4_QM1_PQ_CI_0 0xDE20B0 105 106#define mmNIC4_QM1_PQ_CI_1 0xDE20B4 107 108#define mmNIC4_QM1_PQ_CI_2 0xDE20B8 109 110#define mmNIC4_QM1_PQ_CI_3 0xDE20BC 111 112#define mmNIC4_QM1_PQ_CFG0_0 0xDE20C0 113 114#define mmNIC4_QM1_PQ_CFG0_1 0xDE20C4 115 116#define mmNIC4_QM1_PQ_CFG0_2 0xDE20C8 117 118#define mmNIC4_QM1_PQ_CFG0_3 0xDE20CC 119 120#define mmNIC4_QM1_PQ_CFG1_0 0xDE20D0 121 122#define mmNIC4_QM1_PQ_CFG1_1 0xDE20D4 123 124#define mmNIC4_QM1_PQ_CFG1_2 0xDE20D8 125 126#define mmNIC4_QM1_PQ_CFG1_3 0xDE20DC 127 128#define mmNIC4_QM1_PQ_ARUSER_31_11_0 0xDE20E0 129 130#define mmNIC4_QM1_PQ_ARUSER_31_11_1 0xDE20E4 131 132#define mmNIC4_QM1_PQ_ARUSER_31_11_2 0xDE20E8 133 134#define mmNIC4_QM1_PQ_ARUSER_31_11_3 0xDE20EC 135 136#define mmNIC4_QM1_PQ_STS0_0 0xDE20F0 137 138#define mmNIC4_QM1_PQ_STS0_1 0xDE20F4 139 140#define mmNIC4_QM1_PQ_STS0_2 0xDE20F8 141 142#define mmNIC4_QM1_PQ_STS0_3 0xDE20FC 143 144#define mmNIC4_QM1_PQ_STS1_0 0xDE2100 145 146#define mmNIC4_QM1_PQ_STS1_1 0xDE2104 147 148#define mmNIC4_QM1_PQ_STS1_2 0xDE2108 149 150#define mmNIC4_QM1_PQ_STS1_3 0xDE210C 151 152#define mmNIC4_QM1_CQ_CFG0_0 0xDE2110 153 154#define mmNIC4_QM1_CQ_CFG0_1 0xDE2114 155 156#define mmNIC4_QM1_CQ_CFG0_2 0xDE2118 157 158#define mmNIC4_QM1_CQ_CFG0_3 0xDE211C 159 160#define mmNIC4_QM1_CQ_CFG0_4 0xDE2120 161 162#define mmNIC4_QM1_CQ_CFG1_0 0xDE2124 163 164#define mmNIC4_QM1_CQ_CFG1_1 0xDE2128 165 166#define mmNIC4_QM1_CQ_CFG1_2 0xDE212C 167 168#define mmNIC4_QM1_CQ_CFG1_3 0xDE2130 169 170#define mmNIC4_QM1_CQ_CFG1_4 0xDE2134 171 172#define mmNIC4_QM1_CQ_ARUSER_31_11_0 0xDE2138 173 174#define mmNIC4_QM1_CQ_ARUSER_31_11_1 0xDE213C 175 176#define mmNIC4_QM1_CQ_ARUSER_31_11_2 0xDE2140 177 178#define mmNIC4_QM1_CQ_ARUSER_31_11_3 0xDE2144 179 180#define mmNIC4_QM1_CQ_ARUSER_31_11_4 0xDE2148 181 182#define mmNIC4_QM1_CQ_STS0_0 0xDE214C 183 184#define mmNIC4_QM1_CQ_STS0_1 0xDE2150 185 186#define mmNIC4_QM1_CQ_STS0_2 0xDE2154 187 188#define mmNIC4_QM1_CQ_STS0_3 0xDE2158 189 190#define mmNIC4_QM1_CQ_STS0_4 0xDE215C 191 192#define mmNIC4_QM1_CQ_STS1_0 0xDE2160 193 194#define mmNIC4_QM1_CQ_STS1_1 0xDE2164 195 196#define mmNIC4_QM1_CQ_STS1_2 0xDE2168 197 198#define mmNIC4_QM1_CQ_STS1_3 0xDE216C 199 200#define mmNIC4_QM1_CQ_STS1_4 0xDE2170 201 202#define mmNIC4_QM1_CQ_PTR_LO_0 0xDE2174 203 204#define mmNIC4_QM1_CQ_PTR_HI_0 0xDE2178 205 206#define mmNIC4_QM1_CQ_TSIZE_0 0xDE217C 207 208#define mmNIC4_QM1_CQ_CTL_0 0xDE2180 209 210#define mmNIC4_QM1_CQ_PTR_LO_1 0xDE2184 211 212#define mmNIC4_QM1_CQ_PTR_HI_1 0xDE2188 213 214#define mmNIC4_QM1_CQ_TSIZE_1 0xDE218C 215 216#define mmNIC4_QM1_CQ_CTL_1 0xDE2190 217 218#define mmNIC4_QM1_CQ_PTR_LO_2 0xDE2194 219 220#define mmNIC4_QM1_CQ_PTR_HI_2 0xDE2198 221 222#define mmNIC4_QM1_CQ_TSIZE_2 0xDE219C 223 224#define mmNIC4_QM1_CQ_CTL_2 0xDE21A0 225 226#define mmNIC4_QM1_CQ_PTR_LO_3 0xDE21A4 227 228#define mmNIC4_QM1_CQ_PTR_HI_3 0xDE21A8 229 230#define mmNIC4_QM1_CQ_TSIZE_3 0xDE21AC 231 232#define mmNIC4_QM1_CQ_CTL_3 0xDE21B0 233 234#define mmNIC4_QM1_CQ_PTR_LO_4 0xDE21B4 235 236#define mmNIC4_QM1_CQ_PTR_HI_4 0xDE21B8 237 238#define mmNIC4_QM1_CQ_TSIZE_4 0xDE21BC 239 240#define mmNIC4_QM1_CQ_CTL_4 0xDE21C0 241 242#define mmNIC4_QM1_CQ_PTR_LO_STS_0 0xDE21C4 243 244#define mmNIC4_QM1_CQ_PTR_LO_STS_1 0xDE21C8 245 246#define mmNIC4_QM1_CQ_PTR_LO_STS_2 0xDE21CC 247 248#define mmNIC4_QM1_CQ_PTR_LO_STS_3 0xDE21D0 249 250#define mmNIC4_QM1_CQ_PTR_LO_STS_4 0xDE21D4 251 252#define mmNIC4_QM1_CQ_PTR_HI_STS_0 0xDE21D8 253 254#define mmNIC4_QM1_CQ_PTR_HI_STS_1 0xDE21DC 255 256#define mmNIC4_QM1_CQ_PTR_HI_STS_2 0xDE21E0 257 258#define mmNIC4_QM1_CQ_PTR_HI_STS_3 0xDE21E4 259 260#define mmNIC4_QM1_CQ_PTR_HI_STS_4 0xDE21E8 261 262#define mmNIC4_QM1_CQ_TSIZE_STS_0 0xDE21EC 263 264#define mmNIC4_QM1_CQ_TSIZE_STS_1 0xDE21F0 265 266#define mmNIC4_QM1_CQ_TSIZE_STS_2 0xDE21F4 267 268#define mmNIC4_QM1_CQ_TSIZE_STS_3 0xDE21F8 269 270#define mmNIC4_QM1_CQ_TSIZE_STS_4 0xDE21FC 271 272#define mmNIC4_QM1_CQ_CTL_STS_0 0xDE2200 273 274#define mmNIC4_QM1_CQ_CTL_STS_1 0xDE2204 275 276#define mmNIC4_QM1_CQ_CTL_STS_2 0xDE2208 277 278#define mmNIC4_QM1_CQ_CTL_STS_3 0xDE220C 279 280#define mmNIC4_QM1_CQ_CTL_STS_4 0xDE2210 281 282#define mmNIC4_QM1_CQ_IFIFO_CNT_0 0xDE2214 283 284#define mmNIC4_QM1_CQ_IFIFO_CNT_1 0xDE2218 285 286#define mmNIC4_QM1_CQ_IFIFO_CNT_2 0xDE221C 287 288#define mmNIC4_QM1_CQ_IFIFO_CNT_3 0xDE2220 289 290#define mmNIC4_QM1_CQ_IFIFO_CNT_4 0xDE2224 291 292#define mmNIC4_QM1_CP_MSG_BASE0_ADDR_LO_0 0xDE2228 293 294#define mmNIC4_QM1_CP_MSG_BASE0_ADDR_LO_1 0xDE222C 295 296#define mmNIC4_QM1_CP_MSG_BASE0_ADDR_LO_2 0xDE2230 297 298#define mmNIC4_QM1_CP_MSG_BASE0_ADDR_LO_3 0xDE2234 299 300#define mmNIC4_QM1_CP_MSG_BASE0_ADDR_LO_4 0xDE2238 301 302#define mmNIC4_QM1_CP_MSG_BASE0_ADDR_HI_0 0xDE223C 303 304#define mmNIC4_QM1_CP_MSG_BASE0_ADDR_HI_1 0xDE2240 305 306#define mmNIC4_QM1_CP_MSG_BASE0_ADDR_HI_2 0xDE2244 307 308#define mmNIC4_QM1_CP_MSG_BASE0_ADDR_HI_3 0xDE2248 309 310#define mmNIC4_QM1_CP_MSG_BASE0_ADDR_HI_4 0xDE224C 311 312#define mmNIC4_QM1_CP_MSG_BASE1_ADDR_LO_0 0xDE2250 313 314#define mmNIC4_QM1_CP_MSG_BASE1_ADDR_LO_1 0xDE2254 315 316#define mmNIC4_QM1_CP_MSG_BASE1_ADDR_LO_2 0xDE2258 317 318#define mmNIC4_QM1_CP_MSG_BASE1_ADDR_LO_3 0xDE225C 319 320#define mmNIC4_QM1_CP_MSG_BASE1_ADDR_LO_4 0xDE2260 321 322#define mmNIC4_QM1_CP_MSG_BASE1_ADDR_HI_0 0xDE2264 323 324#define mmNIC4_QM1_CP_MSG_BASE1_ADDR_HI_1 0xDE2268 325 326#define mmNIC4_QM1_CP_MSG_BASE1_ADDR_HI_2 0xDE226C 327 328#define mmNIC4_QM1_CP_MSG_BASE1_ADDR_HI_3 0xDE2270 329 330#define mmNIC4_QM1_CP_MSG_BASE1_ADDR_HI_4 0xDE2274 331 332#define mmNIC4_QM1_CP_MSG_BASE2_ADDR_LO_0 0xDE2278 333 334#define mmNIC4_QM1_CP_MSG_BASE2_ADDR_LO_1 0xDE227C 335 336#define mmNIC4_QM1_CP_MSG_BASE2_ADDR_LO_2 0xDE2280 337 338#define mmNIC4_QM1_CP_MSG_BASE2_ADDR_LO_3 0xDE2284 339 340#define mmNIC4_QM1_CP_MSG_BASE2_ADDR_LO_4 0xDE2288 341 342#define mmNIC4_QM1_CP_MSG_BASE2_ADDR_HI_0 0xDE228C 343 344#define mmNIC4_QM1_CP_MSG_BASE2_ADDR_HI_1 0xDE2290 345 346#define mmNIC4_QM1_CP_MSG_BASE2_ADDR_HI_2 0xDE2294 347 348#define mmNIC4_QM1_CP_MSG_BASE2_ADDR_HI_3 0xDE2298 349 350#define mmNIC4_QM1_CP_MSG_BASE2_ADDR_HI_4 0xDE229C 351 352#define mmNIC4_QM1_CP_MSG_BASE3_ADDR_LO_0 0xDE22A0 353 354#define mmNIC4_QM1_CP_MSG_BASE3_ADDR_LO_1 0xDE22A4 355 356#define mmNIC4_QM1_CP_MSG_BASE3_ADDR_LO_2 0xDE22A8 357 358#define mmNIC4_QM1_CP_MSG_BASE3_ADDR_LO_3 0xDE22AC 359 360#define mmNIC4_QM1_CP_MSG_BASE3_ADDR_LO_4 0xDE22B0 361 362#define mmNIC4_QM1_CP_MSG_BASE3_ADDR_HI_0 0xDE22B4 363 364#define mmNIC4_QM1_CP_MSG_BASE3_ADDR_HI_1 0xDE22B8 365 366#define mmNIC4_QM1_CP_MSG_BASE3_ADDR_HI_2 0xDE22BC 367 368#define mmNIC4_QM1_CP_MSG_BASE3_ADDR_HI_3 0xDE22C0 369 370#define mmNIC4_QM1_CP_MSG_BASE3_ADDR_HI_4 0xDE22C4 371 372#define mmNIC4_QM1_CP_LDMA_TSIZE_OFFSET_0 0xDE22C8 373 374#define mmNIC4_QM1_CP_LDMA_TSIZE_OFFSET_1 0xDE22CC 375 376#define mmNIC4_QM1_CP_LDMA_TSIZE_OFFSET_2 0xDE22D0 377 378#define mmNIC4_QM1_CP_LDMA_TSIZE_OFFSET_3 0xDE22D4 379 380#define mmNIC4_QM1_CP_LDMA_TSIZE_OFFSET_4 0xDE22D8 381 382#define mmNIC4_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xDE22E0 383 384#define mmNIC4_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xDE22E4 385 386#define mmNIC4_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xDE22E8 387 388#define mmNIC4_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xDE22EC 389 390#define mmNIC4_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xDE22F0 391 392#define mmNIC4_QM1_CP_LDMA_DST_BASE_LO_OFFSET_0 0xDE22F4 393 394#define mmNIC4_QM1_CP_LDMA_DST_BASE_LO_OFFSET_1 0xDE22F8 395 396#define mmNIC4_QM1_CP_LDMA_DST_BASE_LO_OFFSET_2 0xDE22FC 397 398#define mmNIC4_QM1_CP_LDMA_DST_BASE_LO_OFFSET_3 0xDE2300 399 400#define mmNIC4_QM1_CP_LDMA_DST_BASE_LO_OFFSET_4 0xDE2304 401 402#define mmNIC4_QM1_CP_FENCE0_RDATA_0 0xDE2308 403 404#define mmNIC4_QM1_CP_FENCE0_RDATA_1 0xDE230C 405 406#define mmNIC4_QM1_CP_FENCE0_RDATA_2 0xDE2310 407 408#define mmNIC4_QM1_CP_FENCE0_RDATA_3 0xDE2314 409 410#define mmNIC4_QM1_CP_FENCE0_RDATA_4 0xDE2318 411 412#define mmNIC4_QM1_CP_FENCE1_RDATA_0 0xDE231C 413 414#define mmNIC4_QM1_CP_FENCE1_RDATA_1 0xDE2320 415 416#define mmNIC4_QM1_CP_FENCE1_RDATA_2 0xDE2324 417 418#define mmNIC4_QM1_CP_FENCE1_RDATA_3 0xDE2328 419 420#define mmNIC4_QM1_CP_FENCE1_RDATA_4 0xDE232C 421 422#define mmNIC4_QM1_CP_FENCE2_RDATA_0 0xDE2330 423 424#define mmNIC4_QM1_CP_FENCE2_RDATA_1 0xDE2334 425 426#define mmNIC4_QM1_CP_FENCE2_RDATA_2 0xDE2338 427 428#define mmNIC4_QM1_CP_FENCE2_RDATA_3 0xDE233C 429 430#define mmNIC4_QM1_CP_FENCE2_RDATA_4 0xDE2340 431 432#define mmNIC4_QM1_CP_FENCE3_RDATA_0 0xDE2344 433 434#define mmNIC4_QM1_CP_FENCE3_RDATA_1 0xDE2348 435 436#define mmNIC4_QM1_CP_FENCE3_RDATA_2 0xDE234C 437 438#define mmNIC4_QM1_CP_FENCE3_RDATA_3 0xDE2350 439 440#define mmNIC4_QM1_CP_FENCE3_RDATA_4 0xDE2354 441 442#define mmNIC4_QM1_CP_FENCE0_CNT_0 0xDE2358 443 444#define mmNIC4_QM1_CP_FENCE0_CNT_1 0xDE235C 445 446#define mmNIC4_QM1_CP_FENCE0_CNT_2 0xDE2360 447 448#define mmNIC4_QM1_CP_FENCE0_CNT_3 0xDE2364 449 450#define mmNIC4_QM1_CP_FENCE0_CNT_4 0xDE2368 451 452#define mmNIC4_QM1_CP_FENCE1_CNT_0 0xDE236C 453 454#define mmNIC4_QM1_CP_FENCE1_CNT_1 0xDE2370 455 456#define mmNIC4_QM1_CP_FENCE1_CNT_2 0xDE2374 457 458#define mmNIC4_QM1_CP_FENCE1_CNT_3 0xDE2378 459 460#define mmNIC4_QM1_CP_FENCE1_CNT_4 0xDE237C 461 462#define mmNIC4_QM1_CP_FENCE2_CNT_0 0xDE2380 463 464#define mmNIC4_QM1_CP_FENCE2_CNT_1 0xDE2384 465 466#define mmNIC4_QM1_CP_FENCE2_CNT_2 0xDE2388 467 468#define mmNIC4_QM1_CP_FENCE2_CNT_3 0xDE238C 469 470#define mmNIC4_QM1_CP_FENCE2_CNT_4 0xDE2390 471 472#define mmNIC4_QM1_CP_FENCE3_CNT_0 0xDE2394 473 474#define mmNIC4_QM1_CP_FENCE3_CNT_1 0xDE2398 475 476#define mmNIC4_QM1_CP_FENCE3_CNT_2 0xDE239C 477 478#define mmNIC4_QM1_CP_FENCE3_CNT_3 0xDE23A0 479 480#define mmNIC4_QM1_CP_FENCE3_CNT_4 0xDE23A4 481 482#define mmNIC4_QM1_CP_STS_0 0xDE23A8 483 484#define mmNIC4_QM1_CP_STS_1 0xDE23AC 485 486#define mmNIC4_QM1_CP_STS_2 0xDE23B0 487 488#define mmNIC4_QM1_CP_STS_3 0xDE23B4 489 490#define mmNIC4_QM1_CP_STS_4 0xDE23B8 491 492#define mmNIC4_QM1_CP_CURRENT_INST_LO_0 0xDE23BC 493 494#define mmNIC4_QM1_CP_CURRENT_INST_LO_1 0xDE23C0 495 496#define mmNIC4_QM1_CP_CURRENT_INST_LO_2 0xDE23C4 497 498#define mmNIC4_QM1_CP_CURRENT_INST_LO_3 0xDE23C8 499 500#define mmNIC4_QM1_CP_CURRENT_INST_LO_4 0xDE23CC 501 502#define mmNIC4_QM1_CP_CURRENT_INST_HI_0 0xDE23D0 503 504#define mmNIC4_QM1_CP_CURRENT_INST_HI_1 0xDE23D4 505 506#define mmNIC4_QM1_CP_CURRENT_INST_HI_2 0xDE23D8 507 508#define mmNIC4_QM1_CP_CURRENT_INST_HI_3 0xDE23DC 509 510#define mmNIC4_QM1_CP_CURRENT_INST_HI_4 0xDE23E0 511 512#define mmNIC4_QM1_CP_BARRIER_CFG_0 0xDE23F4 513 514#define mmNIC4_QM1_CP_BARRIER_CFG_1 0xDE23F8 515 516#define mmNIC4_QM1_CP_BARRIER_CFG_2 0xDE23FC 517 518#define mmNIC4_QM1_CP_BARRIER_CFG_3 0xDE2400 519 520#define mmNIC4_QM1_CP_BARRIER_CFG_4 0xDE2404 521 522#define mmNIC4_QM1_CP_DBG_0_0 0xDE2408 523 524#define mmNIC4_QM1_CP_DBG_0_1 0xDE240C 525 526#define mmNIC4_QM1_CP_DBG_0_2 0xDE2410 527 528#define mmNIC4_QM1_CP_DBG_0_3 0xDE2414 529 530#define mmNIC4_QM1_CP_DBG_0_4 0xDE2418 531 532#define mmNIC4_QM1_CP_ARUSER_31_11_0 0xDE241C 533 534#define mmNIC4_QM1_CP_ARUSER_31_11_1 0xDE2420 535 536#define mmNIC4_QM1_CP_ARUSER_31_11_2 0xDE2424 537 538#define mmNIC4_QM1_CP_ARUSER_31_11_3 0xDE2428 539 540#define mmNIC4_QM1_CP_ARUSER_31_11_4 0xDE242C 541 542#define mmNIC4_QM1_CP_AWUSER_31_11_0 0xDE2430 543 544#define mmNIC4_QM1_CP_AWUSER_31_11_1 0xDE2434 545 546#define mmNIC4_QM1_CP_AWUSER_31_11_2 0xDE2438 547 548#define mmNIC4_QM1_CP_AWUSER_31_11_3 0xDE243C 549 550#define mmNIC4_QM1_CP_AWUSER_31_11_4 0xDE2440 551 552#define mmNIC4_QM1_ARB_CFG_0 0xDE2A00 553 554#define mmNIC4_QM1_ARB_CHOISE_Q_PUSH 0xDE2A04 555 556#define mmNIC4_QM1_ARB_WRR_WEIGHT_0 0xDE2A08 557 558#define mmNIC4_QM1_ARB_WRR_WEIGHT_1 0xDE2A0C 559 560#define mmNIC4_QM1_ARB_WRR_WEIGHT_2 0xDE2A10 561 562#define mmNIC4_QM1_ARB_WRR_WEIGHT_3 0xDE2A14 563 564#define mmNIC4_QM1_ARB_CFG_1 0xDE2A18 565 566#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_0 0xDE2A20 567 568#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_1 0xDE2A24 569 570#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_2 0xDE2A28 571 572#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_3 0xDE2A2C 573 574#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_4 0xDE2A30 575 576#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_5 0xDE2A34 577 578#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_6 0xDE2A38 579 580#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_7 0xDE2A3C 581 582#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_8 0xDE2A40 583 584#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_9 0xDE2A44 585 586#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_10 0xDE2A48 587 588#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_11 0xDE2A4C 589 590#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_12 0xDE2A50 591 592#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_13 0xDE2A54 593 594#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_14 0xDE2A58 595 596#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_15 0xDE2A5C 597 598#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_16 0xDE2A60 599 600#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_17 0xDE2A64 601 602#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_18 0xDE2A68 603 604#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_19 0xDE2A6C 605 606#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_20 0xDE2A70 607 608#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_21 0xDE2A74 609 610#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_22 0xDE2A78 611 612#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_23 0xDE2A7C 613 614#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_24 0xDE2A80 615 616#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_25 0xDE2A84 617 618#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_26 0xDE2A88 619 620#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_27 0xDE2A8C 621 622#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_28 0xDE2A90 623 624#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_29 0xDE2A94 625 626#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_30 0xDE2A98 627 628#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_31 0xDE2A9C 629 630#define mmNIC4_QM1_ARB_MST_CRED_INC 0xDE2AA0 631 632#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_0 0xDE2AA4 633 634#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_1 0xDE2AA8 635 636#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_2 0xDE2AAC 637 638#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_3 0xDE2AB0 639 640#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_4 0xDE2AB4 641 642#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_5 0xDE2AB8 643 644#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_6 0xDE2ABC 645 646#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_7 0xDE2AC0 647 648#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_8 0xDE2AC4 649 650#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_9 0xDE2AC8 651 652#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_10 0xDE2ACC 653 654#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_11 0xDE2AD0 655 656#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_12 0xDE2AD4 657 658#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_13 0xDE2AD8 659 660#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_14 0xDE2ADC 661 662#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_15 0xDE2AE0 663 664#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_16 0xDE2AE4 665 666#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_17 0xDE2AE8 667 668#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_18 0xDE2AEC 669 670#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_19 0xDE2AF0 671 672#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_20 0xDE2AF4 673 674#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_21 0xDE2AF8 675 676#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_22 0xDE2AFC 677 678#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_23 0xDE2B00 679 680#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_24 0xDE2B04 681 682#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_25 0xDE2B08 683 684#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_26 0xDE2B0C 685 686#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_27 0xDE2B10 687 688#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_28 0xDE2B14 689 690#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_29 0xDE2B18 691 692#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_30 0xDE2B1C 693 694#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_31 0xDE2B20 695 696#define mmNIC4_QM1_ARB_SLV_MASTER_INC_CRED_OFST 0xDE2B28 697 698#define mmNIC4_QM1_ARB_MST_SLAVE_EN 0xDE2B2C 699 700#define mmNIC4_QM1_ARB_MST_QUIET_PER 0xDE2B34 701 702#define mmNIC4_QM1_ARB_SLV_CHOISE_WDT 0xDE2B38 703 704#define mmNIC4_QM1_ARB_SLV_ID 0xDE2B3C 705 706#define mmNIC4_QM1_ARB_MSG_MAX_INFLIGHT 0xDE2B44 707 708#define mmNIC4_QM1_ARB_MSG_AWUSER_31_11 0xDE2B48 709 710#define mmNIC4_QM1_ARB_MSG_AWUSER_SEC_PROP 0xDE2B4C 711 712#define mmNIC4_QM1_ARB_MSG_AWUSER_NON_SEC_PROP 0xDE2B50 713 714#define mmNIC4_QM1_ARB_BASE_LO 0xDE2B54 715 716#define mmNIC4_QM1_ARB_BASE_HI 0xDE2B58 717 718#define mmNIC4_QM1_ARB_STATE_STS 0xDE2B80 719 720#define mmNIC4_QM1_ARB_CHOISE_FULLNESS_STS 0xDE2B84 721 722#define mmNIC4_QM1_ARB_MSG_STS 0xDE2B88 723 724#define mmNIC4_QM1_ARB_SLV_CHOISE_Q_HEAD 0xDE2B8C 725 726#define mmNIC4_QM1_ARB_ERR_CAUSE 0xDE2B9C 727 728#define mmNIC4_QM1_ARB_ERR_MSG_EN 0xDE2BA0 729 730#define mmNIC4_QM1_ARB_ERR_STS_DRP 0xDE2BA8 731 732#define mmNIC4_QM1_ARB_MST_CRED_STS_0 0xDE2BB0 733 734#define mmNIC4_QM1_ARB_MST_CRED_STS_1 0xDE2BB4 735 736#define mmNIC4_QM1_ARB_MST_CRED_STS_2 0xDE2BB8 737 738#define mmNIC4_QM1_ARB_MST_CRED_STS_3 0xDE2BBC 739 740#define mmNIC4_QM1_ARB_MST_CRED_STS_4 0xDE2BC0 741 742#define mmNIC4_QM1_ARB_MST_CRED_STS_5 0xDE2BC4 743 744#define mmNIC4_QM1_ARB_MST_CRED_STS_6 0xDE2BC8 745 746#define mmNIC4_QM1_ARB_MST_CRED_STS_7 0xDE2BCC 747 748#define mmNIC4_QM1_ARB_MST_CRED_STS_8 0xDE2BD0 749 750#define mmNIC4_QM1_ARB_MST_CRED_STS_9 0xDE2BD4 751 752#define mmNIC4_QM1_ARB_MST_CRED_STS_10 0xDE2BD8 753 754#define mmNIC4_QM1_ARB_MST_CRED_STS_11 0xDE2BDC 755 756#define mmNIC4_QM1_ARB_MST_CRED_STS_12 0xDE2BE0 757 758#define mmNIC4_QM1_ARB_MST_CRED_STS_13 0xDE2BE4 759 760#define mmNIC4_QM1_ARB_MST_CRED_STS_14 0xDE2BE8 761 762#define mmNIC4_QM1_ARB_MST_CRED_STS_15 0xDE2BEC 763 764#define mmNIC4_QM1_ARB_MST_CRED_STS_16 0xDE2BF0 765 766#define mmNIC4_QM1_ARB_MST_CRED_STS_17 0xDE2BF4 767 768#define mmNIC4_QM1_ARB_MST_CRED_STS_18 0xDE2BF8 769 770#define mmNIC4_QM1_ARB_MST_CRED_STS_19 0xDE2BFC 771 772#define mmNIC4_QM1_ARB_MST_CRED_STS_20 0xDE2C00 773 774#define mmNIC4_QM1_ARB_MST_CRED_STS_21 0xDE2C04 775 776#define mmNIC4_QM1_ARB_MST_CRED_STS_22 0xDE2C08 777 778#define mmNIC4_QM1_ARB_MST_CRED_STS_23 0xDE2C0C 779 780#define mmNIC4_QM1_ARB_MST_CRED_STS_24 0xDE2C10 781 782#define mmNIC4_QM1_ARB_MST_CRED_STS_25 0xDE2C14 783 784#define mmNIC4_QM1_ARB_MST_CRED_STS_26 0xDE2C18 785 786#define mmNIC4_QM1_ARB_MST_CRED_STS_27 0xDE2C1C 787 788#define mmNIC4_QM1_ARB_MST_CRED_STS_28 0xDE2C20 789 790#define mmNIC4_QM1_ARB_MST_CRED_STS_29 0xDE2C24 791 792#define mmNIC4_QM1_ARB_MST_CRED_STS_30 0xDE2C28 793 794#define mmNIC4_QM1_ARB_MST_CRED_STS_31 0xDE2C2C 795 796#define mmNIC4_QM1_CGM_CFG 0xDE2C70 797 798#define mmNIC4_QM1_CGM_STS 0xDE2C74 799 800#define mmNIC4_QM1_CGM_CFG1 0xDE2C78 801 802#define mmNIC4_QM1_LOCAL_RANGE_BASE 0xDE2C80 803 804#define mmNIC4_QM1_LOCAL_RANGE_SIZE 0xDE2C84 805 806#define mmNIC4_QM1_CSMR_STRICT_PRIO_CFG 0xDE2C90 807 808#define mmNIC4_QM1_HBW_RD_RATE_LIM_CFG_1 0xDE2C94 809 810#define mmNIC4_QM1_LBW_WR_RATE_LIM_CFG_0 0xDE2C98 811 812#define mmNIC4_QM1_LBW_WR_RATE_LIM_CFG_1 0xDE2C9C 813 814#define mmNIC4_QM1_HBW_RD_RATE_LIM_CFG_0 0xDE2CA0 815 816#define mmNIC4_QM1_GLBL_AXCACHE 0xDE2CA4 817 818#define mmNIC4_QM1_IND_GW_APB_CFG 0xDE2CB0 819 820#define mmNIC4_QM1_IND_GW_APB_WDATA 0xDE2CB4 821 822#define mmNIC4_QM1_IND_GW_APB_RDATA 0xDE2CB8 823 824#define mmNIC4_QM1_IND_GW_APB_STATUS 0xDE2CBC 825 826#define mmNIC4_QM1_GLBL_ERR_ADDR_LO 0xDE2CD0 827 828#define mmNIC4_QM1_GLBL_ERR_ADDR_HI 0xDE2CD4 829 830#define mmNIC4_QM1_GLBL_ERR_WDATA 0xDE2CD8 831 832#define mmNIC4_QM1_GLBL_MEM_INIT_BUSY 0xDE2D00 833 834#endif /* ASIC_REG_NIC4_QM1_REGS_H_ */