cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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stlb_regs.h (2853B)


      1/* SPDX-License-Identifier: GPL-2.0
      2 *
      3 * Copyright 2016-2018 HabanaLabs, Ltd.
      4 * All Rights Reserved.
      5 *
      6 */
      7
      8/************************************
      9 ** This is an auto-generated file **
     10 **       DO NOT EDIT BELOW        **
     11 ************************************/
     12
     13#ifndef ASIC_REG_STLB_REGS_H_
     14#define ASIC_REG_STLB_REGS_H_
     15
     16/*
     17 *****************************************
     18 *   STLB (Prototype: STLB)
     19 *****************************************
     20 */
     21
     22#define mmSTLB_CACHE_INV                                             0xC12010
     23
     24#define mmSTLB_CACHE_INV_BASE_39_8                                   0xC12014
     25
     26#define mmSTLB_CACHE_INV_BASE_49_40                                  0xC12018
     27
     28#define mmSTLB_STLB_FEATURE_EN                                       0xC1201C
     29
     30#define mmSTLB_STLB_AXI_CACHE                                        0xC12020
     31
     32#define mmSTLB_HOP_CONFIGURATION                                     0xC12024
     33
     34#define mmSTLB_LINK_LIST_LOOKUP_MASK_49_32                           0xC12028
     35
     36#define mmSTLB_LINK_LIST_LOOKUP_MASK_31_0                            0xC1202C
     37
     38#define mmSTLB_LINK_LIST                                             0xC12030
     39
     40#define mmSTLB_INV_ALL_START                                         0xC12034
     41
     42#define mmSTLB_INV_ALL_SET                                           0xC12038
     43
     44#define mmSTLB_INV_PS                                                0xC1203C
     45
     46#define mmSTLB_INV_CONSUMER_INDEX                                    0xC12040
     47
     48#define mmSTLB_INV_HIT_COUNT                                         0xC12044
     49
     50#define mmSTLB_INV_SET                                               0xC12048
     51
     52#define mmSTLB_SRAM_INIT                                             0xC1204C
     53
     54#define mmSTLB_MEM_CACHE_INVALIDATION                                0xC12050
     55
     56#define mmSTLB_MEM_CACHE_INV_STATUS                                  0xC12054
     57
     58#define mmSTLB_MEM_CACHE_BASE_38_7                                   0xC12058
     59
     60#define mmSTLB_MEM_CACHE_BASE_49_39                                  0xC1205C
     61
     62#define mmSTLB_MEM_CACHE_CONFIG                                      0xC12060
     63
     64#define mmSTLB_SET_THRESHOLD_HOP4                                    0xC12064
     65
     66#define mmSTLB_SET_THRESHOLD_HOP3                                    0xC12068
     67
     68#define mmSTLB_SET_THRESHOLD_HOP2                                    0xC1206C
     69
     70#define mmSTLB_SET_THRESHOLD_HOP1                                    0xC12070
     71
     72#define mmSTLB_SET_THRESHOLD_HOP0                                    0xC12074
     73
     74#define mmSTLB_MULTI_HIT_INTERRUPT_CLR                               0xC12078
     75
     76#define mmSTLB_MULTI_HIT_INTERRUPT_MASK                              0xC1207C
     77
     78#define mmSTLB_MEM_L0_CACHE_CFG                                      0xC12080
     79
     80#define mmSTLB_MEM_READ_ARPROT                                       0xC12084
     81
     82#endif /* ASIC_REG_STLB_REGS_H_ */