dma_ch_2_regs.h (7848B)
1/* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2018 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8/************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13#ifndef ASIC_REG_DMA_CH_2_REGS_H_ 14#define ASIC_REG_DMA_CH_2_REGS_H_ 15 16/* 17 ***************************************** 18 * DMA_CH_2 (Prototype: DMA_CH) 19 ***************************************** 20 */ 21 22#define mmDMA_CH_2_CFG0 0x411000 23 24#define mmDMA_CH_2_CFG1 0x411004 25 26#define mmDMA_CH_2_ERRMSG_ADDR_LO 0x411008 27 28#define mmDMA_CH_2_ERRMSG_ADDR_HI 0x41100C 29 30#define mmDMA_CH_2_ERRMSG_WDATA 0x411010 31 32#define mmDMA_CH_2_RD_COMP_ADDR_LO 0x411014 33 34#define mmDMA_CH_2_RD_COMP_ADDR_HI 0x411018 35 36#define mmDMA_CH_2_RD_COMP_WDATA 0x41101C 37 38#define mmDMA_CH_2_WR_COMP_ADDR_LO 0x411020 39 40#define mmDMA_CH_2_WR_COMP_ADDR_HI 0x411024 41 42#define mmDMA_CH_2_WR_COMP_WDATA 0x411028 43 44#define mmDMA_CH_2_LDMA_SRC_ADDR_LO 0x41102C 45 46#define mmDMA_CH_2_LDMA_SRC_ADDR_HI 0x411030 47 48#define mmDMA_CH_2_LDMA_DST_ADDR_LO 0x411034 49 50#define mmDMA_CH_2_LDMA_DST_ADDR_HI 0x411038 51 52#define mmDMA_CH_2_LDMA_TSIZE 0x41103C 53 54#define mmDMA_CH_2_COMIT_TRANSFER 0x411040 55 56#define mmDMA_CH_2_STS0 0x411044 57 58#define mmDMA_CH_2_STS1 0x411048 59 60#define mmDMA_CH_2_STS2 0x41104C 61 62#define mmDMA_CH_2_STS3 0x411050 63 64#define mmDMA_CH_2_STS4 0x411054 65 66#define mmDMA_CH_2_SRC_ADDR_LO_STS 0x411058 67 68#define mmDMA_CH_2_SRC_ADDR_HI_STS 0x41105C 69 70#define mmDMA_CH_2_SRC_TSIZE_STS 0x411060 71 72#define mmDMA_CH_2_DST_ADDR_LO_STS 0x411064 73 74#define mmDMA_CH_2_DST_ADDR_HI_STS 0x411068 75 76#define mmDMA_CH_2_DST_TSIZE_STS 0x41106C 77 78#define mmDMA_CH_2_RD_RATE_LIM_EN 0x411070 79 80#define mmDMA_CH_2_RD_RATE_LIM_RST_TOKEN 0x411074 81 82#define mmDMA_CH_2_RD_RATE_LIM_SAT 0x411078 83 84#define mmDMA_CH_2_RD_RATE_LIM_TOUT 0x41107C 85 86#define mmDMA_CH_2_WR_RATE_LIM_EN 0x411080 87 88#define mmDMA_CH_2_WR_RATE_LIM_RST_TOKEN 0x411084 89 90#define mmDMA_CH_2_WR_RATE_LIM_SAT 0x411088 91 92#define mmDMA_CH_2_WR_RATE_LIM_TOUT 0x41108C 93 94#define mmDMA_CH_2_CFG2 0x411090 95 96#define mmDMA_CH_2_TDMA_CTL 0x411100 97 98#define mmDMA_CH_2_TDMA_SRC_BASE_ADDR_LO 0x411104 99 100#define mmDMA_CH_2_TDMA_SRC_BASE_ADDR_HI 0x411108 101 102#define mmDMA_CH_2_TDMA_SRC_ROI_BASE_0 0x41110C 103 104#define mmDMA_CH_2_TDMA_SRC_ROI_SIZE_0 0x411110 105 106#define mmDMA_CH_2_TDMA_SRC_VALID_ELEMENTS_0 0x411114 107 108#define mmDMA_CH_2_TDMA_SRC_START_OFFSET_0 0x411118 109 110#define mmDMA_CH_2_TDMA_SRC_STRIDE_0 0x41111C 111 112#define mmDMA_CH_2_TDMA_SRC_ROI_BASE_1 0x411120 113 114#define mmDMA_CH_2_TDMA_SRC_ROI_SIZE_1 0x411124 115 116#define mmDMA_CH_2_TDMA_SRC_VALID_ELEMENTS_1 0x411128 117 118#define mmDMA_CH_2_TDMA_SRC_START_OFFSET_1 0x41112C 119 120#define mmDMA_CH_2_TDMA_SRC_STRIDE_1 0x411130 121 122#define mmDMA_CH_2_TDMA_SRC_ROI_BASE_2 0x411134 123 124#define mmDMA_CH_2_TDMA_SRC_ROI_SIZE_2 0x411138 125 126#define mmDMA_CH_2_TDMA_SRC_VALID_ELEMENTS_2 0x41113C 127 128#define mmDMA_CH_2_TDMA_SRC_START_OFFSET_2 0x411140 129 130#define mmDMA_CH_2_TDMA_SRC_STRIDE_2 0x411144 131 132#define mmDMA_CH_2_TDMA_SRC_ROI_BASE_3 0x411148 133 134#define mmDMA_CH_2_TDMA_SRC_ROI_SIZE_3 0x41114C 135 136#define mmDMA_CH_2_TDMA_SRC_VALID_ELEMENTS_3 0x411150 137 138#define mmDMA_CH_2_TDMA_SRC_START_OFFSET_3 0x411154 139 140#define mmDMA_CH_2_TDMA_SRC_STRIDE_3 0x411158 141 142#define mmDMA_CH_2_TDMA_SRC_ROI_BASE_4 0x41115C 143 144#define mmDMA_CH_2_TDMA_SRC_ROI_SIZE_4 0x411160 145 146#define mmDMA_CH_2_TDMA_SRC_VALID_ELEMENTS_4 0x411164 147 148#define mmDMA_CH_2_TDMA_SRC_START_OFFSET_4 0x411168 149 150#define mmDMA_CH_2_TDMA_SRC_STRIDE_4 0x41116C 151 152#define mmDMA_CH_2_TDMA_DST_BASE_ADDR_LO 0x411170 153 154#define mmDMA_CH_2_TDMA_DST_BASE_ADDR_HI 0x411174 155 156#define mmDMA_CH_2_TDMA_DST_ROI_BASE_0 0x411178 157 158#define mmDMA_CH_2_TDMA_DST_ROI_SIZE_0 0x41117C 159 160#define mmDMA_CH_2_TDMA_DST_VALID_ELEMENTS_0 0x411180 161 162#define mmDMA_CH_2_TDMA_DST_START_OFFSET_0 0x411184 163 164#define mmDMA_CH_2_TDMA_DST_STRIDE_0 0x411188 165 166#define mmDMA_CH_2_TDMA_DST_ROI_BASE_1 0x41118C 167 168#define mmDMA_CH_2_TDMA_DST_ROI_SIZE_1 0x411190 169 170#define mmDMA_CH_2_TDMA_DST_VALID_ELEMENTS_1 0x411194 171 172#define mmDMA_CH_2_TDMA_DST_START_OFFSET_1 0x411198 173 174#define mmDMA_CH_2_TDMA_DST_STRIDE_1 0x41119C 175 176#define mmDMA_CH_2_TDMA_DST_ROI_BASE_2 0x4111A0 177 178#define mmDMA_CH_2_TDMA_DST_ROI_SIZE_2 0x4111A4 179 180#define mmDMA_CH_2_TDMA_DST_VALID_ELEMENTS_2 0x4111A8 181 182#define mmDMA_CH_2_TDMA_DST_START_OFFSET_2 0x4111AC 183 184#define mmDMA_CH_2_TDMA_DST_STRIDE_2 0x4111B0 185 186#define mmDMA_CH_2_TDMA_DST_ROI_BASE_3 0x4111B4 187 188#define mmDMA_CH_2_TDMA_DST_ROI_SIZE_3 0x4111B8 189 190#define mmDMA_CH_2_TDMA_DST_VALID_ELEMENTS_3 0x4111BC 191 192#define mmDMA_CH_2_TDMA_DST_START_OFFSET_3 0x4111C0 193 194#define mmDMA_CH_2_TDMA_DST_STRIDE_3 0x4111C4 195 196#define mmDMA_CH_2_TDMA_DST_ROI_BASE_4 0x4111C8 197 198#define mmDMA_CH_2_TDMA_DST_ROI_SIZE_4 0x4111CC 199 200#define mmDMA_CH_2_TDMA_DST_VALID_ELEMENTS_4 0x4111D0 201 202#define mmDMA_CH_2_TDMA_DST_START_OFFSET_4 0x4111D4 203 204#define mmDMA_CH_2_TDMA_DST_STRIDE_4 0x4111D8 205 206#define mmDMA_CH_2_MEM_INIT_BUSY 0x4111FC 207 208#endif /* ASIC_REG_DMA_CH_2_REGS_H_ */