mme4_rtr_regs.h (12668B)
1/* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2018 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8/************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13#ifndef ASIC_REG_MME4_RTR_REGS_H_ 14#define ASIC_REG_MME4_RTR_REGS_H_ 15 16/* 17 ***************************************** 18 * MME4_RTR (Prototype: MME_RTR) 19 ***************************************** 20 */ 21 22#define mmMME4_RTR_HBW_RD_RQ_E_ARB 0x100100 23 24#define mmMME4_RTR_HBW_RD_RQ_W_ARB 0x100104 25 26#define mmMME4_RTR_HBW_RD_RQ_N_ARB 0x100108 27 28#define mmMME4_RTR_HBW_RD_RQ_S_ARB 0x10010C 29 30#define mmMME4_RTR_HBW_RD_RQ_L_ARB 0x100110 31 32#define mmMME4_RTR_HBW_E_ARB_MAX 0x100120 33 34#define mmMME4_RTR_HBW_W_ARB_MAX 0x100124 35 36#define mmMME4_RTR_HBW_N_ARB_MAX 0x100128 37 38#define mmMME4_RTR_HBW_S_ARB_MAX 0x10012C 39 40#define mmMME4_RTR_HBW_L_ARB_MAX 0x100130 41 42#define mmMME4_RTR_HBW_RD_RS_MAX_CREDIT 0x100140 43 44#define mmMME4_RTR_HBW_WR_RQ_MAX_CREDIT 0x100144 45 46#define mmMME4_RTR_HBW_RD_RQ_MAX_CREDIT 0x100148 47 48#define mmMME4_RTR_HBW_RD_RS_E_ARB 0x100150 49 50#define mmMME4_RTR_HBW_RD_RS_W_ARB 0x100154 51 52#define mmMME4_RTR_HBW_RD_RS_N_ARB 0x100158 53 54#define mmMME4_RTR_HBW_RD_RS_S_ARB 0x10015C 55 56#define mmMME4_RTR_HBW_RD_RS_L_ARB 0x100160 57 58#define mmMME4_RTR_HBW_WR_RQ_E_ARB 0x100170 59 60#define mmMME4_RTR_HBW_WR_RQ_W_ARB 0x100174 61 62#define mmMME4_RTR_HBW_WR_RQ_N_ARB 0x100178 63 64#define mmMME4_RTR_HBW_WR_RQ_S_ARB 0x10017C 65 66#define mmMME4_RTR_HBW_WR_RQ_L_ARB 0x100180 67 68#define mmMME4_RTR_HBW_WR_RS_E_ARB 0x100190 69 70#define mmMME4_RTR_HBW_WR_RS_W_ARB 0x100194 71 72#define mmMME4_RTR_HBW_WR_RS_N_ARB 0x100198 73 74#define mmMME4_RTR_HBW_WR_RS_S_ARB 0x10019C 75 76#define mmMME4_RTR_HBW_WR_RS_L_ARB 0x1001A0 77 78#define mmMME4_RTR_LBW_RD_RQ_E_ARB 0x100200 79 80#define mmMME4_RTR_LBW_RD_RQ_W_ARB 0x100204 81 82#define mmMME4_RTR_LBW_RD_RQ_N_ARB 0x100208 83 84#define mmMME4_RTR_LBW_RD_RQ_S_ARB 0x10020C 85 86#define mmMME4_RTR_LBW_RD_RQ_L_ARB 0x100210 87 88#define mmMME4_RTR_LBW_E_ARB_MAX 0x100220 89 90#define mmMME4_RTR_LBW_W_ARB_MAX 0x100224 91 92#define mmMME4_RTR_LBW_N_ARB_MAX 0x100228 93 94#define mmMME4_RTR_LBW_S_ARB_MAX 0x10022C 95 96#define mmMME4_RTR_LBW_L_ARB_MAX 0x100230 97 98#define mmMME4_RTR_LBW_SRAM_MAX_CREDIT 0x100240 99 100#define mmMME4_RTR_LBW_RD_RS_E_ARB 0x100250 101 102#define mmMME4_RTR_LBW_RD_RS_W_ARB 0x100254 103 104#define mmMME4_RTR_LBW_RD_RS_N_ARB 0x100258 105 106#define mmMME4_RTR_LBW_RD_RS_S_ARB 0x10025C 107 108#define mmMME4_RTR_LBW_RD_RS_L_ARB 0x100260 109 110#define mmMME4_RTR_LBW_WR_RQ_E_ARB 0x100270 111 112#define mmMME4_RTR_LBW_WR_RQ_W_ARB 0x100274 113 114#define mmMME4_RTR_LBW_WR_RQ_N_ARB 0x100278 115 116#define mmMME4_RTR_LBW_WR_RQ_S_ARB 0x10027C 117 118#define mmMME4_RTR_LBW_WR_RQ_L_ARB 0x100280 119 120#define mmMME4_RTR_LBW_WR_RS_E_ARB 0x100290 121 122#define mmMME4_RTR_LBW_WR_RS_W_ARB 0x100294 123 124#define mmMME4_RTR_LBW_WR_RS_N_ARB 0x100298 125 126#define mmMME4_RTR_LBW_WR_RS_S_ARB 0x10029C 127 128#define mmMME4_RTR_LBW_WR_RS_L_ARB 0x1002A0 129 130#define mmMME4_RTR_DBG_E_ARB 0x100300 131 132#define mmMME4_RTR_DBG_W_ARB 0x100304 133 134#define mmMME4_RTR_DBG_N_ARB 0x100308 135 136#define mmMME4_RTR_DBG_S_ARB 0x10030C 137 138#define mmMME4_RTR_DBG_L_ARB 0x100310 139 140#define mmMME4_RTR_DBG_E_ARB_MAX 0x100320 141 142#define mmMME4_RTR_DBG_W_ARB_MAX 0x100324 143 144#define mmMME4_RTR_DBG_N_ARB_MAX 0x100328 145 146#define mmMME4_RTR_DBG_S_ARB_MAX 0x10032C 147 148#define mmMME4_RTR_DBG_L_ARB_MAX 0x100330 149 150#define mmMME4_RTR_SPLIT_COEF_0 0x100400 151 152#define mmMME4_RTR_SPLIT_COEF_1 0x100404 153 154#define mmMME4_RTR_SPLIT_COEF_2 0x100408 155 156#define mmMME4_RTR_SPLIT_COEF_3 0x10040C 157 158#define mmMME4_RTR_SPLIT_COEF_4 0x100410 159 160#define mmMME4_RTR_SPLIT_COEF_5 0x100414 161 162#define mmMME4_RTR_SPLIT_COEF_6 0x100418 163 164#define mmMME4_RTR_SPLIT_COEF_7 0x10041C 165 166#define mmMME4_RTR_SPLIT_COEF_8 0x100420 167 168#define mmMME4_RTR_SPLIT_COEF_9 0x100424 169 170#define mmMME4_RTR_SPLIT_CFG 0x100440 171 172#define mmMME4_RTR_SPLIT_RD_SAT 0x100444 173 174#define mmMME4_RTR_SPLIT_RD_RST_TOKEN 0x100448 175 176#define mmMME4_RTR_SPLIT_RD_TIMEOUT_0 0x10044C 177 178#define mmMME4_RTR_SPLIT_RD_TIMEOUT_1 0x100450 179 180#define mmMME4_RTR_SPLIT_WR_SAT 0x100454 181 182#define mmMME4_RTR_WPLIT_WR_TST_TOLEN 0x100458 183 184#define mmMME4_RTR_SPLIT_WR_TIMEOUT_0 0x10045C 185 186#define mmMME4_RTR_SPLIT_WR_TIMEOUT_1 0x100460 187 188#define mmMME4_RTR_HBW_RANGE_HIT 0x100470 189 190#define mmMME4_RTR_HBW_RANGE_MASK_L_0 0x100480 191 192#define mmMME4_RTR_HBW_RANGE_MASK_L_1 0x100484 193 194#define mmMME4_RTR_HBW_RANGE_MASK_L_2 0x100488 195 196#define mmMME4_RTR_HBW_RANGE_MASK_L_3 0x10048C 197 198#define mmMME4_RTR_HBW_RANGE_MASK_L_4 0x100490 199 200#define mmMME4_RTR_HBW_RANGE_MASK_L_5 0x100494 201 202#define mmMME4_RTR_HBW_RANGE_MASK_L_6 0x100498 203 204#define mmMME4_RTR_HBW_RANGE_MASK_L_7 0x10049C 205 206#define mmMME4_RTR_HBW_RANGE_MASK_H_0 0x1004A0 207 208#define mmMME4_RTR_HBW_RANGE_MASK_H_1 0x1004A4 209 210#define mmMME4_RTR_HBW_RANGE_MASK_H_2 0x1004A8 211 212#define mmMME4_RTR_HBW_RANGE_MASK_H_3 0x1004AC 213 214#define mmMME4_RTR_HBW_RANGE_MASK_H_4 0x1004B0 215 216#define mmMME4_RTR_HBW_RANGE_MASK_H_5 0x1004B4 217 218#define mmMME4_RTR_HBW_RANGE_MASK_H_6 0x1004B8 219 220#define mmMME4_RTR_HBW_RANGE_MASK_H_7 0x1004BC 221 222#define mmMME4_RTR_HBW_RANGE_BASE_L_0 0x1004C0 223 224#define mmMME4_RTR_HBW_RANGE_BASE_L_1 0x1004C4 225 226#define mmMME4_RTR_HBW_RANGE_BASE_L_2 0x1004C8 227 228#define mmMME4_RTR_HBW_RANGE_BASE_L_3 0x1004CC 229 230#define mmMME4_RTR_HBW_RANGE_BASE_L_4 0x1004D0 231 232#define mmMME4_RTR_HBW_RANGE_BASE_L_5 0x1004D4 233 234#define mmMME4_RTR_HBW_RANGE_BASE_L_6 0x1004D8 235 236#define mmMME4_RTR_HBW_RANGE_BASE_L_7 0x1004DC 237 238#define mmMME4_RTR_HBW_RANGE_BASE_H_0 0x1004E0 239 240#define mmMME4_RTR_HBW_RANGE_BASE_H_1 0x1004E4 241 242#define mmMME4_RTR_HBW_RANGE_BASE_H_2 0x1004E8 243 244#define mmMME4_RTR_HBW_RANGE_BASE_H_3 0x1004EC 245 246#define mmMME4_RTR_HBW_RANGE_BASE_H_4 0x1004F0 247 248#define mmMME4_RTR_HBW_RANGE_BASE_H_5 0x1004F4 249 250#define mmMME4_RTR_HBW_RANGE_BASE_H_6 0x1004F8 251 252#define mmMME4_RTR_HBW_RANGE_BASE_H_7 0x1004FC 253 254#define mmMME4_RTR_LBW_RANGE_HIT 0x100500 255 256#define mmMME4_RTR_LBW_RANGE_MASK_0 0x100510 257 258#define mmMME4_RTR_LBW_RANGE_MASK_1 0x100514 259 260#define mmMME4_RTR_LBW_RANGE_MASK_2 0x100518 261 262#define mmMME4_RTR_LBW_RANGE_MASK_3 0x10051C 263 264#define mmMME4_RTR_LBW_RANGE_MASK_4 0x100520 265 266#define mmMME4_RTR_LBW_RANGE_MASK_5 0x100524 267 268#define mmMME4_RTR_LBW_RANGE_MASK_6 0x100528 269 270#define mmMME4_RTR_LBW_RANGE_MASK_7 0x10052C 271 272#define mmMME4_RTR_LBW_RANGE_MASK_8 0x100530 273 274#define mmMME4_RTR_LBW_RANGE_MASK_9 0x100534 275 276#define mmMME4_RTR_LBW_RANGE_MASK_10 0x100538 277 278#define mmMME4_RTR_LBW_RANGE_MASK_11 0x10053C 279 280#define mmMME4_RTR_LBW_RANGE_MASK_12 0x100540 281 282#define mmMME4_RTR_LBW_RANGE_MASK_13 0x100544 283 284#define mmMME4_RTR_LBW_RANGE_MASK_14 0x100548 285 286#define mmMME4_RTR_LBW_RANGE_MASK_15 0x10054C 287 288#define mmMME4_RTR_LBW_RANGE_BASE_0 0x100550 289 290#define mmMME4_RTR_LBW_RANGE_BASE_1 0x100554 291 292#define mmMME4_RTR_LBW_RANGE_BASE_2 0x100558 293 294#define mmMME4_RTR_LBW_RANGE_BASE_3 0x10055C 295 296#define mmMME4_RTR_LBW_RANGE_BASE_4 0x100560 297 298#define mmMME4_RTR_LBW_RANGE_BASE_5 0x100564 299 300#define mmMME4_RTR_LBW_RANGE_BASE_6 0x100568 301 302#define mmMME4_RTR_LBW_RANGE_BASE_7 0x10056C 303 304#define mmMME4_RTR_LBW_RANGE_BASE_8 0x100570 305 306#define mmMME4_RTR_LBW_RANGE_BASE_9 0x100574 307 308#define mmMME4_RTR_LBW_RANGE_BASE_10 0x100578 309 310#define mmMME4_RTR_LBW_RANGE_BASE_11 0x10057C 311 312#define mmMME4_RTR_LBW_RANGE_BASE_12 0x100580 313 314#define mmMME4_RTR_LBW_RANGE_BASE_13 0x100584 315 316#define mmMME4_RTR_LBW_RANGE_BASE_14 0x100588 317 318#define mmMME4_RTR_LBW_RANGE_BASE_15 0x10058C 319 320#define mmMME4_RTR_RGLTR 0x100590 321 322#define mmMME4_RTR_RGLTR_WR_RESULT 0x100594 323 324#define mmMME4_RTR_RGLTR_RD_RESULT 0x100598 325 326#define mmMME4_RTR_SCRAMB_EN 0x100600 327 328#define mmMME4_RTR_NON_LIN_SCRAMB 0x100604 329 330#endif /* ASIC_REG_MME4_RTR_REGS_H_ */