cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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stlb_regs.h (1747B)

      1/* SPDX-License-Identifier: GPL-2.0
      2 *
      3 * Copyright 2016-2018 HabanaLabs, Ltd.
      4 * All Rights Reserved.
      5 *
      6 */
      7
      8/************************************
      9 ** This is an auto-generated file **
     10 **       DO NOT EDIT BELOW        **
     11 ************************************/
     12
     13#ifndef ASIC_REG_STLB_REGS_H_
     14#define ASIC_REG_STLB_REGS_H_
     15
     16/*
     17 *****************************************
     18 *   STLB (Prototype: STLB)
     19 *****************************************
     20 */
     21
     22#define mmSTLB_CACHE_INV                                             0x490010
     23
     24#define mmSTLB_CACHE_INV_BASE_39_8                                   0x490014
     25
     26#define mmSTLB_CACHE_INV_BASE_49_40                                  0x490018
     27
     28#define mmSTLB_STLB_FEATURE_EN                                       0x49001C
     29
     30#define mmSTLB_STLB_AXI_CACHE                                        0x490020
     31
     32#define mmSTLB_HOP_CONFIGURATION                                     0x490024
     33
     34#define mmSTLB_LINK_LIST_LOOKUP_MASK_49_32                           0x490028
     35
     36#define mmSTLB_LINK_LIST_LOOKUP_MASK_31_0                            0x49002C
     37
     38#define mmSTLB_LINK_LIST                                             0x490030
     39
     40#define mmSTLB_INV_ALL_START                                         0x490034
     41
     42#define mmSTLB_INV_ALL_SET                                           0x490038
     43
     44#define mmSTLB_INV_PS                                                0x49003C
     45
     46#define mmSTLB_INV_CONSUMER_INDEX                                    0x490040
     47
     48#define mmSTLB_INV_HIT_COUNT                                         0x490044
     49
     50#define mmSTLB_INV_SET                                               0x490048
     51
     52#define mmSTLB_SRAM_INIT                                             0x49004C
     53
     54#endif /* ASIC_REG_STLB_REGS_H_ */