cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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tpc0_cmdq_regs.h (5085B)

      1/* SPDX-License-Identifier: GPL-2.0
      2 *
      3 * Copyright 2016-2018 HabanaLabs, Ltd.
      4 * All Rights Reserved.
      5 *
      6 */
      7
      8/************************************
      9 ** This is an auto-generated file **
     10 **       DO NOT EDIT BELOW        **
     11 ************************************/
     12
     13#ifndef ASIC_REG_TPC0_CMDQ_REGS_H_
     14#define ASIC_REG_TPC0_CMDQ_REGS_H_
     15
     16/*
     17 *****************************************
     18 *   TPC0_CMDQ (Prototype: CMDQ)
     19 *****************************************
     20 */
     21
     22#define mmTPC0_CMDQ_GLBL_CFG0                                        0xE09000
     23
     24#define mmTPC0_CMDQ_GLBL_CFG1                                        0xE09004
     25
     26#define mmTPC0_CMDQ_GLBL_PROT                                        0xE09008
     27
     28#define mmTPC0_CMDQ_GLBL_ERR_CFG                                     0xE0900C
     29
     30#define mmTPC0_CMDQ_GLBL_ERR_ADDR_LO                                 0xE09010
     31
     32#define mmTPC0_CMDQ_GLBL_ERR_ADDR_HI                                 0xE09014
     33
     34#define mmTPC0_CMDQ_GLBL_ERR_WDATA                                   0xE09018
     35
     36#define mmTPC0_CMDQ_GLBL_SECURE_PROPS                                0xE0901C
     37
     38#define mmTPC0_CMDQ_GLBL_NON_SECURE_PROPS                            0xE09020
     39
     40#define mmTPC0_CMDQ_GLBL_STS0                                        0xE09024
     41
     42#define mmTPC0_CMDQ_GLBL_STS1                                        0xE09028
     43
     44#define mmTPC0_CMDQ_CQ_CFG0                                          0xE090B0
     45
     46#define mmTPC0_CMDQ_CQ_CFG1                                          0xE090B4
     47
     48#define mmTPC0_CMDQ_CQ_ARUSER                                        0xE090B8
     49
     50#define mmTPC0_CMDQ_CQ_PTR_LO                                        0xE090C0
     51
     52#define mmTPC0_CMDQ_CQ_PTR_HI                                        0xE090C4
     53
     54#define mmTPC0_CMDQ_CQ_TSIZE                                         0xE090C8
     55
     56#define mmTPC0_CMDQ_CQ_CTL                                           0xE090CC
     57
     58#define mmTPC0_CMDQ_CQ_PTR_LO_STS                                    0xE090D4
     59
     60#define mmTPC0_CMDQ_CQ_PTR_HI_STS                                    0xE090D8
     61
     62#define mmTPC0_CMDQ_CQ_TSIZE_STS                                     0xE090DC
     63
     64#define mmTPC0_CMDQ_CQ_CTL_STS                                       0xE090E0
     65
     66#define mmTPC0_CMDQ_CQ_STS0                                          0xE090E4
     67
     68#define mmTPC0_CMDQ_CQ_STS1                                          0xE090E8
     69
     70#define mmTPC0_CMDQ_CQ_RD_RATE_LIM_EN                                0xE090F0
     71
     72#define mmTPC0_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN                         0xE090F4
     73
     74#define mmTPC0_CMDQ_CQ_RD_RATE_LIM_SAT                               0xE090F8
     75
     76#define mmTPC0_CMDQ_CQ_RD_RATE_LIM_TOUT                              0xE090FC
     77
     78#define mmTPC0_CMDQ_CQ_IFIFO_CNT                                     0xE09108
     79
     80#define mmTPC0_CMDQ_CP_MSG_BASE0_ADDR_LO                             0xE09120
     81
     82#define mmTPC0_CMDQ_CP_MSG_BASE0_ADDR_HI                             0xE09124
     83
     84#define mmTPC0_CMDQ_CP_MSG_BASE1_ADDR_LO                             0xE09128
     85
     86#define mmTPC0_CMDQ_CP_MSG_BASE1_ADDR_HI                             0xE0912C
     87
     88#define mmTPC0_CMDQ_CP_MSG_BASE2_ADDR_LO                             0xE09130
     89
     90#define mmTPC0_CMDQ_CP_MSG_BASE2_ADDR_HI                             0xE09134
     91
     92#define mmTPC0_CMDQ_CP_MSG_BASE3_ADDR_LO                             0xE09138
     93
     94#define mmTPC0_CMDQ_CP_MSG_BASE3_ADDR_HI                             0xE0913C
     95
     96#define mmTPC0_CMDQ_CP_LDMA_TSIZE_OFFSET                             0xE09140
     97
     98#define mmTPC0_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET                       0xE09144
     99
    100#define mmTPC0_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET                       0xE09148
    101
    102#define mmTPC0_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET                       0xE0914C
    103
    104#define mmTPC0_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET                       0xE09150
    105
    106#define mmTPC0_CMDQ_CP_LDMA_COMMIT_OFFSET                            0xE09154
    107
    108#define mmTPC0_CMDQ_CP_FENCE0_RDATA                                  0xE09158
    109
    110#define mmTPC0_CMDQ_CP_FENCE1_RDATA                                  0xE0915C
    111
    112#define mmTPC0_CMDQ_CP_FENCE2_RDATA                                  0xE09160
    113
    114#define mmTPC0_CMDQ_CP_FENCE3_RDATA                                  0xE09164
    115
    116#define mmTPC0_CMDQ_CP_FENCE0_CNT                                    0xE09168
    117
    118#define mmTPC0_CMDQ_CP_FENCE1_CNT                                    0xE0916C
    119
    120#define mmTPC0_CMDQ_CP_FENCE2_CNT                                    0xE09170
    121
    122#define mmTPC0_CMDQ_CP_FENCE3_CNT                                    0xE09174
    123
    124#define mmTPC0_CMDQ_CP_STS                                           0xE09178
    125
    126#define mmTPC0_CMDQ_CP_CURRENT_INST_LO                               0xE0917C
    127
    128#define mmTPC0_CMDQ_CP_CURRENT_INST_HI                               0xE09180
    129
    130#define mmTPC0_CMDQ_CP_BARRIER_CFG                                   0xE09184
    131
    132#define mmTPC0_CMDQ_CP_DBG_0                                         0xE09188
    133
    134#define mmTPC0_CMDQ_CQ_BUF_ADDR                                      0xE09308
    135
    136#define mmTPC0_CMDQ_CQ_BUF_RDATA                                     0xE0930C
    137
    138#endif /* ASIC_REG_TPC0_CMDQ_REGS_H_ */