cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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hw-txe.h (1874B)

      1/* SPDX-License-Identifier: GPL-2.0 */
      2/*
      3 * Copyright (c) 2013-2016, Intel Corporation. All rights reserved.
      4 * Intel Management Engine Interface (Intel MEI) Linux driver
      5 */
      6
      7#ifndef _MEI_HW_TXE_H_
      8#define _MEI_HW_TXE_H_
      9
     10#include <linux/irqreturn.h>
     11
     12#include "hw.h"
     13#include "hw-txe-regs.h"
     14
     15#define MEI_TXI_RPM_TIMEOUT    500 /* ms */
     16
     17/* Flatten Hierarchy interrupt cause */
     18#define TXE_INTR_READINESS_BIT  0 /* HISR_INT_0_STS */
     19#define TXE_INTR_READINESS      HISR_INT_0_STS
     20#define TXE_INTR_ALIVENESS_BIT  1 /* HISR_INT_1_STS */
     21#define TXE_INTR_ALIVENESS      HISR_INT_1_STS
     22#define TXE_INTR_OUT_DB_BIT     2 /* HISR_INT_2_STS */
     23#define TXE_INTR_OUT_DB         HISR_INT_2_STS
     24#define TXE_INTR_IN_READY_BIT   8 /* beyond HISR */
     25#define TXE_INTR_IN_READY       BIT(8)
     26
     27/**
     28 * struct mei_txe_hw - txe hardware specifics
     29 *
     30 * @mem_addr:            SeC and BRIDGE bars
     31 * @aliveness:           aliveness (power gating) state of the hardware
     32 * @readiness:           readiness state of the hardware
     33 * @slots:               number of empty slots
     34 * @wait_aliveness_resp: aliveness wait queue
     35 * @intr_cause:          translated interrupt cause
     36 */
     37struct mei_txe_hw {
     38	void __iomem * const *mem_addr;
     39	u32 aliveness;
     40	u32 readiness;
     41	u32 slots;
     42
     43	wait_queue_head_t wait_aliveness_resp;
     44
     45	unsigned long intr_cause;
     46};
     47
     48#define to_txe_hw(dev) (struct mei_txe_hw *)((dev)->hw)
     49
     50static inline struct mei_device *hw_txe_to_mei(struct mei_txe_hw *hw)
     51{
     52	return container_of((void *)hw, struct mei_device, hw);
     53}
     54
     55struct mei_device *mei_txe_dev_init(struct pci_dev *pdev);
     56
     57irqreturn_t mei_txe_irq_quick_handler(int irq, void *dev_id);
     58irqreturn_t mei_txe_irq_thread_handler(int irq, void *dev_id);
     59
     60int mei_txe_aliveness_set_sync(struct mei_device *dev, u32 req);
     61
     62int mei_txe_setup_satt2(struct mei_device *dev, phys_addr_t addr, u32 range);
     63
     64
     65#endif /* _MEI_HW_TXE_H_ */