cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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samsung.h (1532B)


      1/* SPDX-License-Identifier: GPL-2.0-only */
      2/*
      3 *  Copyright (C) 2008-2010 Samsung Electronics
      4 *  Kyungmin Park <kyungmin.park@samsung.com>
      5 */
      6#ifndef __SAMSUNG_ONENAND_H__
      7#define __SAMSUNG_ONENAND_H__
      8
      9/*
     10 * OneNAND Controller
     11 */
     12#define MEM_CFG_OFFSET		0x0000
     13#define BURST_LEN_OFFSET	0x0010
     14#define MEM_RESET_OFFSET	0x0020
     15#define INT_ERR_STAT_OFFSET	0x0030
     16#define INT_ERR_MASK_OFFSET	0x0040
     17#define INT_ERR_ACK_OFFSET	0x0050
     18#define ECC_ERR_STAT_OFFSET	0x0060
     19#define MANUFACT_ID_OFFSET	0x0070
     20#define DEVICE_ID_OFFSET	0x0080
     21#define DATA_BUF_SIZE_OFFSET	0x0090
     22#define BOOT_BUF_SIZE_OFFSET	0x00A0
     23#define BUF_AMOUNT_OFFSET	0x00B0
     24#define TECH_OFFSET		0x00C0
     25#define FBA_WIDTH_OFFSET	0x00D0
     26#define FPA_WIDTH_OFFSET	0x00E0
     27#define FSA_WIDTH_OFFSET	0x00F0
     28#define TRANS_SPARE_OFFSET	0x0140
     29#define DBS_DFS_WIDTH_OFFSET	0x0160
     30#define INT_PIN_ENABLE_OFFSET	0x01A0
     31#define ACC_CLOCK_OFFSET	0x01C0
     32#define FLASH_VER_ID_OFFSET	0x01F0
     33#define FLASH_AUX_CNTRL_OFFSET	0x0300		/* s3c64xx only */
     34
     35#define ONENAND_MEM_RESET_HOT	0x3
     36#define ONENAND_MEM_RESET_COLD	0x2
     37#define ONENAND_MEM_RESET_WARM	0x1
     38
     39#define CACHE_OP_ERR		(1 << 13)
     40#define RST_CMP			(1 << 12)
     41#define RDY_ACT			(1 << 11)
     42#define INT_ACT			(1 << 10)
     43#define UNSUP_CMD		(1 << 9)
     44#define LOCKED_BLK		(1 << 8)
     45#define BLK_RW_CMP		(1 << 7)
     46#define ERS_CMP			(1 << 6)
     47#define PGM_CMP			(1 << 5)
     48#define LOAD_CMP		(1 << 4)
     49#define ERS_FAIL		(1 << 3)
     50#define PGM_FAIL		(1 << 2)
     51#define INT_TO			(1 << 1)
     52#define LD_FAIL_ECC_ERR		(1 << 0)
     53
     54#define TSRF			(1 << 0)
     55
     56#endif