cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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gpmi-nand.h (5521B)


      1/* SPDX-License-Identifier: GPL-2.0+ */
      2/*
      3 * Freescale GPMI NAND Flash Driver
      4 *
      5 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
      6 * Copyright (C) 2008 Embedded Alley Solutions, Inc.
      7 */
      8#ifndef __DRIVERS_MTD_NAND_GPMI_NAND_H
      9#define __DRIVERS_MTD_NAND_GPMI_NAND_H
     10
     11#include <linux/mtd/rawnand.h>
     12#include <linux/platform_device.h>
     13#include <linux/dma-mapping.h>
     14#include <linux/dmaengine.h>
     15
     16#define GPMI_CLK_MAX 5 /* MX6Q needs five clocks */
     17struct resources {
     18	void __iomem  *gpmi_regs;
     19	void __iomem  *bch_regs;
     20	unsigned int  dma_low_channel;
     21	unsigned int  dma_high_channel;
     22	struct clk    *clock[GPMI_CLK_MAX];
     23};
     24
     25/**
     26 * struct bch_geometry - BCH geometry description.
     27 * @gf_len:                   The length of Galois Field. (e.g., 13 or 14)
     28 * @ecc_strength:             A number that describes the strength of the ECC
     29 *                            algorithm.
     30 * @page_size:                The size, in bytes, of a physical page, including
     31 *                            both data and OOB.
     32 * @metadata_size:            The size, in bytes, of the metadata.
     33 * @ecc0_chunk_size:          The size, in bytes, of a first ECC chunk.
     34 * @eccn_chunk_size:          The size, in bytes, of a single ECC chunk after
     35 *                            the first chunk in the page.
     36 * @ecc_chunk_count:          The number of ECC chunks in the page,
     37 * @payload_size:             The size, in bytes, of the payload buffer.
     38 * @auxiliary_size:           The size, in bytes, of the auxiliary buffer.
     39 * @auxiliary_status_offset:  The offset into the auxiliary buffer at which
     40 *                            the ECC status appears.
     41 * @block_mark_byte_offset:   The byte offset in the ECC-based page view at
     42 *                            which the underlying physical block mark appears.
     43 * @block_mark_bit_offset:    The bit offset into the ECC-based page view at
     44 *                            which the underlying physical block mark appears.
     45 * @ecc_for_meta:             The flag to indicate if there is a dedicate ecc
     46 *                            for meta.
     47 */
     48struct bch_geometry {
     49	unsigned int  gf_len;
     50	unsigned int  ecc_strength;
     51	unsigned int  page_size;
     52	unsigned int  metadata_size;
     53	unsigned int  ecc0_chunk_size;
     54	unsigned int  eccn_chunk_size;
     55	unsigned int  ecc_chunk_count;
     56	unsigned int  payload_size;
     57	unsigned int  auxiliary_size;
     58	unsigned int  auxiliary_status_offset;
     59	unsigned int  block_mark_byte_offset;
     60	unsigned int  block_mark_bit_offset;
     61	unsigned int  ecc_for_meta; /* ECC for meta data */
     62};
     63
     64/**
     65 * struct boot_rom_geometry - Boot ROM geometry description.
     66 * @stride_size_in_pages:        The size of a boot block stride, in pages.
     67 * @search_area_stride_exponent: The logarithm to base 2 of the size of a
     68 *                               search area in boot block strides.
     69 */
     70struct boot_rom_geometry {
     71	unsigned int  stride_size_in_pages;
     72	unsigned int  search_area_stride_exponent;
     73};
     74
     75enum gpmi_type {
     76	IS_MX23,
     77	IS_MX28,
     78	IS_MX6Q,
     79	IS_MX6SX,
     80	IS_MX7D,
     81};
     82
     83struct gpmi_devdata {
     84	enum gpmi_type type;
     85	int bch_max_ecc_strength;
     86	int max_chain_delay; /* See the SDR EDO mode */
     87	const char * const *clks;
     88	const int clks_count;
     89};
     90
     91/**
     92 * struct gpmi_nfc_hardware_timing - GPMI hardware timing parameters.
     93 * @must_apply_timings:        Whether controller timings have already been
     94 *                             applied or not (useful only while there is
     95 *                             support for only one chip select)
     96 * @clk_rate:                  The clock rate that must be used to derive the
     97 *                             following parameters
     98 * @timing0:                   HW_GPMI_TIMING0 register
     99 * @timing1:                   HW_GPMI_TIMING1 register
    100 * @ctrl1n:                    HW_GPMI_CTRL1n register
    101 */
    102struct gpmi_nfc_hardware_timing {
    103	bool must_apply_timings;
    104	unsigned long int clk_rate;
    105	u32 timing0;
    106	u32 timing1;
    107	u32 ctrl1n;
    108};
    109
    110#define GPMI_MAX_TRANSFERS	8
    111
    112struct gpmi_transfer {
    113	u8 cmdbuf[8];
    114	struct scatterlist sgl;
    115	enum dma_data_direction direction;
    116};
    117
    118struct gpmi_nand_data {
    119	/* Devdata */
    120	const struct gpmi_devdata *devdata;
    121
    122	/* System Interface */
    123	struct device		*dev;
    124	struct platform_device	*pdev;
    125
    126	/* Resources */
    127	struct resources	resources;
    128
    129	/* Flash Hardware */
    130	struct gpmi_nfc_hardware_timing hw;
    131
    132	/* BCH */
    133	struct bch_geometry	bch_geometry;
    134	struct completion	bch_done;
    135
    136	/* NAND Boot issue */
    137	bool			swap_block_mark;
    138	struct boot_rom_geometry rom_geometry;
    139
    140	/* MTD / NAND */
    141	struct nand_controller	base;
    142	struct nand_chip	nand;
    143
    144	struct gpmi_transfer	transfers[GPMI_MAX_TRANSFERS];
    145	int			ntransfers;
    146
    147	bool			bch;
    148	uint32_t		bch_flashlayout0;
    149	uint32_t		bch_flashlayout1;
    150
    151	char			*data_buffer_dma;
    152
    153	void			*auxiliary_virt;
    154	dma_addr_t		auxiliary_phys;
    155
    156	void			*raw_buffer;
    157
    158	/* DMA channels */
    159#define DMA_CHANS		8
    160	struct dma_chan		*dma_chans[DMA_CHANS];
    161	struct completion	dma_done;
    162};
    163
    164/* BCH : Status Block Completion Codes */
    165#define STATUS_GOOD		0x00
    166#define STATUS_ERASED		0xff
    167#define STATUS_UNCORRECTABLE	0xfe
    168
    169/* Use the devdata to distinguish different Archs. */
    170#define GPMI_IS_MX23(x)		((x)->devdata->type == IS_MX23)
    171#define GPMI_IS_MX28(x)		((x)->devdata->type == IS_MX28)
    172#define GPMI_IS_MX6Q(x)		((x)->devdata->type == IS_MX6Q)
    173#define GPMI_IS_MX6SX(x)	((x)->devdata->type == IS_MX6SX)
    174#define GPMI_IS_MX7D(x)		((x)->devdata->type == IS_MX7D)
    175
    176#define GPMI_IS_MX6(x)		(GPMI_IS_MX6Q(x) || GPMI_IS_MX6SX(x) || \
    177				 GPMI_IS_MX7D(x))
    178#define GPMI_IS_MXS(x)		(GPMI_IS_MX23(x) || GPMI_IS_MX28(x))
    179#endif