cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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gigadevice.c (2234B)


      1// SPDX-License-Identifier: GPL-2.0
      2/*
      3 * Copyright (C) 2005, Intec Automation Inc.
      4 * Copyright (C) 2014, Freescale Semiconductor, Inc.
      5 */
      6
      7#include <linux/mtd/spi-nor.h>
      8
      9#include "core.h"
     10
     11static void gd25q256_default_init(struct spi_nor *nor)
     12{
     13	/*
     14	 * Some manufacturer like GigaDevice may use different
     15	 * bit to set QE on different memories, so the MFR can't
     16	 * indicate the quad_enable method for this case, we need
     17	 * to set it in the default_init fixup hook.
     18	 */
     19	nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;
     20}
     21
     22static const struct spi_nor_fixups gd25q256_fixups = {
     23	.default_init = gd25q256_default_init,
     24};
     25
     26static const struct flash_info gigadevice_nor_parts[] = {
     27	{ "gd25q16", INFO(0xc84015, 0, 64 * 1024,  32)
     28		FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
     29		NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
     30			      SPI_NOR_QUAD_READ) },
     31	{ "gd25q32", INFO(0xc84016, 0, 64 * 1024,  64)
     32		FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
     33		NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
     34			      SPI_NOR_QUAD_READ) },
     35	{ "gd25lq32", INFO(0xc86016, 0, 64 * 1024, 64)
     36		FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
     37		NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
     38			      SPI_NOR_QUAD_READ) },
     39	{ "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128)
     40		FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
     41		NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
     42			      SPI_NOR_QUAD_READ) },
     43	{ "gd25lq64c", INFO(0xc86017, 0, 64 * 1024, 128)
     44		FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
     45		NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
     46			      SPI_NOR_QUAD_READ) },
     47	{ "gd25lq128d", INFO(0xc86018, 0, 64 * 1024, 256)
     48		FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
     49		NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
     50			      SPI_NOR_QUAD_READ) },
     51	{ "gd25q128", INFO(0xc84018, 0, 64 * 1024, 256)
     52		FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
     53		NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
     54			      SPI_NOR_QUAD_READ) },
     55	{ "gd25q256", INFO(0xc84019, 0, 64 * 1024, 512)
     56		PARSE_SFDP
     57		FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6)
     58		FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
     59		.fixups = &gd25q256_fixups },
     60};
     61
     62const struct spi_nor_manufacturer spi_nor_gigadevice = {
     63	.name = "gigadevice",
     64	.parts = gigadevice_nor_parts,
     65	.nparts = ARRAY_SIZE(gigadevice_nor_parts),
     66};