cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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ctucanfd_kregs.h (10747B)

      1/* SPDX-License-Identifier: GPL-2.0-or-later */
      2/*******************************************************************************
      3 *
      4 * CTU CAN FD IP Core
      5 *
      6 * Copyright (C) 2015-2018 Ondrej Ille <ondrej.ille@gmail.com> FEE CTU
      7 * Copyright (C) 2018-2021 Ondrej Ille <ondrej.ille@gmail.com> self-funded
      8 * Copyright (C) 2018-2019 Martin Jerabek <martin.jerabek01@gmail.com> FEE CTU
      9 * Copyright (C) 2018-2021 Pavel Pisa <pisa@cmp.felk.cvut.cz> FEE CTU/self-funded
     10 *
     11 * Project advisors:
     12 *     Jiri Novak <jnovak@fel.cvut.cz>
     13 *     Pavel Pisa <pisa@cmp.felk.cvut.cz>
     14 *
     15 * Department of Measurement         (http://meas.fel.cvut.cz/)
     16 * Faculty of Electrical Engineering (http://www.fel.cvut.cz)
     17 * Czech Technical University        (http://www.cvut.cz/)
     18 ******************************************************************************/
     19
     20/* This file is autogenerated, DO NOT EDIT! */
     21
     22#ifndef __CTU_CAN_FD_CAN_FD_REGISTER_MAP__
     23#define __CTU_CAN_FD_CAN_FD_REGISTER_MAP__
     24
     25#include <linux/bits.h>
     26
     27/* CAN_Registers memory map */
     28enum ctu_can_fd_can_registers {
     29	CTUCANFD_DEVICE_ID             = 0x0,
     30	CTUCANFD_VERSION               = 0x2,
     31	CTUCANFD_MODE                  = 0x4,
     32	CTUCANFD_SETTINGS              = 0x6,
     33	CTUCANFD_STATUS                = 0x8,
     34	CTUCANFD_COMMAND               = 0xc,
     35	CTUCANFD_INT_STAT             = 0x10,
     36	CTUCANFD_INT_ENA_SET          = 0x14,
     37	CTUCANFD_INT_ENA_CLR          = 0x18,
     38	CTUCANFD_INT_MASK_SET         = 0x1c,
     39	CTUCANFD_INT_MASK_CLR         = 0x20,
     40	CTUCANFD_BTR                  = 0x24,
     41	CTUCANFD_BTR_FD               = 0x28,
     42	CTUCANFD_EWL                  = 0x2c,
     43	CTUCANFD_ERP                  = 0x2d,
     44	CTUCANFD_FAULT_STATE          = 0x2e,
     45	CTUCANFD_REC                  = 0x30,
     46	CTUCANFD_TEC                  = 0x32,
     47	CTUCANFD_ERR_NORM             = 0x34,
     48	CTUCANFD_ERR_FD               = 0x36,
     49	CTUCANFD_CTR_PRES             = 0x38,
     50	CTUCANFD_FILTER_A_MASK        = 0x3c,
     51	CTUCANFD_FILTER_A_VAL         = 0x40,
     52	CTUCANFD_FILTER_B_MASK        = 0x44,
     53	CTUCANFD_FILTER_B_VAL         = 0x48,
     54	CTUCANFD_FILTER_C_MASK        = 0x4c,
     55	CTUCANFD_FILTER_C_VAL         = 0x50,
     56	CTUCANFD_FILTER_RAN_LOW       = 0x54,
     57	CTUCANFD_FILTER_RAN_HIGH      = 0x58,
     58	CTUCANFD_FILTER_CONTROL       = 0x5c,
     59	CTUCANFD_FILTER_STATUS        = 0x5e,
     60	CTUCANFD_RX_MEM_INFO          = 0x60,
     61	CTUCANFD_RX_POINTERS          = 0x64,
     62	CTUCANFD_RX_STATUS            = 0x68,
     63	CTUCANFD_RX_SETTINGS          = 0x6a,
     64	CTUCANFD_RX_DATA              = 0x6c,
     65	CTUCANFD_TX_STATUS            = 0x70,
     66	CTUCANFD_TX_COMMAND           = 0x74,
     67	CTUCANFD_TX_PRIORITY          = 0x78,
     68	CTUCANFD_ERR_CAPT             = 0x7c,
     69	CTUCANFD_ALC                  = 0x7e,
     70	CTUCANFD_TRV_DELAY            = 0x80,
     71	CTUCANFD_SSP_CFG              = 0x82,
     72	CTUCANFD_RX_FR_CTR            = 0x84,
     73	CTUCANFD_TX_FR_CTR            = 0x88,
     74	CTUCANFD_DEBUG_REGISTER       = 0x8c,
     75	CTUCANFD_YOLO_REG             = 0x90,
     76	CTUCANFD_TIMESTAMP_LOW        = 0x94,
     77	CTUCANFD_TIMESTAMP_HIGH       = 0x98,
     78	CTUCANFD_TXTB1_DATA_1        = 0x100,
     79	CTUCANFD_TXTB1_DATA_2        = 0x104,
     80	CTUCANFD_TXTB1_DATA_20       = 0x14c,
     81	CTUCANFD_TXTB2_DATA_1        = 0x200,
     82	CTUCANFD_TXTB2_DATA_2        = 0x204,
     83	CTUCANFD_TXTB2_DATA_20       = 0x24c,
     84	CTUCANFD_TXTB3_DATA_1        = 0x300,
     85	CTUCANFD_TXTB3_DATA_2        = 0x304,
     86	CTUCANFD_TXTB3_DATA_20       = 0x34c,
     87	CTUCANFD_TXTB4_DATA_1        = 0x400,
     88	CTUCANFD_TXTB4_DATA_2        = 0x404,
     89	CTUCANFD_TXTB4_DATA_20       = 0x44c,
     90};
     91
     92/* Control_registers memory region */
     93
     94/*  DEVICE_ID VERSION registers */
     95#define REG_DEVICE_ID_DEVICE_ID GENMASK(15, 0)
     96#define REG_DEVICE_ID_VER_MINOR GENMASK(23, 16)
     97#define REG_DEVICE_ID_VER_MAJOR GENMASK(31, 24)
     98
     99/*  MODE SETTINGS registers */
    100#define REG_MODE_RST BIT(0)
    101#define REG_MODE_BMM BIT(1)
    102#define REG_MODE_STM BIT(2)
    103#define REG_MODE_AFM BIT(3)
    104#define REG_MODE_FDE BIT(4)
    105#define REG_MODE_ACF BIT(7)
    106#define REG_MODE_TSTM BIT(8)
    107#define REG_MODE_RTRLE BIT(16)
    108#define REG_MODE_RTRTH GENMASK(20, 17)
    109#define REG_MODE_ILBP BIT(21)
    110#define REG_MODE_ENA BIT(22)
    111#define REG_MODE_NISOFD BIT(23)
    112#define REG_MODE_PEX BIT(24)
    113#define REG_MODE_TBFBO BIT(25)
    114#define REG_MODE_FDRF BIT(26)
    115
    116/*  STATUS registers */
    117#define REG_STATUS_RXNE BIT(0)
    118#define REG_STATUS_DOR BIT(1)
    119#define REG_STATUS_TXNF BIT(2)
    120#define REG_STATUS_EFT BIT(3)
    121#define REG_STATUS_RXS BIT(4)
    122#define REG_STATUS_TXS BIT(5)
    123#define REG_STATUS_EWL BIT(6)
    124#define REG_STATUS_IDLE BIT(7)
    125#define REG_STATUS_PEXS BIT(8)
    126
    127/*  COMMAND registers */
    128#define REG_COMMAND_RRB BIT(2)
    129#define REG_COMMAND_CDO BIT(3)
    130#define REG_COMMAND_ERCRST BIT(4)
    131#define REG_COMMAND_RXFCRST BIT(5)
    132#define REG_COMMAND_TXFCRST BIT(6)
    133#define REG_COMMAND_CPEXS BIT(7)
    134
    135/*  INT_STAT registers */
    136#define REG_INT_STAT_RXI BIT(0)
    137#define REG_INT_STAT_TXI BIT(1)
    138#define REG_INT_STAT_EWLI BIT(2)
    139#define REG_INT_STAT_DOI BIT(3)
    140#define REG_INT_STAT_FCSI BIT(4)
    141#define REG_INT_STAT_ALI BIT(5)
    142#define REG_INT_STAT_BEI BIT(6)
    143#define REG_INT_STAT_OFI BIT(7)
    144#define REG_INT_STAT_RXFI BIT(8)
    145#define REG_INT_STAT_BSI BIT(9)
    146#define REG_INT_STAT_RBNEI BIT(10)
    147#define REG_INT_STAT_TXBHCI BIT(11)
    148
    149/*  INT_ENA_SET registers */
    150#define REG_INT_ENA_SET_INT_ENA_SET GENMASK(11, 0)
    151
    152/*  INT_ENA_CLR registers */
    153#define REG_INT_ENA_CLR_INT_ENA_CLR GENMASK(11, 0)
    154
    155/*  INT_MASK_SET registers */
    156#define REG_INT_MASK_SET_INT_MASK_SET GENMASK(11, 0)
    157
    158/*  INT_MASK_CLR registers */
    159#define REG_INT_MASK_CLR_INT_MASK_CLR GENMASK(11, 0)
    160
    161/*  BTR registers */
    162#define REG_BTR_PROP GENMASK(6, 0)
    163#define REG_BTR_PH1 GENMASK(12, 7)
    164#define REG_BTR_PH2 GENMASK(18, 13)
    165#define REG_BTR_BRP GENMASK(26, 19)
    166#define REG_BTR_SJW GENMASK(31, 27)
    167
    168/*  BTR_FD registers */
    169#define REG_BTR_FD_PROP_FD GENMASK(5, 0)
    170#define REG_BTR_FD_PH1_FD GENMASK(11, 7)
    171#define REG_BTR_FD_PH2_FD GENMASK(17, 13)
    172#define REG_BTR_FD_BRP_FD GENMASK(26, 19)
    173#define REG_BTR_FD_SJW_FD GENMASK(31, 27)
    174
    175/*  EWL ERP FAULT_STATE registers */
    176#define REG_EWL_EW_LIMIT GENMASK(7, 0)
    177#define REG_EWL_ERP_LIMIT GENMASK(15, 8)
    178#define REG_EWL_ERA BIT(16)
    179#define REG_EWL_ERP BIT(17)
    180#define REG_EWL_BOF BIT(18)
    181
    182/*  REC TEC registers */
    183#define REG_REC_REC_VAL GENMASK(8, 0)
    184#define REG_REC_TEC_VAL GENMASK(24, 16)
    185
    186/*  ERR_NORM ERR_FD registers */
    187#define REG_ERR_NORM_ERR_NORM_VAL GENMASK(15, 0)
    188#define REG_ERR_NORM_ERR_FD_VAL GENMASK(31, 16)
    189
    190/*  CTR_PRES registers */
    191#define REG_CTR_PRES_CTPV GENMASK(8, 0)
    192#define REG_CTR_PRES_PTX BIT(9)
    193#define REG_CTR_PRES_PRX BIT(10)
    194#define REG_CTR_PRES_ENORM BIT(11)
    195#define REG_CTR_PRES_EFD BIT(12)
    196
    197/*  FILTER_A_MASK registers */
    198#define REG_FILTER_A_MASK_BIT_MASK_A_VAL GENMASK(28, 0)
    199
    200/*  FILTER_A_VAL registers */
    201#define REG_FILTER_A_VAL_BIT_VAL_A_VAL GENMASK(28, 0)
    202
    203/*  FILTER_B_MASK registers */
    204#define REG_FILTER_B_MASK_BIT_MASK_B_VAL GENMASK(28, 0)
    205
    206/*  FILTER_B_VAL registers */
    207#define REG_FILTER_B_VAL_BIT_VAL_B_VAL GENMASK(28, 0)
    208
    209/*  FILTER_C_MASK registers */
    210#define REG_FILTER_C_MASK_BIT_MASK_C_VAL GENMASK(28, 0)
    211
    212/*  FILTER_C_VAL registers */
    213#define REG_FILTER_C_VAL_BIT_VAL_C_VAL GENMASK(28, 0)
    214
    215/*  FILTER_RAN_LOW registers */
    216#define REG_FILTER_RAN_LOW_BIT_RAN_LOW_VAL GENMASK(28, 0)
    217
    218/*  FILTER_RAN_HIGH registers */
    219#define REG_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL GENMASK(28, 0)
    220
    221/*  FILTER_CONTROL FILTER_STATUS registers */
    222#define REG_FILTER_CONTROL_FANB BIT(0)
    223#define REG_FILTER_CONTROL_FANE BIT(1)
    224#define REG_FILTER_CONTROL_FAFB BIT(2)
    225#define REG_FILTER_CONTROL_FAFE BIT(3)
    226#define REG_FILTER_CONTROL_FBNB BIT(4)
    227#define REG_FILTER_CONTROL_FBNE BIT(5)
    228#define REG_FILTER_CONTROL_FBFB BIT(6)
    229#define REG_FILTER_CONTROL_FBFE BIT(7)
    230#define REG_FILTER_CONTROL_FCNB BIT(8)
    231#define REG_FILTER_CONTROL_FCNE BIT(9)
    232#define REG_FILTER_CONTROL_FCFB BIT(10)
    233#define REG_FILTER_CONTROL_FCFE BIT(11)
    234#define REG_FILTER_CONTROL_FRNB BIT(12)
    235#define REG_FILTER_CONTROL_FRNE BIT(13)
    236#define REG_FILTER_CONTROL_FRFB BIT(14)
    237#define REG_FILTER_CONTROL_FRFE BIT(15)
    238#define REG_FILTER_CONTROL_SFA BIT(16)
    239#define REG_FILTER_CONTROL_SFB BIT(17)
    240#define REG_FILTER_CONTROL_SFC BIT(18)
    241#define REG_FILTER_CONTROL_SFR BIT(19)
    242
    243/*  RX_MEM_INFO registers */
    244#define REG_RX_MEM_INFO_RX_BUFF_SIZE GENMASK(12, 0)
    245#define REG_RX_MEM_INFO_RX_MEM_FREE GENMASK(28, 16)
    246
    247/*  RX_POINTERS registers */
    248#define REG_RX_POINTERS_RX_WPP GENMASK(11, 0)
    249#define REG_RX_POINTERS_RX_RPP GENMASK(27, 16)
    250
    251/*  RX_STATUS RX_SETTINGS registers */
    252#define REG_RX_STATUS_RXE BIT(0)
    253#define REG_RX_STATUS_RXF BIT(1)
    254#define REG_RX_STATUS_RXMOF BIT(2)
    255#define REG_RX_STATUS_RXFRC GENMASK(14, 4)
    256#define REG_RX_STATUS_RTSOP BIT(16)
    257
    258/*  RX_DATA registers */
    259#define REG_RX_DATA_RX_DATA GENMASK(31, 0)
    260
    261/*  TX_STATUS registers */
    262#define REG_TX_STATUS_TX1S GENMASK(3, 0)
    263#define REG_TX_STATUS_TX2S GENMASK(7, 4)
    264#define REG_TX_STATUS_TX3S GENMASK(11, 8)
    265#define REG_TX_STATUS_TX4S GENMASK(15, 12)
    266
    267/*  TX_COMMAND registers */
    268#define REG_TX_COMMAND_TXCE BIT(0)
    269#define REG_TX_COMMAND_TXCR BIT(1)
    270#define REG_TX_COMMAND_TXCA BIT(2)
    271#define REG_TX_COMMAND_TXB1 BIT(8)
    272#define REG_TX_COMMAND_TXB2 BIT(9)
    273#define REG_TX_COMMAND_TXB3 BIT(10)
    274#define REG_TX_COMMAND_TXB4 BIT(11)
    275
    276/*  TX_PRIORITY registers */
    277#define REG_TX_PRIORITY_TXT1P GENMASK(2, 0)
    278#define REG_TX_PRIORITY_TXT2P GENMASK(6, 4)
    279#define REG_TX_PRIORITY_TXT3P GENMASK(10, 8)
    280#define REG_TX_PRIORITY_TXT4P GENMASK(14, 12)
    281
    282/*  ERR_CAPT ALC registers */
    283#define REG_ERR_CAPT_ERR_POS GENMASK(4, 0)
    284#define REG_ERR_CAPT_ERR_TYPE GENMASK(7, 5)
    285#define REG_ERR_CAPT_ALC_BIT GENMASK(20, 16)
    286#define REG_ERR_CAPT_ALC_ID_FIELD GENMASK(23, 21)
    287
    288/*  TRV_DELAY SSP_CFG registers */
    289#define REG_TRV_DELAY_TRV_DELAY_VALUE GENMASK(6, 0)
    290#define REG_TRV_DELAY_SSP_OFFSET GENMASK(23, 16)
    291#define REG_TRV_DELAY_SSP_SRC GENMASK(25, 24)
    292
    293/*  RX_FR_CTR registers */
    294#define REG_RX_FR_CTR_RX_FR_CTR_VAL GENMASK(31, 0)
    295
    296/*  TX_FR_CTR registers */
    297#define REG_TX_FR_CTR_TX_FR_CTR_VAL GENMASK(31, 0)
    298
    299/*  DEBUG_REGISTER registers */
    300#define REG_DEBUG_REGISTER_STUFF_COUNT GENMASK(2, 0)
    301#define REG_DEBUG_REGISTER_DESTUFF_COUNT GENMASK(5, 3)
    302#define REG_DEBUG_REGISTER_PC_ARB BIT(6)
    303#define REG_DEBUG_REGISTER_PC_CON BIT(7)
    304#define REG_DEBUG_REGISTER_PC_DAT BIT(8)
    305#define REG_DEBUG_REGISTER_PC_STC BIT(9)
    306#define REG_DEBUG_REGISTER_PC_CRC BIT(10)
    307#define REG_DEBUG_REGISTER_PC_CRCD BIT(11)
    308#define REG_DEBUG_REGISTER_PC_ACK BIT(12)
    309#define REG_DEBUG_REGISTER_PC_ACKD BIT(13)
    310#define REG_DEBUG_REGISTER_PC_EOF BIT(14)
    311#define REG_DEBUG_REGISTER_PC_INT BIT(15)
    312#define REG_DEBUG_REGISTER_PC_SUSP BIT(16)
    313#define REG_DEBUG_REGISTER_PC_OVR BIT(17)
    314#define REG_DEBUG_REGISTER_PC_SOF BIT(18)
    315
    316/*  YOLO_REG registers */
    317#define REG_YOLO_REG_YOLO_VAL GENMASK(31, 0)
    318
    319/*  TIMESTAMP_LOW registers */
    320#define REG_TIMESTAMP_LOW_TIMESTAMP_LOW GENMASK(31, 0)
    321
    322/*  TIMESTAMP_HIGH registers */
    323#define REG_TIMESTAMP_HIGH_TIMESTAMP_HIGH GENMASK(31, 0)
    324
    325#endif