cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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sja1000.h (5564B)


      1/*
      2 * sja1000.h -  Philips SJA1000 network device driver
      3 *
      4 * Copyright (c) 2003 Matthias Brukner, Trajet Gmbh, Rebenring 33,
      5 * 38106 Braunschweig, GERMANY
      6 *
      7 * Copyright (c) 2002-2007 Volkswagen Group Electronic Research
      8 * All rights reserved.
      9 *
     10 * Redistribution and use in source and binary forms, with or without
     11 * modification, are permitted provided that the following conditions
     12 * are met:
     13 * 1. Redistributions of source code must retain the above copyright
     14 *    notice, this list of conditions and the following disclaimer.
     15 * 2. Redistributions in binary form must reproduce the above copyright
     16 *    notice, this list of conditions and the following disclaimer in the
     17 *    documentation and/or other materials provided with the distribution.
     18 * 3. Neither the name of Volkswagen nor the names of its contributors
     19 *    may be used to endorse or promote products derived from this software
     20 *    without specific prior written permission.
     21 *
     22 * Alternatively, provided that this notice is retained in full, this
     23 * software may be distributed under the terms of the GNU General
     24 * Public License ("GPL") version 2, in which case the provisions of the
     25 * GPL apply INSTEAD OF those given above.
     26 *
     27 * The provided data structures and external interfaces from this code
     28 * are not restricted to be used by modules with a GPL compatible license.
     29 *
     30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
     31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
     32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
     33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
     34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
     35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
     36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
     40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
     41 * DAMAGE.
     42 *
     43 */
     44
     45#ifndef SJA1000_DEV_H
     46#define SJA1000_DEV_H
     47
     48#include <linux/irqreturn.h>
     49#include <linux/can/dev.h>
     50#include <linux/can/platform/sja1000.h>
     51
     52#define SJA1000_ECHO_SKB_MAX	1 /* the SJA1000 has one TX buffer object */
     53
     54#define SJA1000_MAX_IRQ 20	/* max. number of interrupts handled in ISR */
     55
     56/* SJA1000 registers - manual section 6.4 (Pelican Mode) */
     57#define SJA1000_MOD		0x00
     58#define SJA1000_CMR		0x01
     59#define SJA1000_SR		0x02
     60#define SJA1000_IR		0x03
     61#define SJA1000_IER		0x04
     62#define SJA1000_ALC		0x0B
     63#define SJA1000_ECC		0x0C
     64#define SJA1000_EWL		0x0D
     65#define SJA1000_RXERR		0x0E
     66#define SJA1000_TXERR		0x0F
     67#define SJA1000_ACCC0		0x10
     68#define SJA1000_ACCC1		0x11
     69#define SJA1000_ACCC2		0x12
     70#define SJA1000_ACCC3		0x13
     71#define SJA1000_ACCM0		0x14
     72#define SJA1000_ACCM1		0x15
     73#define SJA1000_ACCM2		0x16
     74#define SJA1000_ACCM3		0x17
     75#define SJA1000_RMC		0x1D
     76#define SJA1000_RBSA		0x1E
     77
     78/* Common registers - manual section 6.5 */
     79#define SJA1000_BTR0		0x06
     80#define SJA1000_BTR1		0x07
     81#define SJA1000_OCR		0x08
     82#define SJA1000_CDR		0x1F
     83
     84#define SJA1000_FI		0x10
     85#define SJA1000_SFF_BUF		0x13
     86#define SJA1000_EFF_BUF		0x15
     87
     88#define SJA1000_FI_FF		0x80
     89#define SJA1000_FI_RTR		0x40
     90
     91#define SJA1000_ID1		0x11
     92#define SJA1000_ID2		0x12
     93#define SJA1000_ID3		0x13
     94#define SJA1000_ID4		0x14
     95
     96#define SJA1000_CAN_RAM		0x20
     97
     98/* mode register */
     99#define MOD_RM		0x01
    100#define MOD_LOM		0x02
    101#define MOD_STM		0x04
    102#define MOD_AFM		0x08
    103#define MOD_SM		0x10
    104
    105/* commands */
    106#define CMD_SRR		0x10
    107#define CMD_CDO		0x08
    108#define CMD_RRB		0x04
    109#define CMD_AT		0x02
    110#define CMD_TR		0x01
    111
    112/* interrupt sources */
    113#define IRQ_BEI		0x80
    114#define IRQ_ALI		0x40
    115#define IRQ_EPI		0x20
    116#define IRQ_WUI		0x10
    117#define IRQ_DOI		0x08
    118#define IRQ_EI		0x04
    119#define IRQ_TI		0x02
    120#define IRQ_RI		0x01
    121#define IRQ_ALL		0xFF
    122#define IRQ_OFF		0x00
    123
    124/* status register content */
    125#define SR_BS		0x80
    126#define SR_ES		0x40
    127#define SR_TS		0x20
    128#define SR_RS		0x10
    129#define SR_TCS		0x08
    130#define SR_TBS		0x04
    131#define SR_DOS		0x02
    132#define SR_RBS		0x01
    133
    134#define SR_CRIT (SR_BS|SR_ES)
    135
    136/* ECC register */
    137#define ECC_SEG		0x1F
    138#define ECC_DIR		0x20
    139#define ECC_ERR		6
    140#define ECC_BIT		0x00
    141#define ECC_FORM	0x40
    142#define ECC_STUFF	0x80
    143#define ECC_MASK	0xc0
    144
    145/*
    146 * Flags for sja1000priv.flags
    147 */
    148#define SJA1000_CUSTOM_IRQ_HANDLER 0x1
    149
    150/*
    151 * SJA1000 private data structure
    152 */
    153struct sja1000_priv {
    154	struct can_priv can;	/* must be the first member */
    155	struct sk_buff *echo_skb;
    156
    157	/* the lower-layer is responsible for appropriate locking */
    158	u8 (*read_reg) (const struct sja1000_priv *priv, int reg);
    159	void (*write_reg) (const struct sja1000_priv *priv, int reg, u8 val);
    160	void (*pre_irq) (const struct sja1000_priv *priv);
    161	void (*post_irq) (const struct sja1000_priv *priv);
    162
    163	void *priv;		/* for board-specific data */
    164	struct net_device *dev;
    165
    166	void __iomem *reg_base;	 /* ioremap'ed address to registers */
    167	unsigned long irq_flags; /* for request_irq() */
    168	spinlock_t cmdreg_lock;  /* lock for concurrent cmd register writes */
    169
    170	u16 flags;		/* custom mode flags */
    171	u8 ocr;			/* output control register */
    172	u8 cdr;			/* clock divider register */
    173};
    174
    175struct net_device *alloc_sja1000dev(int sizeof_priv);
    176void free_sja1000dev(struct net_device *dev);
    177int register_sja1000dev(struct net_device *dev);
    178void unregister_sja1000dev(struct net_device *dev);
    179
    180irqreturn_t sja1000_interrupt(int irq, void *dev_id);
    181
    182#endif /* SJA1000_DEV_H */