cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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mv88e6060.c (7691B)


      1// SPDX-License-Identifier: GPL-2.0+
      2/*
      3 * net/dsa/mv88e6060.c - Driver for Marvell 88e6060 switch chips
      4 * Copyright (c) 2008-2009 Marvell Semiconductor
      5 */
      6
      7#include <linux/delay.h>
      8#include <linux/etherdevice.h>
      9#include <linux/jiffies.h>
     10#include <linux/list.h>
     11#include <linux/module.h>
     12#include <linux/netdevice.h>
     13#include <linux/phy.h>
     14#include <net/dsa.h>
     15#include "mv88e6060.h"
     16
     17static int reg_read(struct mv88e6060_priv *priv, int addr, int reg)
     18{
     19	return mdiobus_read_nested(priv->bus, priv->sw_addr + addr, reg);
     20}
     21
     22static int reg_write(struct mv88e6060_priv *priv, int addr, int reg, u16 val)
     23{
     24	return mdiobus_write_nested(priv->bus, priv->sw_addr + addr, reg, val);
     25}
     26
     27static const char *mv88e6060_get_name(struct mii_bus *bus, int sw_addr)
     28{
     29	int ret;
     30
     31	ret = mdiobus_read(bus, sw_addr + REG_PORT(0), PORT_SWITCH_ID);
     32	if (ret >= 0) {
     33		if (ret == PORT_SWITCH_ID_6060)
     34			return "Marvell 88E6060 (A0)";
     35		if (ret == PORT_SWITCH_ID_6060_R1 ||
     36		    ret == PORT_SWITCH_ID_6060_R2)
     37			return "Marvell 88E6060 (B0)";
     38		if ((ret & PORT_SWITCH_ID_6060_MASK) == PORT_SWITCH_ID_6060)
     39			return "Marvell 88E6060";
     40	}
     41
     42	return NULL;
     43}
     44
     45static enum dsa_tag_protocol mv88e6060_get_tag_protocol(struct dsa_switch *ds,
     46							int port,
     47							enum dsa_tag_protocol m)
     48{
     49	return DSA_TAG_PROTO_TRAILER;
     50}
     51
     52static int mv88e6060_switch_reset(struct mv88e6060_priv *priv)
     53{
     54	int i;
     55	int ret;
     56	unsigned long timeout;
     57
     58	/* Set all ports to the disabled state. */
     59	for (i = 0; i < MV88E6060_PORTS; i++) {
     60		ret = reg_read(priv, REG_PORT(i), PORT_CONTROL);
     61		if (ret < 0)
     62			return ret;
     63		ret = reg_write(priv, REG_PORT(i), PORT_CONTROL,
     64				ret & ~PORT_CONTROL_STATE_MASK);
     65		if (ret)
     66			return ret;
     67	}
     68
     69	/* Wait for transmit queues to drain. */
     70	usleep_range(2000, 4000);
     71
     72	/* Reset the switch. */
     73	ret = reg_write(priv, REG_GLOBAL, GLOBAL_ATU_CONTROL,
     74			GLOBAL_ATU_CONTROL_SWRESET |
     75			GLOBAL_ATU_CONTROL_LEARNDIS);
     76	if (ret)
     77		return ret;
     78
     79	/* Wait up to one second for reset to complete. */
     80	timeout = jiffies + 1 * HZ;
     81	while (time_before(jiffies, timeout)) {
     82		ret = reg_read(priv, REG_GLOBAL, GLOBAL_STATUS);
     83		if (ret < 0)
     84			return ret;
     85
     86		if (ret & GLOBAL_STATUS_INIT_READY)
     87			break;
     88
     89		usleep_range(1000, 2000);
     90	}
     91	if (time_after(jiffies, timeout))
     92		return -ETIMEDOUT;
     93
     94	return 0;
     95}
     96
     97static int mv88e6060_setup_global(struct mv88e6060_priv *priv)
     98{
     99	int ret;
    100
    101	/* Disable discarding of frames with excessive collisions,
    102	 * set the maximum frame size to 1536 bytes, and mask all
    103	 * interrupt sources.
    104	 */
    105	ret = reg_write(priv, REG_GLOBAL, GLOBAL_CONTROL,
    106			GLOBAL_CONTROL_MAX_FRAME_1536);
    107	if (ret)
    108		return ret;
    109
    110	/* Disable automatic address learning.
    111	 */
    112	return reg_write(priv, REG_GLOBAL, GLOBAL_ATU_CONTROL,
    113			 GLOBAL_ATU_CONTROL_LEARNDIS);
    114}
    115
    116static int mv88e6060_setup_port(struct mv88e6060_priv *priv, int p)
    117{
    118	int addr = REG_PORT(p);
    119	int ret;
    120
    121	/* Do not force flow control, disable Ingress and Egress
    122	 * Header tagging, disable VLAN tunneling, and set the port
    123	 * state to Forwarding.  Additionally, if this is the CPU
    124	 * port, enable Ingress and Egress Trailer tagging mode.
    125	 */
    126	ret = reg_write(priv, addr, PORT_CONTROL,
    127			dsa_is_cpu_port(priv->ds, p) ?
    128			PORT_CONTROL_TRAILER |
    129			PORT_CONTROL_INGRESS_MODE |
    130			PORT_CONTROL_STATE_FORWARDING :
    131			PORT_CONTROL_STATE_FORWARDING);
    132	if (ret)
    133		return ret;
    134
    135	/* Port based VLAN map: give each port its own address
    136	 * database, allow the CPU port to talk to each of the 'real'
    137	 * ports, and allow each of the 'real' ports to only talk to
    138	 * the CPU port.
    139	 */
    140	ret = reg_write(priv, addr, PORT_VLAN_MAP,
    141			((p & 0xf) << PORT_VLAN_MAP_DBNUM_SHIFT) |
    142			(dsa_is_cpu_port(priv->ds, p) ?
    143			 dsa_user_ports(priv->ds) :
    144			 BIT(dsa_to_port(priv->ds, p)->cpu_dp->index)));
    145	if (ret)
    146		return ret;
    147
    148	/* Port Association Vector: when learning source addresses
    149	 * of packets, add the address to the address database using
    150	 * a port bitmap that has only the bit for this port set and
    151	 * the other bits clear.
    152	 */
    153	return reg_write(priv, addr, PORT_ASSOC_VECTOR, BIT(p));
    154}
    155
    156static int mv88e6060_setup_addr(struct mv88e6060_priv *priv)
    157{
    158	u8 addr[ETH_ALEN];
    159	int ret;
    160	u16 val;
    161
    162	eth_random_addr(addr);
    163
    164	val = addr[0] << 8 | addr[1];
    165
    166	/* The multicast bit is always transmitted as a zero, so the switch uses
    167	 * bit 8 for "DiffAddr", where 0 means all ports transmit the same SA.
    168	 */
    169	val &= 0xfeff;
    170
    171	ret = reg_write(priv, REG_GLOBAL, GLOBAL_MAC_01, val);
    172	if (ret)
    173		return ret;
    174
    175	ret = reg_write(priv, REG_GLOBAL, GLOBAL_MAC_23,
    176			(addr[2] << 8) | addr[3]);
    177	if (ret)
    178		return ret;
    179
    180	return reg_write(priv, REG_GLOBAL, GLOBAL_MAC_45,
    181			 (addr[4] << 8) | addr[5]);
    182}
    183
    184static int mv88e6060_setup(struct dsa_switch *ds)
    185{
    186	struct mv88e6060_priv *priv = ds->priv;
    187	int ret;
    188	int i;
    189
    190	priv->ds = ds;
    191
    192	ret = mv88e6060_switch_reset(priv);
    193	if (ret < 0)
    194		return ret;
    195
    196	/* @@@ initialise atu */
    197
    198	ret = mv88e6060_setup_global(priv);
    199	if (ret < 0)
    200		return ret;
    201
    202	ret = mv88e6060_setup_addr(priv);
    203	if (ret < 0)
    204		return ret;
    205
    206	for (i = 0; i < MV88E6060_PORTS; i++) {
    207		ret = mv88e6060_setup_port(priv, i);
    208		if (ret < 0)
    209			return ret;
    210	}
    211
    212	return 0;
    213}
    214
    215static int mv88e6060_port_to_phy_addr(int port)
    216{
    217	if (port >= 0 && port < MV88E6060_PORTS)
    218		return port;
    219	return -1;
    220}
    221
    222static int mv88e6060_phy_read(struct dsa_switch *ds, int port, int regnum)
    223{
    224	struct mv88e6060_priv *priv = ds->priv;
    225	int addr;
    226
    227	addr = mv88e6060_port_to_phy_addr(port);
    228	if (addr == -1)
    229		return 0xffff;
    230
    231	return reg_read(priv, addr, regnum);
    232}
    233
    234static int
    235mv88e6060_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
    236{
    237	struct mv88e6060_priv *priv = ds->priv;
    238	int addr;
    239
    240	addr = mv88e6060_port_to_phy_addr(port);
    241	if (addr == -1)
    242		return 0xffff;
    243
    244	return reg_write(priv, addr, regnum, val);
    245}
    246
    247static const struct dsa_switch_ops mv88e6060_switch_ops = {
    248	.get_tag_protocol = mv88e6060_get_tag_protocol,
    249	.setup		= mv88e6060_setup,
    250	.phy_read	= mv88e6060_phy_read,
    251	.phy_write	= mv88e6060_phy_write,
    252};
    253
    254static int mv88e6060_probe(struct mdio_device *mdiodev)
    255{
    256	struct device *dev = &mdiodev->dev;
    257	struct mv88e6060_priv *priv;
    258	struct dsa_switch *ds;
    259	const char *name;
    260
    261	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
    262	if (!priv)
    263		return -ENOMEM;
    264
    265	priv->bus = mdiodev->bus;
    266	priv->sw_addr = mdiodev->addr;
    267
    268	name = mv88e6060_get_name(priv->bus, priv->sw_addr);
    269	if (!name)
    270		return -ENODEV;
    271
    272	dev_info(dev, "switch %s detected\n", name);
    273
    274	ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
    275	if (!ds)
    276		return -ENOMEM;
    277
    278	ds->dev = dev;
    279	ds->num_ports = MV88E6060_PORTS;
    280	ds->priv = priv;
    281	ds->dev = dev;
    282	ds->ops = &mv88e6060_switch_ops;
    283
    284	dev_set_drvdata(dev, ds);
    285
    286	return dsa_register_switch(ds);
    287}
    288
    289static void mv88e6060_remove(struct mdio_device *mdiodev)
    290{
    291	struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
    292
    293	if (!ds)
    294		return;
    295
    296	dsa_unregister_switch(ds);
    297
    298	dev_set_drvdata(&mdiodev->dev, NULL);
    299}
    300
    301static void mv88e6060_shutdown(struct mdio_device *mdiodev)
    302{
    303	struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
    304
    305	if (!ds)
    306		return;
    307
    308	dsa_switch_shutdown(ds);
    309
    310	dev_set_drvdata(&mdiodev->dev, NULL);
    311}
    312
    313static const struct of_device_id mv88e6060_of_match[] = {
    314	{
    315		.compatible = "marvell,mv88e6060",
    316	},
    317	{ /* sentinel */ },
    318};
    319
    320static struct mdio_driver mv88e6060_driver = {
    321	.probe	= mv88e6060_probe,
    322	.remove = mv88e6060_remove,
    323	.shutdown = mv88e6060_shutdown,
    324	.mdiodrv.driver = {
    325		.name = "mv88e6060",
    326		.of_match_table = mv88e6060_of_match,
    327	},
    328};
    329
    330mdio_module_driver(mv88e6060_driver);
    331
    332MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
    333MODULE_DESCRIPTION("Driver for Marvell 88E6060 ethernet switch chip");
    334MODULE_LICENSE("GPL");
    335MODULE_ALIAS("platform:mv88e6060");