port.h (20871B)
1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * Marvell 88E6xxx Switch Port Registers support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 8 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 9 */ 10 11#ifndef _MV88E6XXX_PORT_H 12#define _MV88E6XXX_PORT_H 13 14#include "chip.h" 15 16/* Offset 0x00: Port Status Register */ 17#define MV88E6XXX_PORT_STS 0x00 18#define MV88E6XXX_PORT_STS_PAUSE_EN 0x8000 19#define MV88E6XXX_PORT_STS_MY_PAUSE 0x4000 20#define MV88E6XXX_PORT_STS_HD_FLOW 0x2000 21#define MV88E6XXX_PORT_STS_PHY_DETECT 0x1000 22#define MV88E6250_PORT_STS_LINK 0x1000 23#define MV88E6250_PORT_STS_PORTMODE_MASK 0x0f00 24#define MV88E6250_PORT_STS_PORTMODE_PHY_10_HALF 0x0800 25#define MV88E6250_PORT_STS_PORTMODE_PHY_100_HALF 0x0900 26#define MV88E6250_PORT_STS_PORTMODE_PHY_10_FULL 0x0a00 27#define MV88E6250_PORT_STS_PORTMODE_PHY_100_FULL 0x0b00 28#define MV88E6250_PORT_STS_PORTMODE_MII_10_HALF 0x0c00 29#define MV88E6250_PORT_STS_PORTMODE_MII_100_HALF 0x0d00 30#define MV88E6250_PORT_STS_PORTMODE_MII_10_FULL 0x0e00 31#define MV88E6250_PORT_STS_PORTMODE_MII_100_FULL 0x0f00 32#define MV88E6XXX_PORT_STS_LINK 0x0800 33#define MV88E6XXX_PORT_STS_DUPLEX 0x0400 34#define MV88E6XXX_PORT_STS_SPEED_MASK 0x0300 35#define MV88E6XXX_PORT_STS_SPEED_10 0x0000 36#define MV88E6XXX_PORT_STS_SPEED_100 0x0100 37#define MV88E6XXX_PORT_STS_SPEED_1000 0x0200 38#define MV88E6XXX_PORT_STS_SPEED_10000 0x0300 39#define MV88E6352_PORT_STS_EEE 0x0040 40#define MV88E6165_PORT_STS_AM_DIS 0x0040 41#define MV88E6185_PORT_STS_MGMII 0x0040 42#define MV88E6XXX_PORT_STS_TX_PAUSED 0x0020 43#define MV88E6XXX_PORT_STS_FLOW_CTL 0x0010 44#define MV88E6XXX_PORT_STS_CMODE_MASK 0x000f 45#define MV88E6XXX_PORT_STS_CMODE_MII_PHY 0x0001 46#define MV88E6XXX_PORT_STS_CMODE_MII 0x0002 47#define MV88E6XXX_PORT_STS_CMODE_GMII 0x0003 48#define MV88E6XXX_PORT_STS_CMODE_RMII_PHY 0x0004 49#define MV88E6XXX_PORT_STS_CMODE_RMII 0x0005 50#define MV88E6XXX_PORT_STS_CMODE_RGMII 0x0007 51#define MV88E6XXX_PORT_STS_CMODE_100BASEX 0x0008 52#define MV88E6XXX_PORT_STS_CMODE_1000BASEX 0x0009 53#define MV88E6XXX_PORT_STS_CMODE_SGMII 0x000a 54#define MV88E6XXX_PORT_STS_CMODE_2500BASEX 0x000b 55#define MV88E6XXX_PORT_STS_CMODE_XAUI 0x000c 56#define MV88E6XXX_PORT_STS_CMODE_RXAUI 0x000d 57#define MV88E6393X_PORT_STS_CMODE_5GBASER 0x000c 58#define MV88E6393X_PORT_STS_CMODE_10GBASER 0x000d 59#define MV88E6393X_PORT_STS_CMODE_USXGMII 0x000e 60#define MV88E6185_PORT_STS_CDUPLEX 0x0008 61#define MV88E6185_PORT_STS_CMODE_MASK 0x0007 62#define MV88E6185_PORT_STS_CMODE_GMII_FD 0x0000 63#define MV88E6185_PORT_STS_CMODE_MII_100_FD_PS 0x0001 64#define MV88E6185_PORT_STS_CMODE_MII_100 0x0002 65#define MV88E6185_PORT_STS_CMODE_MII_10 0x0003 66#define MV88E6185_PORT_STS_CMODE_SERDES 0x0004 67#define MV88E6185_PORT_STS_CMODE_1000BASE_X 0x0005 68#define MV88E6185_PORT_STS_CMODE_PHY 0x0006 69#define MV88E6185_PORT_STS_CMODE_DISABLED 0x0007 70 71/* Offset 0x01: MAC (or PCS or Physical) Control Register */ 72#define MV88E6XXX_PORT_MAC_CTL 0x01 73#define MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK 0x8000 74#define MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK 0x4000 75#define MV88E6185_PORT_MAC_CTL_SYNC_OK 0x4000 76#define MV88E6390_PORT_MAC_CTL_FORCE_SPEED 0x2000 77#define MV88E6390_PORT_MAC_CTL_ALTSPEED 0x1000 78#define MV88E6352_PORT_MAC_CTL_200BASE 0x1000 79#define MV88E6XXX_PORT_MAC_CTL_EEE 0x0200 80#define MV88E6XXX_PORT_MAC_CTL_FORCE_EEE 0x0100 81#define MV88E6185_PORT_MAC_CTL_AN_EN 0x0400 82#define MV88E6185_PORT_MAC_CTL_AN_RESTART 0x0200 83#define MV88E6185_PORT_MAC_CTL_AN_DONE 0x0100 84#define MV88E6XXX_PORT_MAC_CTL_FC 0x0080 85#define MV88E6XXX_PORT_MAC_CTL_FORCE_FC 0x0040 86#define MV88E6XXX_PORT_MAC_CTL_LINK_UP 0x0020 87#define MV88E6XXX_PORT_MAC_CTL_FORCE_LINK 0x0010 88#define MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL 0x0008 89#define MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX 0x0004 90#define MV88E6XXX_PORT_MAC_CTL_SPEED_MASK 0x0003 91#define MV88E6XXX_PORT_MAC_CTL_SPEED_10 0x0000 92#define MV88E6XXX_PORT_MAC_CTL_SPEED_100 0x0001 93#define MV88E6065_PORT_MAC_CTL_SPEED_200 0x0002 94#define MV88E6XXX_PORT_MAC_CTL_SPEED_1000 0x0002 95#define MV88E6390_PORT_MAC_CTL_SPEED_10000 0x0003 96#define MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED 0x0003 97 98/* Offset 0x02: Jamming Control Register */ 99#define MV88E6097_PORT_JAM_CTL 0x02 100#define MV88E6097_PORT_JAM_CTL_LIMIT_OUT_MASK 0xff00 101#define MV88E6097_PORT_JAM_CTL_LIMIT_IN_MASK 0x00ff 102 103/* Offset 0x02: Flow Control Register */ 104#define MV88E6390_PORT_FLOW_CTL 0x02 105#define MV88E6390_PORT_FLOW_CTL_UPDATE 0x8000 106#define MV88E6390_PORT_FLOW_CTL_PTR_MASK 0x7f00 107#define MV88E6390_PORT_FLOW_CTL_LIMIT_IN 0x0000 108#define MV88E6390_PORT_FLOW_CTL_LIMIT_OUT 0x0100 109#define MV88E6390_PORT_FLOW_CTL_DATA_MASK 0x00ff 110 111/* Offset 0x03: Switch Identifier Register */ 112#define MV88E6XXX_PORT_SWITCH_ID 0x03 113#define MV88E6XXX_PORT_SWITCH_ID_PROD_MASK 0xfff0 114#define MV88E6XXX_PORT_SWITCH_ID_PROD_6085 0x04a0 115#define MV88E6XXX_PORT_SWITCH_ID_PROD_6095 0x0950 116#define MV88E6XXX_PORT_SWITCH_ID_PROD_6097 0x0990 117#define MV88E6XXX_PORT_SWITCH_ID_PROD_6190X 0x0a00 118#define MV88E6XXX_PORT_SWITCH_ID_PROD_6390X 0x0a10 119#define MV88E6XXX_PORT_SWITCH_ID_PROD_6131 0x1060 120#define MV88E6XXX_PORT_SWITCH_ID_PROD_6320 0x1150 121#define MV88E6XXX_PORT_SWITCH_ID_PROD_6123 0x1210 122#define MV88E6XXX_PORT_SWITCH_ID_PROD_6161 0x1610 123#define MV88E6XXX_PORT_SWITCH_ID_PROD_6165 0x1650 124#define MV88E6XXX_PORT_SWITCH_ID_PROD_6171 0x1710 125#define MV88E6XXX_PORT_SWITCH_ID_PROD_6172 0x1720 126#define MV88E6XXX_PORT_SWITCH_ID_PROD_6175 0x1750 127#define MV88E6XXX_PORT_SWITCH_ID_PROD_6176 0x1760 128#define MV88E6XXX_PORT_SWITCH_ID_PROD_6190 0x1900 129#define MV88E6XXX_PORT_SWITCH_ID_PROD_6191 0x1910 130#define MV88E6XXX_PORT_SWITCH_ID_PROD_6191X 0x1920 131#define MV88E6XXX_PORT_SWITCH_ID_PROD_6193X 0x1930 132#define MV88E6XXX_PORT_SWITCH_ID_PROD_6185 0x1a70 133#define MV88E6XXX_PORT_SWITCH_ID_PROD_6220 0x2200 134#define MV88E6XXX_PORT_SWITCH_ID_PROD_6240 0x2400 135#define MV88E6XXX_PORT_SWITCH_ID_PROD_6250 0x2500 136#define MV88E6XXX_PORT_SWITCH_ID_PROD_6290 0x2900 137#define MV88E6XXX_PORT_SWITCH_ID_PROD_6321 0x3100 138#define MV88E6XXX_PORT_SWITCH_ID_PROD_6141 0x3400 139#define MV88E6XXX_PORT_SWITCH_ID_PROD_6341 0x3410 140#define MV88E6XXX_PORT_SWITCH_ID_PROD_6352 0x3520 141#define MV88E6XXX_PORT_SWITCH_ID_PROD_6350 0x3710 142#define MV88E6XXX_PORT_SWITCH_ID_PROD_6351 0x3750 143#define MV88E6XXX_PORT_SWITCH_ID_PROD_6390 0x3900 144#define MV88E6XXX_PORT_SWITCH_ID_PROD_6393X 0x3930 145#define MV88E6XXX_PORT_SWITCH_ID_REV_MASK 0x000f 146 147/* Offset 0x04: Port Control Register */ 148#define MV88E6XXX_PORT_CTL0 0x04 149#define MV88E6XXX_PORT_CTL0_USE_CORE_TAG 0x8000 150#define MV88E6XXX_PORT_CTL0_SA_FILT_MASK 0xc000 151#define MV88E6XXX_PORT_CTL0_SA_FILT_DISABLED 0x0000 152#define MV88E6XXX_PORT_CTL0_SA_FILT_DROP_ON_LOCK 0x4000 153#define MV88E6XXX_PORT_CTL0_SA_FILT_DROP_ON_UNLOCK 0x8000 154#define MV88E6XXX_PORT_CTL0_SA_FILT_DROP_ON_CPU 0xc000 155#define MV88E6XXX_PORT_CTL0_EGRESS_MODE_MASK 0x3000 156#define MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNMODIFIED 0x0000 157#define MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNTAGGED 0x1000 158#define MV88E6XXX_PORT_CTL0_EGRESS_MODE_TAGGED 0x2000 159#define MV88E6XXX_PORT_CTL0_EGRESS_MODE_ETHER_TYPE_DSA 0x3000 160#define MV88E6XXX_PORT_CTL0_HEADER 0x0800 161#define MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP 0x0400 162#define MV88E6XXX_PORT_CTL0_DOUBLE_TAG 0x0200 163#define MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK 0x0300 164#define MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL 0x0000 165#define MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA 0x0100 166#define MV88E6XXX_PORT_CTL0_FRAME_MODE_PROVIDER 0x0200 167#define MV88E6XXX_PORT_CTL0_FRAME_MODE_ETHER_TYPE_DSA 0x0300 168#define MV88E6XXX_PORT_CTL0_DSA_TAG 0x0100 169#define MV88E6XXX_PORT_CTL0_VLAN_TUNNEL 0x0080 170#define MV88E6XXX_PORT_CTL0_TAG_IF_BOTH 0x0040 171#define MV88E6185_PORT_CTL0_USE_IP 0x0020 172#define MV88E6185_PORT_CTL0_USE_TAG 0x0010 173#define MV88E6185_PORT_CTL0_FORWARD_UNKNOWN 0x0004 174#define MV88E6352_PORT_CTL0_EGRESS_FLOODS_UC 0x0004 175#define MV88E6352_PORT_CTL0_EGRESS_FLOODS_MC 0x0008 176#define MV88E6XXX_PORT_CTL0_STATE_MASK 0x0003 177#define MV88E6XXX_PORT_CTL0_STATE_DISABLED 0x0000 178#define MV88E6XXX_PORT_CTL0_STATE_BLOCKING 0x0001 179#define MV88E6XXX_PORT_CTL0_STATE_LEARNING 0x0002 180#define MV88E6XXX_PORT_CTL0_STATE_FORWARDING 0x0003 181 182/* Offset 0x05: Port Control 1 */ 183#define MV88E6XXX_PORT_CTL1 0x05 184#define MV88E6XXX_PORT_CTL1_MESSAGE_PORT 0x8000 185#define MV88E6XXX_PORT_CTL1_TRUNK_PORT 0x4000 186#define MV88E6XXX_PORT_CTL1_TRUNK_ID_MASK 0x0f00 187#define MV88E6XXX_PORT_CTL1_TRUNK_ID_SHIFT 8 188#define MV88E6XXX_PORT_CTL1_FID_11_4_MASK 0x00ff 189 190/* Offset 0x06: Port Based VLAN Map */ 191#define MV88E6XXX_PORT_BASE_VLAN 0x06 192#define MV88E6XXX_PORT_BASE_VLAN_FID_3_0_MASK 0xf000 193 194/* Offset 0x07: Default Port VLAN ID & Priority */ 195#define MV88E6XXX_PORT_DEFAULT_VLAN 0x07 196#define MV88E6XXX_PORT_DEFAULT_VLAN_MASK 0x0fff 197 198/* Offset 0x08: Port Control 2 Register */ 199#define MV88E6XXX_PORT_CTL2 0x08 200#define MV88E6XXX_PORT_CTL2_IGNORE_FCS 0x8000 201#define MV88E6XXX_PORT_CTL2_VTU_PRI_OVERRIDE 0x4000 202#define MV88E6XXX_PORT_CTL2_SA_PRIO_OVERRIDE 0x2000 203#define MV88E6XXX_PORT_CTL2_DA_PRIO_OVERRIDE 0x1000 204#define MV88E6XXX_PORT_CTL2_JUMBO_MODE_MASK 0x3000 205#define MV88E6XXX_PORT_CTL2_JUMBO_MODE_1522 0x0000 206#define MV88E6XXX_PORT_CTL2_JUMBO_MODE_2048 0x1000 207#define MV88E6XXX_PORT_CTL2_JUMBO_MODE_10240 0x2000 208#define MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK 0x0c00 209#define MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED 0x0000 210#define MV88E6XXX_PORT_CTL2_8021Q_MODE_FALLBACK 0x0400 211#define MV88E6XXX_PORT_CTL2_8021Q_MODE_CHECK 0x0800 212#define MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE 0x0c00 213#define MV88E6XXX_PORT_CTL2_DISCARD_TAGGED 0x0200 214#define MV88E6XXX_PORT_CTL2_DISCARD_UNTAGGED 0x0100 215#define MV88E6XXX_PORT_CTL2_MAP_DA 0x0080 216#define MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD 0x0040 217#define MV88E6XXX_PORT_CTL2_EGRESS_MONITOR 0x0020 218#define MV88E6XXX_PORT_CTL2_INGRESS_MONITOR 0x0010 219#define MV88E6095_PORT_CTL2_CPU_PORT_MASK 0x000f 220 221/* Offset 0x09: Egress Rate Control */ 222#define MV88E6XXX_PORT_EGRESS_RATE_CTL1 0x09 223 224/* Offset 0x0A: Egress Rate Control 2 */ 225#define MV88E6XXX_PORT_EGRESS_RATE_CTL2 0x0a 226 227/* Offset 0x0B: Port Association Vector */ 228#define MV88E6XXX_PORT_ASSOC_VECTOR 0x0b 229#define MV88E6XXX_PORT_ASSOC_VECTOR_HOLD_AT_1 0x8000 230#define MV88E6XXX_PORT_ASSOC_VECTOR_INT_AGE_OUT 0x4000 231#define MV88E6XXX_PORT_ASSOC_VECTOR_LOCKED_PORT 0x2000 232#define MV88E6XXX_PORT_ASSOC_VECTOR_IGNORE_WRONG 0x1000 233#define MV88E6XXX_PORT_ASSOC_VECTOR_REFRESH_LOCKED 0x0800 234 235/* Offset 0x0C: Port ATU Control */ 236#define MV88E6XXX_PORT_ATU_CTL 0x0c 237 238/* Offset 0x0D: Priority Override Register */ 239#define MV88E6XXX_PORT_PRI_OVERRIDE 0x0d 240 241/* Offset 0x0E: Policy Control Register */ 242#define MV88E6XXX_PORT_POLICY_CTL 0x0e 243#define MV88E6XXX_PORT_POLICY_CTL_DA_MASK 0xc000 244#define MV88E6XXX_PORT_POLICY_CTL_SA_MASK 0x3000 245#define MV88E6XXX_PORT_POLICY_CTL_VTU_MASK 0x0c00 246#define MV88E6XXX_PORT_POLICY_CTL_ETYPE_MASK 0x0300 247#define MV88E6XXX_PORT_POLICY_CTL_PPPOE_MASK 0x00c0 248#define MV88E6XXX_PORT_POLICY_CTL_VBAS_MASK 0x0030 249#define MV88E6XXX_PORT_POLICY_CTL_OPT82_MASK 0x000c 250#define MV88E6XXX_PORT_POLICY_CTL_UDP_MASK 0x0003 251#define MV88E6XXX_PORT_POLICY_CTL_NORMAL 0x0000 252#define MV88E6XXX_PORT_POLICY_CTL_MIRROR 0x0001 253#define MV88E6XXX_PORT_POLICY_CTL_TRAP 0x0002 254#define MV88E6XXX_PORT_POLICY_CTL_DISCARD 0x0003 255 256/* Offset 0x0E: Policy & MGMT Control Register (FAMILY_6393X) */ 257#define MV88E6393X_PORT_POLICY_MGMT_CTL 0x0e 258#define MV88E6393X_PORT_POLICY_MGMT_CTL_UPDATE 0x8000 259#define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_MASK 0x3f00 260#define MV88E6393X_PORT_POLICY_MGMT_CTL_DATA_MASK 0x00ff 261#define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000000XLO 0x2000 262#define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000000XHI 0x2100 263#define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000002XLO 0x2400 264#define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000002XHI 0x2500 265#define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_INGRESS_DEST 0x3000 266#define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_CPU_DEST 0x3800 267#define MV88E6393X_PORT_POLICY_MGMT_CTL_CPU_DEST_MGMTPRI 0x00e0 268 269/* Offset 0x0F: Port Special Ether Type */ 270#define MV88E6XXX_PORT_ETH_TYPE 0x0f 271#define MV88E6XXX_PORT_ETH_TYPE_DEFAULT 0x9100 272 273/* Offset 0x10: InDiscards Low Counter */ 274#define MV88E6XXX_PORT_IN_DISCARD_LO 0x10 275 276/* Offset 0x10: Extended Port Control Command */ 277#define MV88E6393X_PORT_EPC_CMD 0x10 278#define MV88E6393X_PORT_EPC_CMD_BUSY 0x8000 279#define MV88E6393X_PORT_EPC_CMD_WRITE 0x0300 280#define MV88E6393X_PORT_EPC_INDEX_PORT_ETYPE 0x02 281 282/* Offset 0x11: Extended Port Control Data */ 283#define MV88E6393X_PORT_EPC_DATA 0x11 284 285/* Offset 0x11: InDiscards High Counter */ 286#define MV88E6XXX_PORT_IN_DISCARD_HI 0x11 287 288/* Offset 0x12: InFiltered Counter */ 289#define MV88E6XXX_PORT_IN_FILTERED 0x12 290 291/* Offset 0x13: OutFiltered Counter */ 292#define MV88E6XXX_PORT_OUT_FILTERED 0x13 293 294/* Offset 0x18: IEEE Priority Mapping Table */ 295#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE 0x18 296#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_UPDATE 0x8000 297#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_MASK 0x7000 298#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP 0x0000 299#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP 0x1000 300#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP 0x2000 301#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP 0x3000 302#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_DSCP 0x5000 303#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_DSCP 0x6000 304#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_DSCP 0x7000 305#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_PTR_MASK 0x0e00 306#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_DATA_MASK 0x01ff 307 308/* Offset 0x18: Port IEEE Priority Remapping Registers (0-3) */ 309#define MV88E6095_PORT_IEEE_PRIO_REMAP_0123 0x18 310 311/* Offset 0x19: Port IEEE Priority Remapping Registers (4-7) */ 312#define MV88E6095_PORT_IEEE_PRIO_REMAP_4567 0x19 313 314/* Offset 0x1a: Magic undocumented errata register */ 315#define MV88E6XXX_PORT_RESERVED_1A 0x1a 316#define MV88E6XXX_PORT_RESERVED_1A_BUSY 0x8000 317#define MV88E6XXX_PORT_RESERVED_1A_WRITE 0x4000 318#define MV88E6XXX_PORT_RESERVED_1A_READ 0x0000 319#define MV88E6XXX_PORT_RESERVED_1A_PORT_SHIFT 5 320#define MV88E6XXX_PORT_RESERVED_1A_BLOCK_SHIFT 10 321#define MV88E6XXX_PORT_RESERVED_1A_CTRL_PORT 0x04 322#define MV88E6XXX_PORT_RESERVED_1A_DATA_PORT 0x05 323#define MV88E6341_PORT_RESERVED_1A_FORCE_CMODE 0x8000 324#define MV88E6341_PORT_RESERVED_1A_SGMII_AN 0x2000 325 326int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg, 327 u16 *val); 328int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg, 329 u16 val); 330int mv88e6xxx_port_wait_bit(struct mv88e6xxx_chip *chip, int port, int reg, 331 int bit, int val); 332 333int mv88e6185_port_set_pause(struct mv88e6xxx_chip *chip, int port, 334 int pause); 335int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 336 phy_interface_t mode); 337int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 338 phy_interface_t mode); 339 340int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link); 341 342int mv88e6xxx_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup); 343int mv88e6185_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup); 344 345int mv88e6065_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 346 int speed, int duplex); 347int mv88e6185_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 348 int speed, int duplex); 349int mv88e6250_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 350 int speed, int duplex); 351int mv88e6341_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 352 int speed, int duplex); 353int mv88e6352_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 354 int speed, int duplex); 355int mv88e6390_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 356 int speed, int duplex); 357int mv88e6390x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 358 int speed, int duplex); 359int mv88e6393x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 360 int speed, int duplex); 361 362phy_interface_t mv88e6341_port_max_speed_mode(int port); 363phy_interface_t mv88e6390_port_max_speed_mode(int port); 364phy_interface_t mv88e6390x_port_max_speed_mode(int port); 365phy_interface_t mv88e6393x_port_max_speed_mode(int port); 366 367int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state); 368 369int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map); 370 371int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid); 372int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid); 373 374int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid); 375int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid); 376 377int mv88e6xxx_port_set_lock(struct mv88e6xxx_chip *chip, int port, 378 bool locked); 379 380int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port, 381 u16 mode); 382int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port); 383int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port); 384int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port, 385 enum mv88e6xxx_egress_mode mode); 386int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, 387 enum mv88e6xxx_frame_mode mode); 388int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, 389 enum mv88e6xxx_frame_mode mode); 390int mv88e6185_port_set_forward_unknown(struct mv88e6xxx_chip *chip, 391 int port, bool unicast); 392int mv88e6185_port_set_default_forward(struct mv88e6xxx_chip *chip, 393 int port, bool multicast); 394int mv88e6352_port_set_ucast_flood(struct mv88e6xxx_chip *chip, int port, 395 bool unicast); 396int mv88e6352_port_set_mcast_flood(struct mv88e6xxx_chip *chip, int port, 397 bool multicast); 398int mv88e6352_port_set_policy(struct mv88e6xxx_chip *chip, int port, 399 enum mv88e6xxx_policy_mapping mapping, 400 enum mv88e6xxx_policy_action action); 401int mv88e6393x_port_set_policy(struct mv88e6xxx_chip *chip, int port, 402 enum mv88e6xxx_policy_mapping mapping, 403 enum mv88e6xxx_policy_action action); 404int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port, 405 u16 etype); 406int mv88e6393x_set_egress_port(struct mv88e6xxx_chip *chip, 407 enum mv88e6xxx_egress_direction direction, 408 int port); 409int mv88e6393x_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port, 410 int upstream_port); 411int mv88e6393x_port_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip); 412int mv88e6393x_port_set_ether_type(struct mv88e6xxx_chip *chip, int port, 413 u16 etype); 414int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port, 415 bool message_port); 416int mv88e6xxx_port_set_trunk(struct mv88e6xxx_chip *chip, int port, 417 bool trunk, u8 id); 418int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port, 419 size_t size); 420int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port); 421int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port); 422int mv88e6xxx_port_set_assoc_vector(struct mv88e6xxx_chip *chip, int port, 423 u16 pav); 424int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, 425 u8 out); 426int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, 427 u8 out); 428int mv88e6341_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 429 phy_interface_t mode); 430int mv88e6390_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 431 phy_interface_t mode); 432int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 433 phy_interface_t mode); 434int mv88e6393x_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 435 phy_interface_t mode); 436int mv88e6185_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode); 437int mv88e6352_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode); 438int mv88e6xxx_port_drop_untagged(struct mv88e6xxx_chip *chip, int port, 439 bool drop_untagged); 440int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port, bool map); 441int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port, 442 int upstream_port); 443int mv88e6xxx_port_set_mirror(struct mv88e6xxx_chip *chip, int port, 444 enum mv88e6xxx_egress_direction direction, 445 bool mirror); 446 447int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port); 448int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port); 449 450int mv88e6xxx_port_hidden_write(struct mv88e6xxx_chip *chip, int block, 451 int port, int reg, u16 val); 452int mv88e6xxx_port_hidden_wait(struct mv88e6xxx_chip *chip); 453int mv88e6xxx_port_hidden_read(struct mv88e6xxx_chip *chip, int block, int port, 454 int reg, u16 *val); 455 456#endif /* _MV88E6XXX_PORT_H */