cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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sun4i-emac.h (4752B)

      1/*
      2 * Allwinner EMAC Fast Ethernet driver for Linux.
      3 *
      4 * Copyright 2012 Stefan Roese <sr@denx.de>
      5 * Copyright 2013 Maxime Ripard <maxime.ripard@free-electrons.com>
      6 *
      7 * Based on the Linux driver provided by Allwinner:
      8 * Copyright (C) 1997  Sten Wang
      9 *
     10 * This file is licensed under the terms of the GNU General Public
     11 * License version 2. This program is licensed "as is" without any
     12 * warranty of any kind, whether express or implied.
     13 */
     14
     15#ifndef _SUN4I_EMAC_H_
     16#define _SUN4I_EMAC_H_
     17
     18#define EMAC_CTL_REG		(0x00)
     19#define EMAC_CTL_RESET			(1 << 0)
     20#define EMAC_CTL_TX_EN			(1 << 1)
     21#define EMAC_CTL_RX_EN			(1 << 2)
     22#define EMAC_TX_MODE_REG	(0x04)
     23#define EMAC_TX_MODE_ABORTED_FRAME_EN	(1 << 0)
     24#define EMAC_TX_MODE_DMA_EN		(1 << 1)
     25#define EMAC_TX_FLOW_REG	(0x08)
     26#define EMAC_TX_CTL0_REG	(0x0c)
     27#define EMAC_TX_CTL1_REG	(0x10)
     28#define EMAC_TX_INS_REG		(0x14)
     29#define EMAC_TX_PL0_REG		(0x18)
     30#define EMAC_TX_PL1_REG		(0x1c)
     31#define EMAC_TX_STA_REG		(0x20)
     32#define EMAC_TX_IO_DATA_REG	(0x24)
     33#define EMAC_TX_IO_DATA1_REG	(0x28)
     34#define EMAC_TX_TSVL0_REG	(0x2c)
     35#define EMAC_TX_TSVH0_REG	(0x30)
     36#define EMAC_TX_TSVL1_REG	(0x34)
     37#define EMAC_TX_TSVH1_REG	(0x38)
     38#define EMAC_RX_CTL_REG		(0x3c)
     39#define EMAC_RX_CTL_AUTO_DRQ_EN		(1 << 1)
     40#define EMAC_RX_CTL_DMA_EN		(1 << 2)
     41#define EMAC_RX_CTL_FLUSH_FIFO		(1 << 3)
     42#define EMAC_RX_CTL_PASS_ALL_EN		(1 << 4)
     43#define EMAC_RX_CTL_PASS_CTL_EN		(1 << 5)
     44#define EMAC_RX_CTL_PASS_CRC_ERR_EN	(1 << 6)
     45#define EMAC_RX_CTL_PASS_LEN_ERR_EN	(1 << 7)
     46#define EMAC_RX_CTL_PASS_LEN_OOR_EN	(1 << 8)
     47#define EMAC_RX_CTL_ACCEPT_UNICAST_EN	(1 << 16)
     48#define EMAC_RX_CTL_DA_FILTER_EN	(1 << 17)
     49#define EMAC_RX_CTL_ACCEPT_MULTICAST_EN	(1 << 20)
     50#define EMAC_RX_CTL_HASH_FILTER_EN	(1 << 21)
     51#define EMAC_RX_CTL_ACCEPT_BROADCAST_EN	(1 << 22)
     52#define EMAC_RX_CTL_SA_FILTER_EN	(1 << 24)
     53#define EMAC_RX_CTL_SA_FILTER_INVERT_EN	(1 << 25)
     54#define EMAC_RX_HASH0_REG	(0x40)
     55#define EMAC_RX_HASH1_REG	(0x44)
     56#define EMAC_RX_STA_REG		(0x48)
     57#define EMAC_RX_IO_DATA_REG	(0x4c)
     58#define EMAC_RX_IO_DATA_LEN(x)		(x & 0xffff)
     59#define EMAC_RX_IO_DATA_STATUS(x)	((x >> 16) & 0xffff)
     60#define EMAC_RX_IO_DATA_STATUS_CRC_ERR	(1 << 4)
     61#define EMAC_RX_IO_DATA_STATUS_LEN_ERR	(3 << 5)
     62#define EMAC_RX_IO_DATA_STATUS_OK	(1 << 7)
     63#define EMAC_RX_FBC_REG		(0x50)
     64#define EMAC_INT_CTL_REG	(0x54)
     65#define EMAC_INT_CTL_RX_EN	(1 << 8)
     66#define EMAC_INT_CTL_TX0_EN	(1)
     67#define EMAC_INT_CTL_TX1_EN	(1 << 1)
     68#define EMAC_INT_CTL_TX_EN	(EMAC_INT_CTL_TX0_EN | EMAC_INT_CTL_TX1_EN)
     69#define EMAC_INT_CTL_TX0_ABRT_EN	(0x1 << 2)
     70#define EMAC_INT_CTL_TX1_ABRT_EN	(0x1 << 3)
     71#define EMAC_INT_CTL_TX_ABRT_EN	(EMAC_INT_CTL_TX0_ABRT_EN | EMAC_INT_CTL_TX1_ABRT_EN)
     72#define EMAC_INT_STA_REG	(0x58)
     73#define EMAC_INT_STA_TX0_COMPLETE	(0x1)
     74#define EMAC_INT_STA_TX1_COMPLETE	(0x1 << 1)
     75#define EMAC_INT_STA_TX_COMPLETE	(EMAC_INT_STA_TX0_COMPLETE | EMAC_INT_STA_TX1_COMPLETE)
     76#define EMAC_INT_STA_TX0_ABRT	(0x1 << 2)
     77#define EMAC_INT_STA_TX1_ABRT	(0x1 << 3)
     78#define EMAC_INT_STA_TX_ABRT	(EMAC_INT_STA_TX0_ABRT | EMAC_INT_STA_TX1_ABRT)
     79#define EMAC_INT_STA_RX_COMPLETE	(0x1 << 8)
     80#define EMAC_MAC_CTL0_REG	(0x5c)
     81#define EMAC_MAC_CTL0_RX_FLOW_CTL_EN	(1 << 2)
     82#define EMAC_MAC_CTL0_TX_FLOW_CTL_EN	(1 << 3)
     83#define EMAC_MAC_CTL0_SOFT_RESET	(1 << 15)
     84#define EMAC_MAC_CTL1_REG	(0x60)
     85#define EMAC_MAC_CTL1_DUPLEX_EN		(1 << 0)
     86#define EMAC_MAC_CTL1_LEN_CHECK_EN	(1 << 1)
     87#define EMAC_MAC_CTL1_HUGE_FRAME_EN	(1 << 2)
     88#define EMAC_MAC_CTL1_DELAYED_CRC_EN	(1 << 3)
     89#define EMAC_MAC_CTL1_CRC_EN		(1 << 4)
     90#define EMAC_MAC_CTL1_PAD_EN		(1 << 5)
     91#define EMAC_MAC_CTL1_PAD_CRC_EN	(1 << 6)
     92#define EMAC_MAC_CTL1_AD_SHORT_FRAME_EN	(1 << 7)
     93#define EMAC_MAC_CTL1_BACKOFF_DIS	(1 << 12)
     94#define EMAC_MAC_IPGT_REG	(0x64)
     95#define EMAC_MAC_IPGT_HALF_DUPLEX	(0x12)
     96#define EMAC_MAC_IPGT_FULL_DUPLEX	(0x15)
     97#define EMAC_MAC_IPGR_REG	(0x68)
     98#define EMAC_MAC_IPGR_IPG1		(0x0c)
     99#define EMAC_MAC_IPGR_IPG2		(0x12)
    100#define EMAC_MAC_CLRT_REG	(0x6c)
    101#define EMAC_MAC_CLRT_COLLISION_WINDOW	(0x37)
    102#define EMAC_MAC_CLRT_RM		(0x0f)
    103#define EMAC_MAC_MAXF_REG	(0x70)
    104#define EMAC_MAC_SUPP_REG	(0x74)
    105#define EMAC_MAC_SUPP_100M	(0x1 << 8)
    106#define EMAC_MAC_TEST_REG	(0x78)
    107#define EMAC_MAC_MCFG_REG	(0x7c)
    108#define EMAC_MAC_MCFG_MII_CLKD_MASK	(0xff << 2)
    109#define EMAC_MAC_MCFG_MII_CLKD_72	(0x0d << 2)
    110#define EMAC_MAC_A0_REG		(0x98)
    111#define EMAC_MAC_A1_REG		(0x9c)
    112#define EMAC_MAC_A2_REG		(0xa0)
    113#define EMAC_SAFX_L_REG0	(0xa4)
    114#define EMAC_SAFX_H_REG0	(0xa8)
    115#define EMAC_SAFX_L_REG1	(0xac)
    116#define EMAC_SAFX_H_REG1	(0xb0)
    117#define EMAC_SAFX_L_REG2	(0xb4)
    118#define EMAC_SAFX_H_REG2	(0xb8)
    119#define EMAC_SAFX_L_REG3	(0xbc)
    120#define EMAC_SAFX_H_REG3	(0xc0)
    121
    122#define EMAC_PHY_DUPLEX		(1 << 8)
    123
    124#define EMAC_EEPROM_MAGIC	(0x444d394b)
    125#define EMAC_UNDOCUMENTED_MAGIC	(0x0143414d)
    126#endif /* _SUN4I_EMAC_H_ */