ena_regs_defs.h (6510B)
1/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2/* 3 * Copyright 2015-2020 Amazon.com, Inc. or its affiliates. All rights reserved. 4 */ 5#ifndef _ENA_REGS_H_ 6#define _ENA_REGS_H_ 7 8enum ena_regs_reset_reason_types { 9 ENA_REGS_RESET_NORMAL = 0, 10 ENA_REGS_RESET_KEEP_ALIVE_TO = 1, 11 ENA_REGS_RESET_ADMIN_TO = 2, 12 ENA_REGS_RESET_MISS_TX_CMPL = 3, 13 ENA_REGS_RESET_INV_RX_REQ_ID = 4, 14 ENA_REGS_RESET_INV_TX_REQ_ID = 5, 15 ENA_REGS_RESET_TOO_MANY_RX_DESCS = 6, 16 ENA_REGS_RESET_INIT_ERR = 7, 17 ENA_REGS_RESET_DRIVER_INVALID_STATE = 8, 18 ENA_REGS_RESET_OS_TRIGGER = 9, 19 ENA_REGS_RESET_OS_NETDEV_WD = 10, 20 ENA_REGS_RESET_SHUTDOWN = 11, 21 ENA_REGS_RESET_USER_TRIGGER = 12, 22 ENA_REGS_RESET_GENERIC = 13, 23 ENA_REGS_RESET_MISS_INTERRUPT = 14, 24}; 25 26/* ena_registers offsets */ 27 28/* 0 base */ 29#define ENA_REGS_VERSION_OFF 0x0 30#define ENA_REGS_CONTROLLER_VERSION_OFF 0x4 31#define ENA_REGS_CAPS_OFF 0x8 32#define ENA_REGS_CAPS_EXT_OFF 0xc 33#define ENA_REGS_AQ_BASE_LO_OFF 0x10 34#define ENA_REGS_AQ_BASE_HI_OFF 0x14 35#define ENA_REGS_AQ_CAPS_OFF 0x18 36#define ENA_REGS_ACQ_BASE_LO_OFF 0x20 37#define ENA_REGS_ACQ_BASE_HI_OFF 0x24 38#define ENA_REGS_ACQ_CAPS_OFF 0x28 39#define ENA_REGS_AQ_DB_OFF 0x2c 40#define ENA_REGS_ACQ_TAIL_OFF 0x30 41#define ENA_REGS_AENQ_CAPS_OFF 0x34 42#define ENA_REGS_AENQ_BASE_LO_OFF 0x38 43#define ENA_REGS_AENQ_BASE_HI_OFF 0x3c 44#define ENA_REGS_AENQ_HEAD_DB_OFF 0x40 45#define ENA_REGS_AENQ_TAIL_OFF 0x44 46#define ENA_REGS_INTR_MASK_OFF 0x4c 47#define ENA_REGS_DEV_CTL_OFF 0x54 48#define ENA_REGS_DEV_STS_OFF 0x58 49#define ENA_REGS_MMIO_REG_READ_OFF 0x5c 50#define ENA_REGS_MMIO_RESP_LO_OFF 0x60 51#define ENA_REGS_MMIO_RESP_HI_OFF 0x64 52#define ENA_REGS_RSS_IND_ENTRY_UPDATE_OFF 0x68 53 54/* version register */ 55#define ENA_REGS_VERSION_MINOR_VERSION_MASK 0xff 56#define ENA_REGS_VERSION_MAJOR_VERSION_SHIFT 8 57#define ENA_REGS_VERSION_MAJOR_VERSION_MASK 0xff00 58 59/* controller_version register */ 60#define ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK 0xff 61#define ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT 8 62#define ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK 0xff00 63#define ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT 16 64#define ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK 0xff0000 65#define ENA_REGS_CONTROLLER_VERSION_IMPL_ID_SHIFT 24 66#define ENA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK 0xff000000 67 68/* caps register */ 69#define ENA_REGS_CAPS_CONTIGUOUS_QUEUE_REQUIRED_MASK 0x1 70#define ENA_REGS_CAPS_RESET_TIMEOUT_SHIFT 1 71#define ENA_REGS_CAPS_RESET_TIMEOUT_MASK 0x3e 72#define ENA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT 8 73#define ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK 0xff00 74#define ENA_REGS_CAPS_ADMIN_CMD_TO_SHIFT 16 75#define ENA_REGS_CAPS_ADMIN_CMD_TO_MASK 0xf0000 76 77/* aq_caps register */ 78#define ENA_REGS_AQ_CAPS_AQ_DEPTH_MASK 0xffff 79#define ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_SHIFT 16 80#define ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK 0xffff0000 81 82/* acq_caps register */ 83#define ENA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK 0xffff 84#define ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_SHIFT 16 85#define ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK 0xffff0000 86 87/* aenq_caps register */ 88#define ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK 0xffff 89#define ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT 16 90#define ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK 0xffff0000 91 92/* dev_ctl register */ 93#define ENA_REGS_DEV_CTL_DEV_RESET_MASK 0x1 94#define ENA_REGS_DEV_CTL_AQ_RESTART_SHIFT 1 95#define ENA_REGS_DEV_CTL_AQ_RESTART_MASK 0x2 96#define ENA_REGS_DEV_CTL_QUIESCENT_SHIFT 2 97#define ENA_REGS_DEV_CTL_QUIESCENT_MASK 0x4 98#define ENA_REGS_DEV_CTL_IO_RESUME_SHIFT 3 99#define ENA_REGS_DEV_CTL_IO_RESUME_MASK 0x8 100#define ENA_REGS_DEV_CTL_RESET_REASON_SHIFT 28 101#define ENA_REGS_DEV_CTL_RESET_REASON_MASK 0xf0000000 102 103/* dev_sts register */ 104#define ENA_REGS_DEV_STS_READY_MASK 0x1 105#define ENA_REGS_DEV_STS_AQ_RESTART_IN_PROGRESS_SHIFT 1 106#define ENA_REGS_DEV_STS_AQ_RESTART_IN_PROGRESS_MASK 0x2 107#define ENA_REGS_DEV_STS_AQ_RESTART_FINISHED_SHIFT 2 108#define ENA_REGS_DEV_STS_AQ_RESTART_FINISHED_MASK 0x4 109#define ENA_REGS_DEV_STS_RESET_IN_PROGRESS_SHIFT 3 110#define ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK 0x8 111#define ENA_REGS_DEV_STS_RESET_FINISHED_SHIFT 4 112#define ENA_REGS_DEV_STS_RESET_FINISHED_MASK 0x10 113#define ENA_REGS_DEV_STS_FATAL_ERROR_SHIFT 5 114#define ENA_REGS_DEV_STS_FATAL_ERROR_MASK 0x20 115#define ENA_REGS_DEV_STS_QUIESCENT_STATE_IN_PROGRESS_SHIFT 6 116#define ENA_REGS_DEV_STS_QUIESCENT_STATE_IN_PROGRESS_MASK 0x40 117#define ENA_REGS_DEV_STS_QUIESCENT_STATE_ACHIEVED_SHIFT 7 118#define ENA_REGS_DEV_STS_QUIESCENT_STATE_ACHIEVED_MASK 0x80 119 120/* mmio_reg_read register */ 121#define ENA_REGS_MMIO_REG_READ_REQ_ID_MASK 0xffff 122#define ENA_REGS_MMIO_REG_READ_REG_OFF_SHIFT 16 123#define ENA_REGS_MMIO_REG_READ_REG_OFF_MASK 0xffff0000 124 125/* rss_ind_entry_update register */ 126#define ENA_REGS_RSS_IND_ENTRY_UPDATE_INDEX_MASK 0xffff 127#define ENA_REGS_RSS_IND_ENTRY_UPDATE_CQ_IDX_SHIFT 16 128#define ENA_REGS_RSS_IND_ENTRY_UPDATE_CQ_IDX_MASK 0xffff0000 129 130#endif /* _ENA_REGS_H_ */