cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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mac.c (2733B)

      1// SPDX-License-Identifier: GPL-2.0-or-later
      2/*
      3 * Applied Micro X-Gene SoC Ethernet v2 Driver
      4 *
      5 * Copyright (c) 2017, Applied Micro Circuits Corporation
      6 * Author(s): Iyappan Subramanian <isubramanian@apm.com>
      7 *	      Keyur Chudgar <kchudgar@apm.com>
      8 */
      9
     10#include "main.h"
     11
     12void xge_mac_reset(struct xge_pdata *pdata)
     13{
     14	xge_wr_csr(pdata, MAC_CONFIG_1, SOFT_RESET);
     15	xge_wr_csr(pdata, MAC_CONFIG_1, 0);
     16}
     17
     18void xge_mac_set_speed(struct xge_pdata *pdata)
     19{
     20	u32 icm0, icm2, ecm0, mc2;
     21	u32 intf_ctrl, rgmii;
     22
     23	icm0 = xge_rd_csr(pdata, ICM_CONFIG0_REG_0);
     24	icm2 = xge_rd_csr(pdata, ICM_CONFIG2_REG_0);
     25	ecm0 = xge_rd_csr(pdata, ECM_CONFIG0_REG_0);
     26	rgmii = xge_rd_csr(pdata, RGMII_REG_0);
     27	mc2 = xge_rd_csr(pdata, MAC_CONFIG_2);
     28	intf_ctrl = xge_rd_csr(pdata, INTERFACE_CONTROL);
     29	icm2 |= CFG_WAITASYNCRD_EN;
     30
     31	switch (pdata->phy_speed) {
     32	case SPEED_10:
     33		SET_REG_BITS(&mc2, INTF_MODE, 1);
     34		SET_REG_BITS(&intf_ctrl, HD_MODE, 0);
     35		SET_REG_BITS(&icm0, CFG_MACMODE, 0);
     36		SET_REG_BITS(&icm2, CFG_WAITASYNCRD, 500);
     37		SET_REG_BIT(&rgmii, CFG_SPEED_125, 0);
     38		break;
     39	case SPEED_100:
     40		SET_REG_BITS(&mc2, INTF_MODE, 1);
     41		SET_REG_BITS(&intf_ctrl, HD_MODE, 1);
     42		SET_REG_BITS(&icm0, CFG_MACMODE, 1);
     43		SET_REG_BITS(&icm2, CFG_WAITASYNCRD, 80);
     44		SET_REG_BIT(&rgmii, CFG_SPEED_125, 0);
     45		break;
     46	default:
     47		SET_REG_BITS(&mc2, INTF_MODE, 2);
     48		SET_REG_BITS(&intf_ctrl, HD_MODE, 2);
     49		SET_REG_BITS(&icm0, CFG_MACMODE, 2);
     50		SET_REG_BITS(&icm2, CFG_WAITASYNCRD, 16);
     51		SET_REG_BIT(&rgmii, CFG_SPEED_125, 1);
     52		break;
     53	}
     54
     55	mc2 |= FULL_DUPLEX | CRC_EN | PAD_CRC;
     56	SET_REG_BITS(&ecm0, CFG_WFIFOFULLTHR, 0x32);
     57
     58	xge_wr_csr(pdata, MAC_CONFIG_2, mc2);
     59	xge_wr_csr(pdata, INTERFACE_CONTROL, intf_ctrl);
     60	xge_wr_csr(pdata, RGMII_REG_0, rgmii);
     61	xge_wr_csr(pdata, ICM_CONFIG0_REG_0, icm0);
     62	xge_wr_csr(pdata, ICM_CONFIG2_REG_0, icm2);
     63	xge_wr_csr(pdata, ECM_CONFIG0_REG_0, ecm0);
     64}
     65
     66void xge_mac_set_station_addr(struct xge_pdata *pdata)
     67{
     68	const u8 *dev_addr = pdata->ndev->dev_addr;
     69	u32 addr0, addr1;
     70
     71	addr0 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
     72		(dev_addr[1] << 8) | dev_addr[0];
     73	addr1 = (dev_addr[5] << 24) | (dev_addr[4] << 16);
     74
     75	xge_wr_csr(pdata, STATION_ADDR0, addr0);
     76	xge_wr_csr(pdata, STATION_ADDR1, addr1);
     77}
     78
     79void xge_mac_init(struct xge_pdata *pdata)
     80{
     81	xge_mac_reset(pdata);
     82	xge_mac_set_speed(pdata);
     83	xge_mac_set_station_addr(pdata);
     84}
     85
     86void xge_mac_enable(struct xge_pdata *pdata)
     87{
     88	u32 data;
     89
     90	data = xge_rd_csr(pdata, MAC_CONFIG_1);
     91	data |= TX_EN | RX_EN;
     92	xge_wr_csr(pdata, MAC_CONFIG_1, data);
     93
     94	data = xge_rd_csr(pdata, MAC_CONFIG_1);
     95}
     96
     97void xge_mac_disable(struct xge_pdata *pdata)
     98{
     99	u32 data;
    100
    101	data = xge_rd_csr(pdata, MAC_CONFIG_1);
    102	data &= ~(TX_EN | RX_EN);
    103	xge_wr_csr(pdata, MAC_CONFIG_1, data);
    104}