atl2.h (15443B)
1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* atl2.h -- atl2 driver definitions 3 * 4 * Copyright(c) 2007 Atheros Corporation. All rights reserved. 5 * Copyright(c) 2006 xiong huang <xiong.huang@atheros.com> 6 * Copyright(c) 2007 Chris Snook <csnook@redhat.com> 7 * 8 * Derived from Intel e1000 driver 9 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. 10 */ 11 12#ifndef _ATL2_H_ 13#define _ATL2_H_ 14 15#include <linux/atomic.h> 16#include <linux/netdevice.h> 17 18#ifndef _ATL2_HW_H_ 19#define _ATL2_HW_H_ 20 21#ifndef _ATL2_OSDEP_H_ 22#define _ATL2_OSDEP_H_ 23 24#include <linux/pci.h> 25#include <linux/delay.h> 26#include <linux/interrupt.h> 27#include <linux/if_ether.h> 28 29#include "atlx.h" 30 31#ifdef ETHTOOL_OPS_COMPAT 32int ethtool_ioctl(struct ifreq *ifr); 33#endif 34 35#define PCI_COMMAND_REGISTER PCI_COMMAND 36#define CMD_MEM_WRT_INVALIDATE PCI_COMMAND_INVALIDATE 37 38#define ATL2_WRITE_REG(a, reg, value) (iowrite32((value), \ 39 ((a)->hw_addr + (reg)))) 40 41#define ATL2_WRITE_FLUSH(a) (ioread32((a)->hw_addr)) 42 43#define ATL2_READ_REG(a, reg) (ioread32((a)->hw_addr + (reg))) 44 45#define ATL2_WRITE_REGB(a, reg, value) (iowrite8((value), \ 46 ((a)->hw_addr + (reg)))) 47 48#define ATL2_READ_REGB(a, reg) (ioread8((a)->hw_addr + (reg))) 49 50#define ATL2_WRITE_REGW(a, reg, value) (iowrite16((value), \ 51 ((a)->hw_addr + (reg)))) 52 53#define ATL2_READ_REGW(a, reg) (ioread16((a)->hw_addr + (reg))) 54 55#define ATL2_WRITE_REG_ARRAY(a, reg, offset, value) \ 56 (iowrite32((value), (((a)->hw_addr + (reg)) + ((offset) << 2)))) 57 58#define ATL2_READ_REG_ARRAY(a, reg, offset) \ 59 (ioread32(((a)->hw_addr + (reg)) + ((offset) << 2))) 60 61#endif /* _ATL2_OSDEP_H_ */ 62 63struct atl2_adapter; 64struct atl2_hw; 65 66/* function prototype */ 67static s32 atl2_reset_hw(struct atl2_hw *hw); 68static s32 atl2_read_mac_addr(struct atl2_hw *hw); 69static s32 atl2_init_hw(struct atl2_hw *hw); 70static s32 atl2_get_speed_and_duplex(struct atl2_hw *hw, u16 *speed, 71 u16 *duplex); 72static u32 atl2_hash_mc_addr(struct atl2_hw *hw, u8 *mc_addr); 73static void atl2_hash_set(struct atl2_hw *hw, u32 hash_value); 74static s32 atl2_read_phy_reg(struct atl2_hw *hw, u16 reg_addr, u16 *phy_data); 75static s32 atl2_write_phy_reg(struct atl2_hw *hw, u32 reg_addr, u16 phy_data); 76static void atl2_read_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value); 77static void atl2_write_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value); 78static void atl2_set_mac_addr(struct atl2_hw *hw); 79static bool atl2_read_eeprom(struct atl2_hw *hw, u32 Offset, u32 *pValue); 80static bool atl2_write_eeprom(struct atl2_hw *hw, u32 offset, u32 value); 81static s32 atl2_phy_init(struct atl2_hw *hw); 82static int atl2_check_eeprom_exist(struct atl2_hw *hw); 83static void atl2_force_ps(struct atl2_hw *hw); 84 85/* register definition */ 86 87/* Block IDLE Status Register */ 88#define IDLE_STATUS_RXMAC 1 /* 1: RXMAC is non-IDLE */ 89#define IDLE_STATUS_TXMAC 2 /* 1: TXMAC is non-IDLE */ 90#define IDLE_STATUS_DMAR 8 /* 1: DMAR is non-IDLE */ 91#define IDLE_STATUS_DMAW 4 /* 1: DMAW is non-IDLE */ 92 93/* MDIO Control Register */ 94#define MDIO_WAIT_TIMES 10 95 96/* MAC Control Register */ 97#define MAC_CTRL_DBG_TX_BKPRESURE 0x100000 /* 1: TX max backoff */ 98#define MAC_CTRL_MACLP_CLK_PHY 0x8000000 /* 1: 25MHz from phy */ 99#define MAC_CTRL_HALF_LEFT_BUF_SHIFT 28 100#define MAC_CTRL_HALF_LEFT_BUF_MASK 0xF /* MAC retry buf x32B */ 101 102/* Internal SRAM Partition Register */ 103#define REG_SRAM_TXRAM_END 0x1500 /* Internal tail address of TXRAM 104 * default: 2byte*1024 */ 105#define REG_SRAM_RXRAM_END 0x1502 /* Internal tail address of RXRAM 106 * default: 2byte*1024 */ 107 108/* Descriptor Control register */ 109#define REG_TXD_BASE_ADDR_LO 0x1544 /* The base address of the Transmit 110 * Data Mem low 32-bit(dword align) */ 111#define REG_TXD_MEM_SIZE 0x1548 /* Transmit Data Memory size(by 112 * double word , max 256KB) */ 113#define REG_TXS_BASE_ADDR_LO 0x154C /* The base address of the Transmit 114 * Status Memory low 32-bit(dword word 115 * align) */ 116#define REG_TXS_MEM_SIZE 0x1550 /* double word unit, max 4*2047 117 * bytes. */ 118#define REG_RXD_BASE_ADDR_LO 0x1554 /* The base address of the Transmit 119 * Status Memory low 32-bit(unit 8 120 * bytes) */ 121#define REG_RXD_BUF_NUM 0x1558 /* Receive Data & Status Memory buffer 122 * number (unit 1536bytes, max 123 * 1536*2047) */ 124 125/* DMAR Control Register */ 126#define REG_DMAR 0x1580 127#define DMAR_EN 0x1 /* 1: Enable DMAR */ 128 129/* TX Cur-Through (early tx threshold) Control Register */ 130#define REG_TX_CUT_THRESH 0x1590 /* TxMac begin transmit packet 131 * threshold(unit word) */ 132 133/* DMAW Control Register */ 134#define REG_DMAW 0x15A0 135#define DMAW_EN 0x1 136 137/* Flow control register */ 138#define REG_PAUSE_ON_TH 0x15A8 /* RXD high watermark of overflow 139 * threshold configuration register */ 140#define REG_PAUSE_OFF_TH 0x15AA /* RXD lower watermark of overflow 141 * threshold configuration register */ 142 143/* Mailbox Register */ 144#define REG_MB_TXD_WR_IDX 0x15f0 /* double word align */ 145#define REG_MB_RXD_RD_IDX 0x15F4 /* RXD Read index (unit: 1536byets) */ 146 147/* Interrupt Status Register */ 148#define ISR_TIMER 1 /* Interrupt when Timer counts down to zero */ 149#define ISR_MANUAL 2 /* Software manual interrupt, for debug. Set 150 * when SW_MAN_INT_EN is set in Table 51 151 * Selene Master Control Register 152 * (Offset 0x1400). */ 153#define ISR_RXF_OV 4 /* RXF overflow interrupt */ 154#define ISR_TXF_UR 8 /* TXF underrun interrupt */ 155#define ISR_TXS_OV 0x10 /* Internal transmit status buffer full 156 * interrupt */ 157#define ISR_RXS_OV 0x20 /* Internal receive status buffer full 158 * interrupt */ 159#define ISR_LINK_CHG 0x40 /* Link Status Change Interrupt */ 160#define ISR_HOST_TXD_UR 0x80 161#define ISR_HOST_RXD_OV 0x100 /* Host rx data memory full , one pulse */ 162#define ISR_DMAR_TO_RST 0x200 /* DMAR op timeout interrupt. SW should 163 * do Reset */ 164#define ISR_DMAW_TO_RST 0x400 165#define ISR_PHY 0x800 /* phy interrupt */ 166#define ISR_TS_UPDATE 0x10000 /* interrupt after new tx pkt status written 167 * to host */ 168#define ISR_RS_UPDATE 0x20000 /* interrupt ater new rx pkt status written 169 * to host. */ 170#define ISR_TX_EARLY 0x40000 /* interrupt when txmac begin transmit one 171 * packet */ 172 173#define ISR_TX_EVENT (ISR_TXF_UR | ISR_TXS_OV | ISR_HOST_TXD_UR |\ 174 ISR_TS_UPDATE | ISR_TX_EARLY) 175#define ISR_RX_EVENT (ISR_RXF_OV | ISR_RXS_OV | ISR_HOST_RXD_OV |\ 176 ISR_RS_UPDATE) 177 178#define IMR_NORMAL_MASK (\ 179 /*ISR_LINK_CHG |*/\ 180 ISR_MANUAL |\ 181 ISR_DMAR_TO_RST |\ 182 ISR_DMAW_TO_RST |\ 183 ISR_PHY |\ 184 ISR_PHY_LINKDOWN |\ 185 ISR_TS_UPDATE |\ 186 ISR_RS_UPDATE) 187 188/* Receive MAC Statistics Registers */ 189#define REG_STS_RX_PAUSE 0x1700 /* Num pause packets received */ 190#define REG_STS_RXD_OV 0x1704 /* Num frames dropped due to RX 191 * FIFO overflow */ 192#define REG_STS_RXS_OV 0x1708 /* Num frames dropped due to RX 193 * Status Buffer Overflow */ 194#define REG_STS_RX_FILTER 0x170C /* Num packets dropped due to 195 * address filtering */ 196 197/* MII definitions */ 198 199/* PHY Common Register */ 200#define MII_SMARTSPEED 0x14 201#define MII_DBG_ADDR 0x1D 202#define MII_DBG_DATA 0x1E 203 204/* PCI Command Register Bit Definitions */ 205#define PCI_REG_COMMAND 0x04 206#define CMD_IO_SPACE 0x0001 207#define CMD_MEMORY_SPACE 0x0002 208#define CMD_BUS_MASTER 0x0004 209 210#define MEDIA_TYPE_100M_FULL 1 211#define MEDIA_TYPE_100M_HALF 2 212#define MEDIA_TYPE_10M_FULL 3 213#define MEDIA_TYPE_10M_HALF 4 214 215#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x000F /* Everything */ 216 217/* The size (in bytes) of a ethernet packet */ 218#define MAXIMUM_ETHERNET_FRAME_SIZE 1518 /* with FCS */ 219#define MINIMUM_ETHERNET_FRAME_SIZE 64 /* with FCS */ 220#define MAX_JUMBO_FRAME_SIZE 0x2000 221 222struct tx_pkt_header { 223 unsigned pkt_size:11; 224 unsigned:4; /* reserved */ 225 unsigned ins_vlan:1; /* txmac should insert vlan */ 226 unsigned short vlan; /* vlan tag */ 227}; 228/* FIXME: replace above bitfields with MASK/SHIFT defines below */ 229#define TX_PKT_HEADER_SIZE_MASK 0x7FF 230#define TX_PKT_HEADER_SIZE_SHIFT 0 231#define TX_PKT_HEADER_INS_VLAN_MASK 0x1 232#define TX_PKT_HEADER_INS_VLAN_SHIFT 15 233#define TX_PKT_HEADER_VLAN_TAG_MASK 0xFFFF 234#define TX_PKT_HEADER_VLAN_TAG_SHIFT 16 235 236struct tx_pkt_status { 237 unsigned pkt_size:11; 238 unsigned:5; /* reserved */ 239 unsigned ok:1; /* current packet transmitted without error */ 240 unsigned bcast:1; /* broadcast packet */ 241 unsigned mcast:1; /* multicast packet */ 242 unsigned pause:1; /* transmiited a pause frame */ 243 unsigned ctrl:1; 244 unsigned defer:1; /* current packet is xmitted with defer */ 245 unsigned exc_defer:1; 246 unsigned single_col:1; 247 unsigned multi_col:1; 248 unsigned late_col:1; 249 unsigned abort_col:1; 250 unsigned underrun:1; /* current packet is aborted 251 * due to txram underrun */ 252 unsigned:3; /* reserved */ 253 unsigned update:1; /* always 1'b1 in tx_status_buf */ 254}; 255/* FIXME: replace above bitfields with MASK/SHIFT defines below */ 256#define TX_PKT_STATUS_SIZE_MASK 0x7FF 257#define TX_PKT_STATUS_SIZE_SHIFT 0 258#define TX_PKT_STATUS_OK_MASK 0x1 259#define TX_PKT_STATUS_OK_SHIFT 16 260#define TX_PKT_STATUS_BCAST_MASK 0x1 261#define TX_PKT_STATUS_BCAST_SHIFT 17 262#define TX_PKT_STATUS_MCAST_MASK 0x1 263#define TX_PKT_STATUS_MCAST_SHIFT 18 264#define TX_PKT_STATUS_PAUSE_MASK 0x1 265#define TX_PKT_STATUS_PAUSE_SHIFT 19 266#define TX_PKT_STATUS_CTRL_MASK 0x1 267#define TX_PKT_STATUS_CTRL_SHIFT 20 268#define TX_PKT_STATUS_DEFER_MASK 0x1 269#define TX_PKT_STATUS_DEFER_SHIFT 21 270#define TX_PKT_STATUS_EXC_DEFER_MASK 0x1 271#define TX_PKT_STATUS_EXC_DEFER_SHIFT 22 272#define TX_PKT_STATUS_SINGLE_COL_MASK 0x1 273#define TX_PKT_STATUS_SINGLE_COL_SHIFT 23 274#define TX_PKT_STATUS_MULTI_COL_MASK 0x1 275#define TX_PKT_STATUS_MULTI_COL_SHIFT 24 276#define TX_PKT_STATUS_LATE_COL_MASK 0x1 277#define TX_PKT_STATUS_LATE_COL_SHIFT 25 278#define TX_PKT_STATUS_ABORT_COL_MASK 0x1 279#define TX_PKT_STATUS_ABORT_COL_SHIFT 26 280#define TX_PKT_STATUS_UNDERRUN_MASK 0x1 281#define TX_PKT_STATUS_UNDERRUN_SHIFT 27 282#define TX_PKT_STATUS_UPDATE_MASK 0x1 283#define TX_PKT_STATUS_UPDATE_SHIFT 31 284 285struct rx_pkt_status { 286 unsigned pkt_size:11; /* packet size, max 2047 bytes */ 287 unsigned:5; /* reserved */ 288 unsigned ok:1; /* current packet received ok without error */ 289 unsigned bcast:1; /* current packet is broadcast */ 290 unsigned mcast:1; /* current packet is multicast */ 291 unsigned pause:1; 292 unsigned ctrl:1; 293 unsigned crc:1; /* received a packet with crc error */ 294 unsigned code:1; /* received a packet with code error */ 295 unsigned runt:1; /* received a packet less than 64 bytes 296 * with good crc */ 297 unsigned frag:1; /* received a packet less than 64 bytes 298 * with bad crc */ 299 unsigned trunc:1; /* current frame truncated due to rxram full */ 300 unsigned align:1; /* this packet is alignment error */ 301 unsigned vlan:1; /* this packet has vlan */ 302 unsigned:3; /* reserved */ 303 unsigned update:1; 304 unsigned short vtag; /* vlan tag */ 305 unsigned:16; 306}; 307/* FIXME: replace above bitfields with MASK/SHIFT defines below */ 308#define RX_PKT_STATUS_SIZE_MASK 0x7FF 309#define RX_PKT_STATUS_SIZE_SHIFT 0 310#define RX_PKT_STATUS_OK_MASK 0x1 311#define RX_PKT_STATUS_OK_SHIFT 16 312#define RX_PKT_STATUS_BCAST_MASK 0x1 313#define RX_PKT_STATUS_BCAST_SHIFT 17 314#define RX_PKT_STATUS_MCAST_MASK 0x1 315#define RX_PKT_STATUS_MCAST_SHIFT 18 316#define RX_PKT_STATUS_PAUSE_MASK 0x1 317#define RX_PKT_STATUS_PAUSE_SHIFT 19 318#define RX_PKT_STATUS_CTRL_MASK 0x1 319#define RX_PKT_STATUS_CTRL_SHIFT 20 320#define RX_PKT_STATUS_CRC_MASK 0x1 321#define RX_PKT_STATUS_CRC_SHIFT 21 322#define RX_PKT_STATUS_CODE_MASK 0x1 323#define RX_PKT_STATUS_CODE_SHIFT 22 324#define RX_PKT_STATUS_RUNT_MASK 0x1 325#define RX_PKT_STATUS_RUNT_SHIFT 23 326#define RX_PKT_STATUS_FRAG_MASK 0x1 327#define RX_PKT_STATUS_FRAG_SHIFT 24 328#define RX_PKT_STATUS_TRUNK_MASK 0x1 329#define RX_PKT_STATUS_TRUNK_SHIFT 25 330#define RX_PKT_STATUS_ALIGN_MASK 0x1 331#define RX_PKT_STATUS_ALIGN_SHIFT 26 332#define RX_PKT_STATUS_VLAN_MASK 0x1 333#define RX_PKT_STATUS_VLAN_SHIFT 27 334#define RX_PKT_STATUS_UPDATE_MASK 0x1 335#define RX_PKT_STATUS_UPDATE_SHIFT 31 336#define RX_PKT_STATUS_VLAN_TAG_MASK 0xFFFF 337#define RX_PKT_STATUS_VLAN_TAG_SHIFT 32 338 339struct rx_desc { 340 struct rx_pkt_status status; 341 unsigned char packet[1536-sizeof(struct rx_pkt_status)]; 342}; 343 344enum atl2_speed_duplex { 345 atl2_10_half = 0, 346 atl2_10_full = 1, 347 atl2_100_half = 2, 348 atl2_100_full = 3 349}; 350 351struct atl2_spi_flash_dev { 352 const char *manu_name; /* manufacturer id */ 353 /* op-code */ 354 u8 cmdWRSR; 355 u8 cmdREAD; 356 u8 cmdPROGRAM; 357 u8 cmdWREN; 358 u8 cmdWRDI; 359 u8 cmdRDSR; 360 u8 cmdRDID; 361 u8 cmdSECTOR_ERASE; 362 u8 cmdCHIP_ERASE; 363}; 364 365/* Structure containing variables used by the shared code (atl2_hw.c) */ 366struct atl2_hw { 367 u8 __iomem *hw_addr; 368 void *back; 369 370 u8 preamble_len; 371 u8 max_retry; /* Retransmission maximum, afterwards the 372 * packet will be discarded. */ 373 u8 jam_ipg; /* IPG to start JAM for collision based flow 374 * control in half-duplex mode. In unit of 375 * 8-bit time. */ 376 u8 ipgt; /* Desired back to back inter-packet gap. The 377 * default is 96-bit time. */ 378 u8 min_ifg; /* Minimum number of IFG to enforce in between 379 * RX frames. Frame gap below such IFP is 380 * dropped. */ 381 u8 ipgr1; /* 64bit Carrier-Sense window */ 382 u8 ipgr2; /* 96-bit IPG window */ 383 u8 retry_buf; /* When half-duplex mode, should hold some 384 * bytes for mac retry . (8*4bytes unit) */ 385 386 u16 fc_rxd_hi; 387 u16 fc_rxd_lo; 388 u16 lcol; /* Collision Window */ 389 u16 max_frame_size; 390 391 u16 MediaType; 392 u16 autoneg_advertised; 393 u16 pci_cmd_word; 394 395 u16 mii_autoneg_adv_reg; 396 397 u32 mem_rang; 398 u32 txcw; 399 u32 mc_filter_type; 400 u32 num_mc_addrs; 401 u32 collision_delta; 402 u32 tx_packet_delta; 403 u16 phy_spd_default; 404 405 u16 device_id; 406 u16 vendor_id; 407 u16 subsystem_id; 408 u16 subsystem_vendor_id; 409 u8 revision_id; 410 411 /* spi flash */ 412 u8 flash_vendor; 413 414 u8 dma_fairness; 415 u8 mac_addr[ETH_ALEN]; 416 u8 perm_mac_addr[ETH_ALEN]; 417 418 /* FIXME */ 419 /* bool phy_preamble_sup; */ 420 bool phy_configured; 421}; 422 423#endif /* _ATL2_HW_H_ */ 424 425struct atl2_ring_header { 426 /* pointer to the descriptor ring memory */ 427 void *desc; 428 /* physical address of the descriptor ring */ 429 dma_addr_t dma; 430 /* length of descriptor ring in bytes */ 431 unsigned int size; 432}; 433 434/* board specific private data structure */ 435struct atl2_adapter { 436 /* OS defined structs */ 437 struct net_device *netdev; 438 struct pci_dev *pdev; 439 u32 wol; 440 u16 link_speed; 441 u16 link_duplex; 442 443 spinlock_t stats_lock; 444 445 struct work_struct reset_task; 446 struct work_struct link_chg_task; 447 struct timer_list watchdog_timer; 448 struct timer_list phy_config_timer; 449 450 unsigned long cfg_phy; 451 bool mac_disabled; 452 453 /* All Descriptor memory */ 454 dma_addr_t ring_dma; 455 void *ring_vir_addr; 456 int ring_size; 457 458 struct tx_pkt_header *txd_ring; 459 dma_addr_t txd_dma; 460 461 struct tx_pkt_status *txs_ring; 462 dma_addr_t txs_dma; 463 464 struct rx_desc *rxd_ring; 465 dma_addr_t rxd_dma; 466 467 u32 txd_ring_size; /* bytes per unit */ 468 u32 txs_ring_size; /* dwords per unit */ 469 u32 rxd_ring_size; /* 1536 bytes per unit */ 470 471 /* read /write ptr: */ 472 /* host */ 473 u32 txd_write_ptr; 474 u32 txs_next_clear; 475 u32 rxd_read_ptr; 476 477 /* nic */ 478 atomic_t txd_read_ptr; 479 atomic_t txs_write_ptr; 480 u32 rxd_write_ptr; 481 482 /* Interrupt Moderator timer ( 2us resolution) */ 483 u16 imt; 484 /* Interrupt Clear timer (2us resolution) */ 485 u16 ict; 486 487 unsigned long flags; 488 /* structs defined in atl2_hw.h */ 489 u32 bd_number; /* board number */ 490 bool pci_using_64; 491 bool have_msi; 492 struct atl2_hw hw; 493 494 u32 usr_cmd; 495 /* FIXME */ 496 /* u32 regs_buff[ATL2_REGS_LEN]; */ 497 u32 pci_state[16]; 498 499 u32 *config_space; 500}; 501 502enum atl2_state_t { 503 __ATL2_TESTING, 504 __ATL2_RESETTING, 505 __ATL2_DOWN 506}; 507 508#endif /* _ATL2_H_ */