cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

octeon_device.h (25568B)


      1/**********************************************************************
      2 * Author: Cavium, Inc.
      3 *
      4 * Contact: support@cavium.com
      5 *          Please include "LiquidIO" in the subject.
      6 *
      7 * Copyright (c) 2003-2016 Cavium, Inc.
      8 *
      9 * This file is free software; you can redistribute it and/or modify
     10 * it under the terms of the GNU General Public License, Version 2, as
     11 * published by the Free Software Foundation.
     12 *
     13 * This file is distributed in the hope that it will be useful, but
     14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
     15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
     16 * NONINFRINGEMENT.  See the GNU General Public License for more details.
     17 ***********************************************************************/
     18/*! \file octeon_device.h
     19 *  \brief Host Driver: This file defines the octeon device structure.
     20 */
     21
     22#ifndef _OCTEON_DEVICE_H_
     23#define  _OCTEON_DEVICE_H_
     24
     25#include <linux/interrupt.h>
     26#include <net/devlink.h>
     27
     28/** PCI VendorId Device Id */
     29#define  OCTEON_CN68XX_PCIID          0x91177d
     30#define  OCTEON_CN66XX_PCIID          0x92177d
     31#define  OCTEON_CN23XX_PCIID_PF       0x9702177d
     32/** Driver identifies chips by these Ids, created by clubbing together
     33 *  DeviceId+RevisionId; Where Revision Id is not used to distinguish
     34 *  between chips, a value of 0 is used for revision id.
     35 */
     36#define  OCTEON_CN68XX                0x0091
     37#define  OCTEON_CN66XX                0x0092
     38#define  OCTEON_CN23XX_PF_VID         0x9702
     39#define  OCTEON_CN23XX_VF_VID         0x9712
     40
     41/**RevisionId for the chips */
     42#define  OCTEON_CN23XX_REV_1_0        0x00
     43#define  OCTEON_CN23XX_REV_1_1        0x01
     44#define  OCTEON_CN23XX_REV_2_0        0x80
     45
     46/**SubsystemId for the chips */
     47#define	 OCTEON_CN2350_10GB_SUBSYS_ID_1	0X3177d
     48#define	 OCTEON_CN2350_10GB_SUBSYS_ID_2	0X4177d
     49#define	 OCTEON_CN2360_10GB_SUBSYS_ID	0X5177d
     50#define	 OCTEON_CN2350_25GB_SUBSYS_ID	0X7177d
     51#define	 OCTEON_CN2360_25GB_SUBSYS_ID	0X6177d
     52
     53/** Endian-swap modes supported by Octeon. */
     54enum octeon_pci_swap_mode {
     55	OCTEON_PCI_PASSTHROUGH = 0,
     56	OCTEON_PCI_64BIT_SWAP = 1,
     57	OCTEON_PCI_32BIT_BYTE_SWAP = 2,
     58	OCTEON_PCI_32BIT_LW_SWAP = 3
     59};
     60
     61enum lio_fw_state {
     62	FW_IS_PRELOADED = 0,
     63	FW_NEEDS_TO_BE_LOADED = 1,
     64	FW_IS_BEING_LOADED = 2,
     65	FW_HAS_BEEN_LOADED = 3,
     66};
     67
     68enum {
     69	OCTEON_CONFIG_TYPE_DEFAULT = 0,
     70	NUM_OCTEON_CONFS,
     71};
     72
     73#define  OCTEON_INPUT_INTR    (1)
     74#define  OCTEON_OUTPUT_INTR   (2)
     75#define  OCTEON_MBOX_INTR     (4)
     76#define  OCTEON_ALL_INTR      0xff
     77
     78/*---------------   PCI BAR1 index registers -------------*/
     79
     80/* BAR1 Mask */
     81#define    PCI_BAR1_ENABLE_CA            1
     82#define    PCI_BAR1_ENDIAN_MODE          OCTEON_PCI_64BIT_SWAP
     83#define    PCI_BAR1_ENTRY_VALID          1
     84#define    PCI_BAR1_MASK                 ((PCI_BAR1_ENABLE_CA << 3)   \
     85					    | (PCI_BAR1_ENDIAN_MODE << 1) \
     86					    | PCI_BAR1_ENTRY_VALID)
     87
     88/** Octeon Device state.
     89 *  Each octeon device goes through each of these states
     90 *  as it is initialized.
     91 */
     92#define    OCT_DEV_BEGIN_STATE            0x0
     93#define    OCT_DEV_PCI_ENABLE_DONE        0x1
     94#define    OCT_DEV_PCI_MAP_DONE           0x2
     95#define    OCT_DEV_DISPATCH_INIT_DONE     0x3
     96#define    OCT_DEV_INSTR_QUEUE_INIT_DONE  0x4
     97#define    OCT_DEV_SC_BUFF_POOL_INIT_DONE 0x5
     98#define    OCT_DEV_RESP_LIST_INIT_DONE    0x6
     99#define    OCT_DEV_DROQ_INIT_DONE         0x7
    100#define    OCT_DEV_MBOX_SETUP_DONE        0x8
    101#define    OCT_DEV_MSIX_ALLOC_VECTOR_DONE 0x9
    102#define    OCT_DEV_INTR_SET_DONE          0xa
    103#define    OCT_DEV_IO_QUEUES_DONE         0xb
    104#define    OCT_DEV_CONSOLE_INIT_DONE      0xc
    105#define    OCT_DEV_HOST_OK                0xd
    106#define    OCT_DEV_CORE_OK                0xe
    107#define    OCT_DEV_RUNNING                0xf
    108#define    OCT_DEV_IN_RESET               0x10
    109#define    OCT_DEV_STATE_INVALID          0x11
    110
    111#define    OCT_DEV_STATES                 OCT_DEV_STATE_INVALID
    112
    113/** Octeon Device interrupts
    114 * These interrupt bits are set in int_status filed of
    115 * octeon_device structure
    116 */
    117#define	   OCT_DEV_INTR_DMA0_FORCE	  0x01
    118#define	   OCT_DEV_INTR_DMA1_FORCE	  0x02
    119#define	   OCT_DEV_INTR_PKT_DATA	  0x04
    120
    121#define LIO_RESET_SECS (3)
    122
    123/*---------------------------DISPATCH LIST-------------------------------*/
    124
    125/** The dispatch list entry.
    126 *  The driver keeps a record of functions registered for each
    127 *  response header opcode in this structure. Since the opcode is
    128 *  hashed to index into the driver's list, more than one opcode
    129 *  can hash to the same entry, in which case the list field points
    130 *  to a linked list with the other entries.
    131 */
    132struct octeon_dispatch {
    133	/** List head for this entry */
    134	struct list_head list;
    135
    136	/** The opcode for which the dispatch function & arg should be used */
    137	u16 opcode;
    138
    139	/** The function to be called for a packet received by the driver */
    140	octeon_dispatch_fn_t dispatch_fn;
    141
    142	/* The application specified argument to be passed to the above
    143	 * function along with the received packet
    144	 */
    145	void *arg;
    146};
    147
    148/** The dispatch list structure. */
    149struct octeon_dispatch_list {
    150	/** access to dispatch list must be atomic */
    151	spinlock_t lock;
    152
    153	/** Count of dispatch functions currently registered */
    154	u32 count;
    155
    156	/** The list of dispatch functions */
    157	struct octeon_dispatch *dlist;
    158};
    159
    160/*-----------------------  THE OCTEON DEVICE  ---------------------------*/
    161
    162#define OCT_MEM_REGIONS     3
    163/** PCI address space mapping information.
    164 *  Each of the 3 address spaces given by BAR0, BAR2 and BAR4 of
    165 *  Octeon gets mapped to different physical address spaces in
    166 *  the kernel.
    167 */
    168struct octeon_mmio {
    169	/** PCI address to which the BAR is mapped. */
    170	u64 start;
    171
    172	/** Length of this PCI address space. */
    173	u32 len;
    174
    175	/** Length that has been mapped to phys. address space. */
    176	u32 mapped_len;
    177
    178	/** The physical address to which the PCI address space is mapped. */
    179	u8 __iomem *hw_addr;
    180
    181	/** Flag indicating the mapping was successful. */
    182	u32 done;
    183};
    184
    185#define   MAX_OCTEON_MAPS    32
    186
    187struct octeon_io_enable {
    188	u64 iq;
    189	u64 oq;
    190	u64 iq64B;
    191};
    192
    193struct octeon_reg_list {
    194	u32 __iomem *pci_win_wr_addr_hi;
    195	u32 __iomem *pci_win_wr_addr_lo;
    196	u64 __iomem *pci_win_wr_addr;
    197
    198	u32 __iomem *pci_win_rd_addr_hi;
    199	u32 __iomem *pci_win_rd_addr_lo;
    200	u64 __iomem *pci_win_rd_addr;
    201
    202	u32 __iomem *pci_win_wr_data_hi;
    203	u32 __iomem *pci_win_wr_data_lo;
    204	u64 __iomem *pci_win_wr_data;
    205
    206	u32 __iomem *pci_win_rd_data_hi;
    207	u32 __iomem *pci_win_rd_data_lo;
    208	u64 __iomem *pci_win_rd_data;
    209};
    210
    211#define OCTEON_CONSOLE_MAX_READ_BYTES 512
    212typedef int (*octeon_console_print_fn)(struct octeon_device *oct,
    213				       u32 num, char *pre, char *suf);
    214struct octeon_console {
    215	u32 active;
    216	u32 waiting;
    217	u64 addr;
    218	u32 buffer_size;
    219	u64 input_base_addr;
    220	u64 output_base_addr;
    221	octeon_console_print_fn print;
    222	char leftover[OCTEON_CONSOLE_MAX_READ_BYTES];
    223};
    224
    225struct octeon_board_info {
    226	char name[OCT_BOARD_NAME];
    227	char serial_number[OCT_SERIAL_LEN];
    228	u64 major;
    229	u64 minor;
    230};
    231
    232struct octeon_fn_list {
    233	void (*setup_iq_regs)(struct octeon_device *, u32);
    234	void (*setup_oq_regs)(struct octeon_device *, u32);
    235
    236	irqreturn_t (*process_interrupt_regs)(void *);
    237	u64 (*msix_interrupt_handler)(void *);
    238
    239	int (*setup_mbox)(struct octeon_device *);
    240	int (*free_mbox)(struct octeon_device *);
    241
    242	int (*soft_reset)(struct octeon_device *);
    243	int (*setup_device_regs)(struct octeon_device *);
    244	void (*bar1_idx_setup)(struct octeon_device *, u64, u32, int);
    245	void (*bar1_idx_write)(struct octeon_device *, u32, u32);
    246	u32 (*bar1_idx_read)(struct octeon_device *, u32);
    247	u32 (*update_iq_read_idx)(struct octeon_instr_queue *);
    248
    249	void (*enable_oq_pkt_time_intr)(struct octeon_device *, u32);
    250	void (*disable_oq_pkt_time_intr)(struct octeon_device *, u32);
    251
    252	void (*enable_interrupt)(struct octeon_device *, u8);
    253	void (*disable_interrupt)(struct octeon_device *, u8);
    254
    255	int (*enable_io_queues)(struct octeon_device *);
    256	void (*disable_io_queues)(struct octeon_device *);
    257};
    258
    259/* Must be multiple of 8, changing breaks ABI */
    260#define CVMX_BOOTMEM_NAME_LEN 128
    261
    262/* Structure for named memory blocks
    263 * Number of descriptors
    264 * available can be changed without affecting compatibility,
    265 * but name length changes require a bump in the bootmem
    266 * descriptor version
    267 * Note: This structure must be naturally 64 bit aligned, as a single
    268 * memory image will be used by both 32 and 64 bit programs.
    269 */
    270struct cvmx_bootmem_named_block_desc {
    271	/** Base address of named block */
    272	u64 base_addr;
    273
    274	/** Size actually allocated for named block */
    275	u64 size;
    276
    277	/** name of named block */
    278	char name[CVMX_BOOTMEM_NAME_LEN];
    279};
    280
    281struct oct_fw_info {
    282	u32 max_nic_ports;      /** max nic ports for the device */
    283	u32 num_gmx_ports;      /** num gmx ports */
    284	u64 app_cap_flags;      /** firmware cap flags */
    285
    286	/** The core application is running in this mode.
    287	 * See octeon-drv-opcodes.h for values.
    288	 */
    289	u32 app_mode;
    290	char   liquidio_firmware_version[32];
    291	/* Fields extracted from legacy string 'liquidio_firmware_version' */
    292	struct {
    293		u8  maj;
    294		u8  min;
    295		u8  rev;
    296	} ver;
    297};
    298
    299#define OCT_FW_VER(maj, min, rev) \
    300	(((u32)(maj) << 16) | ((u32)(min) << 8) | ((u32)(rev)))
    301
    302/* wrappers around work structs */
    303struct cavium_wk {
    304	struct delayed_work work;
    305	void *ctxptr;
    306	u64 ctxul;
    307};
    308
    309struct cavium_wq {
    310	struct workqueue_struct *wq;
    311	struct cavium_wk wk;
    312};
    313
    314struct octdev_props {
    315	/* Each interface in the Octeon device has a network
    316	 * device pointer (used for OS specific calls).
    317	 */
    318	int    rx_on;
    319	int    fec;
    320	int    fec_boot;
    321	int    napi_enabled;
    322	int    gmxport;
    323	struct net_device *netdev;
    324};
    325
    326#define LIO_FLAG_MSIX_ENABLED	0x1
    327#define MSIX_PO_INT		0x1
    328#define MSIX_PI_INT		0x2
    329#define MSIX_MBOX_INT		0x4
    330
    331struct octeon_pf_vf_hs_word {
    332#ifdef __LITTLE_ENDIAN_BITFIELD
    333	/** PKIND value assigned for the DPI interface */
    334	u64        pkind : 8;
    335
    336	/** OCTEON core clock multiplier   */
    337	u64        core_tics_per_us : 16;
    338
    339	/** OCTEON coprocessor clock multiplier  */
    340	u64        coproc_tics_per_us : 16;
    341
    342	/** app that currently running on OCTEON  */
    343	u64        app_mode : 8;
    344
    345	/** RESERVED */
    346	u64 reserved : 16;
    347
    348#else
    349
    350	/** RESERVED */
    351	u64 reserved : 16;
    352
    353	/** app that currently running on OCTEON  */
    354	u64        app_mode : 8;
    355
    356	/** OCTEON coprocessor clock multiplier  */
    357	u64        coproc_tics_per_us : 16;
    358
    359	/** OCTEON core clock multiplier   */
    360	u64        core_tics_per_us : 16;
    361
    362	/** PKIND value assigned for the DPI interface */
    363	u64        pkind : 8;
    364#endif
    365};
    366
    367struct octeon_sriov_info {
    368	/* Number of rings assigned to VF */
    369	u32	rings_per_vf;
    370
    371	/** Max Number of VF devices that can be enabled. This variable can
    372	 *  specified during load time or it will be derived after allocating
    373	 *  PF queues. When max_vfs is derived then each VF will get one queue
    374	 **/
    375	u32	max_vfs;
    376
    377	/** Number of VF devices enabled using sysfs. */
    378	u32	num_vfs_alloced;
    379
    380	/* Actual rings left for PF device */
    381	u32	num_pf_rings;
    382
    383	/* SRN of PF usable IO queues */
    384	u32	pf_srn;
    385
    386	/* total pf rings */
    387	u32	trs;
    388
    389	u32	sriov_enabled;
    390
    391	struct lio_trusted_vf	trusted_vf;
    392
    393	/*lookup table that maps DPI ring number to VF pci_dev struct pointer*/
    394	struct pci_dev *dpiring_to_vfpcidev_lut[MAX_POSSIBLE_VFS];
    395
    396	u64	vf_macaddr[MAX_POSSIBLE_VFS];
    397
    398	u16	vf_vlantci[MAX_POSSIBLE_VFS];
    399
    400	int	vf_linkstate[MAX_POSSIBLE_VFS];
    401
    402	bool    vf_spoofchk[MAX_POSSIBLE_VFS];
    403
    404	u64	vf_drv_loaded_mask;
    405};
    406
    407struct octeon_ioq_vector {
    408	struct octeon_device   *oct_dev;
    409	int		        iq_index;
    410	int		        droq_index;
    411	int			vector;
    412	struct octeon_mbox     *mbox;
    413	struct cpumask		affinity_mask;
    414	u32			ioq_num;
    415};
    416
    417struct lio_vf_rep_list {
    418	int num_vfs;
    419	struct net_device *ndev[CN23XX_MAX_VFS_PER_PF];
    420};
    421
    422struct lio_devlink_priv {
    423	struct octeon_device *oct;
    424};
    425
    426/** The Octeon device.
    427 *  Each Octeon device has this structure to represent all its
    428 *  components.
    429 */
    430struct octeon_device {
    431	/** Lock for PCI window configuration accesses */
    432	spinlock_t pci_win_lock;
    433
    434	/** Lock for memory accesses */
    435	spinlock_t mem_access_lock;
    436
    437	/** PCI device pointer */
    438	struct pci_dev *pci_dev;
    439
    440	/** Chip specific information. */
    441	void *chip;
    442
    443	/** Number of interfaces detected in this octeon device. */
    444	u32 ifcount;
    445
    446	struct octdev_props props[MAX_OCTEON_LINKS];
    447
    448	/** Octeon Chip type. */
    449	u16 chip_id;
    450
    451	u16 rev_id;
    452
    453	u32 subsystem_id;
    454
    455	u16 pf_num;
    456
    457	u16 vf_num;
    458
    459	/** This device's id - set by the driver. */
    460	u32 octeon_id;
    461
    462	/** This device's PCIe port used for traffic. */
    463	u16 pcie_port;
    464
    465	u16 flags;
    466#define LIO_FLAG_MSI_ENABLED                  (u32)(1 << 1)
    467
    468	/** The state of this device */
    469	atomic_t status;
    470
    471	/** memory mapped io range */
    472	struct octeon_mmio mmio[OCT_MEM_REGIONS];
    473
    474	struct octeon_reg_list reg_list;
    475
    476	struct octeon_fn_list fn_list;
    477
    478	struct octeon_board_info boardinfo;
    479
    480	u32 num_iqs;
    481
    482	/* The pool containing pre allocated buffers used for soft commands */
    483	struct octeon_sc_buffer_pool	sc_buf_pool;
    484
    485	/** The input instruction queues */
    486	struct octeon_instr_queue *instr_queue
    487		[MAX_POSSIBLE_OCTEON_INSTR_QUEUES];
    488
    489	/** The doubly-linked list of instruction response */
    490	struct octeon_response_list response_list[MAX_RESPONSE_LISTS];
    491
    492	u32 num_oqs;
    493
    494	/** The DROQ output queues  */
    495	struct octeon_droq *droq[MAX_POSSIBLE_OCTEON_OUTPUT_QUEUES];
    496
    497	struct octeon_io_enable io_qmask;
    498
    499	/** List of dispatch functions */
    500	struct octeon_dispatch_list dispatch;
    501
    502	u32 int_status;
    503
    504	u64 droq_intr;
    505
    506	/** Physical location of the cvmx_bootmem_desc_t in octeon memory */
    507	u64 bootmem_desc_addr;
    508
    509	/** Placeholder memory for named blocks.
    510	 * Assumes single-threaded access
    511	 */
    512	struct cvmx_bootmem_named_block_desc bootmem_named_block_desc;
    513
    514	/** Address of consoles descriptor */
    515	u64 console_desc_addr;
    516
    517	/** Number of consoles available. 0 means they are inaccessible */
    518	u32 num_consoles;
    519
    520	/* Console caches */
    521	struct octeon_console console[MAX_OCTEON_MAPS];
    522
    523	/* Console named block info */
    524	struct {
    525		u64 dram_region_base;
    526		int bar1_index;
    527	} console_nb_info;
    528
    529	/* Coprocessor clock rate. */
    530	u64 coproc_clock_rate;
    531
    532	/** The core application is running in this mode. See liquidio_common.h
    533	 * for values.
    534	 */
    535	u32 app_mode;
    536
    537	struct oct_fw_info fw_info;
    538
    539	/** The name given to this device. */
    540	char device_name[32];
    541
    542	/** Application Context */
    543	void *app_ctx;
    544
    545	struct cavium_wq dma_comp_wq;
    546
    547	/** Lock for dma response list */
    548	spinlock_t cmd_resp_wqlock;
    549	u32 cmd_resp_state;
    550
    551	struct cavium_wq check_db_wq[MAX_POSSIBLE_OCTEON_INSTR_QUEUES];
    552
    553	struct cavium_wk nic_poll_work;
    554
    555	struct cavium_wk console_poll_work[MAX_OCTEON_MAPS];
    556
    557	void *priv;
    558
    559	int num_msix_irqs;
    560
    561	void *msix_entries;
    562
    563	/* when requesting IRQs, the names are stored here */
    564	void *irq_name_storage;
    565
    566	struct octeon_sriov_info sriov_info;
    567
    568	struct octeon_pf_vf_hs_word pfvf_hsword;
    569
    570	int msix_on;
    571
    572	/** Mail Box details of each octeon queue. */
    573	struct octeon_mbox  *mbox[MAX_POSSIBLE_VFS];
    574
    575	/** IOq information of it's corresponding MSI-X interrupt. */
    576	struct octeon_ioq_vector    *ioq_vector;
    577
    578	int rx_pause;
    579	int tx_pause;
    580
    581	struct oct_link_stats link_stats; /*stastics from firmware*/
    582
    583	/* private flags to control driver-specific features through ethtool */
    584	u32 priv_flags;
    585
    586	void *watchdog_task;
    587
    588	u32 rx_coalesce_usecs;
    589	u32 rx_max_coalesced_frames;
    590	u32 tx_max_coalesced_frames;
    591
    592	bool cores_crashed;
    593
    594	struct {
    595		int bus;
    596		int dev;
    597		int func;
    598	} loc;
    599
    600	atomic_t *adapter_refcount; /* reference count of adapter */
    601
    602	atomic_t *adapter_fw_state; /* per-adapter, lio_fw_state */
    603
    604	bool ptp_enable;
    605
    606	struct lio_vf_rep_list vf_rep_list;
    607	struct devlink *devlink;
    608	enum devlink_eswitch_mode eswitch_mode;
    609
    610	/* for 25G NIC speed change */
    611	u8  speed_boot;
    612	u8  speed_setting;
    613	u8  no_speed_setting;
    614
    615	u32    vfstats_poll;
    616#define LIO_VFSTATS_POLL 10
    617};
    618
    619#define  OCT_DRV_ONLINE 1
    620#define  OCT_DRV_OFFLINE 2
    621#define  OCTEON_CN6XXX(oct)	({					\
    622				 typeof(oct) _oct = (oct);		\
    623				 ((_oct->chip_id == OCTEON_CN66XX) ||	\
    624				  (_oct->chip_id == OCTEON_CN68XX));	})
    625#define  OCTEON_CN23XX_PF(oct)        ((oct)->chip_id == OCTEON_CN23XX_PF_VID)
    626#define  OCTEON_CN23XX_VF(oct)        ((oct)->chip_id == OCTEON_CN23XX_VF_VID)
    627#define CHIP_CONF(oct, TYPE)             \
    628	(((struct octeon_ ## TYPE  *)((oct)->chip))->conf)
    629
    630#define MAX_IO_PENDING_PKT_COUNT 100
    631
    632/*------------------ Function Prototypes ----------------------*/
    633
    634/** Initialize device list memory */
    635void octeon_init_device_list(int conf_type);
    636
    637/** Free memory for Input and Output queue structures for a octeon device */
    638void octeon_free_device_mem(struct octeon_device *oct);
    639
    640/* Look up a free entry in the octeon_device table and allocate resources
    641 * for the octeon_device structure for an octeon device. Called at init
    642 * time.
    643 */
    644struct octeon_device *octeon_allocate_device(u32 pci_id,
    645					     u32 priv_size);
    646
    647/** Register a device's bus location at initialization time.
    648 *  @param octeon_dev - pointer to the octeon device structure.
    649 *  @param bus        - PCIe bus #
    650 *  @param dev        - PCIe device #
    651 *  @param func       - PCIe function #
    652 *  @param is_pf      - TRUE for PF, FALSE for VF
    653 *  @return reference count of device's adapter
    654 */
    655int octeon_register_device(struct octeon_device *oct,
    656			   int bus, int dev, int func, int is_pf);
    657
    658/** Deregister a device at de-initialization time.
    659 *  @param octeon_dev - pointer to the octeon device structure.
    660 *  @return reference count of device's adapter
    661 */
    662int octeon_deregister_device(struct octeon_device *oct);
    663
    664/**  Initialize the driver's dispatch list which is a mix of a hash table
    665 *  and a linked list. This is done at driver load time.
    666 *  @param octeon_dev - pointer to the octeon device structure.
    667 *  @return 0 on success, else -ve error value
    668 */
    669int octeon_init_dispatch_list(struct octeon_device *octeon_dev);
    670
    671/**  Delete the driver's dispatch list and all registered entries.
    672 * This is done at driver unload time.
    673 *  @param octeon_dev - pointer to the octeon device structure.
    674 */
    675void octeon_delete_dispatch_list(struct octeon_device *octeon_dev);
    676
    677/** Initialize the core device fields with the info returned by the FW.
    678 * @param recv_info - Receive info structure
    679 * @param buf       - Receive buffer
    680 */
    681int octeon_core_drv_init(struct octeon_recv_info *recv_info, void *buf);
    682
    683/** Gets the dispatch function registered to receive packets with a
    684 *  given opcode/subcode.
    685 *  @param  octeon_dev  - the octeon device pointer.
    686 *  @param  opcode      - the opcode for which the dispatch function
    687 *                        is to checked.
    688 *  @param  subcode     - the subcode for which the dispatch function
    689 *                        is to checked.
    690 *
    691 *  @return Success: octeon_dispatch_fn_t (dispatch function pointer)
    692 *  @return Failure: NULL
    693 *
    694 *  Looks up the dispatch list to get the dispatch function for a
    695 *  given opcode.
    696 */
    697octeon_dispatch_fn_t
    698octeon_get_dispatch(struct octeon_device *octeon_dev, u16 opcode,
    699		    u16 subcode);
    700
    701/** Get the octeon device pointer.
    702 *  @param octeon_id  - The id for which the octeon device pointer is required.
    703 *  @return Success: Octeon device pointer.
    704 *  @return Failure: NULL.
    705 */
    706struct octeon_device *lio_get_device(u32 octeon_id);
    707
    708/** Get the octeon id assigned to the octeon device passed as argument.
    709 *  This function is exported to other modules.
    710 *  @param dev - octeon device pointer passed as a void *.
    711 *  @return octeon device id
    712 */
    713int lio_get_device_id(void *dev);
    714
    715/** Read windowed register.
    716 *  @param  oct   -  pointer to the Octeon device.
    717 *  @param  addr  -  Address of the register to read.
    718 *
    719 *  This routine is called to read from the indirectly accessed
    720 *  Octeon registers that are visible through a PCI BAR0 mapped window
    721 *  register.
    722 *  @return  - 64 bit value read from the register.
    723 */
    724
    725u64 lio_pci_readq(struct octeon_device *oct, u64 addr);
    726
    727/** Write windowed register.
    728 *  @param  oct  -  pointer to the Octeon device.
    729 *  @param  val  -  Value to write
    730 *  @param  addr -  Address of the register to write
    731 *
    732 *  This routine is called to write to the indirectly accessed
    733 *  Octeon registers that are visible through a PCI BAR0 mapped window
    734 *  register.
    735 *  @return   Nothing.
    736 */
    737void lio_pci_writeq(struct octeon_device *oct, u64 val, u64 addr);
    738
    739/* Routines for reading and writing CSRs */
    740#define   octeon_write_csr(oct_dev, reg_off, value) \
    741		writel(value, (oct_dev)->mmio[0].hw_addr + (reg_off))
    742
    743#define   octeon_write_csr64(oct_dev, reg_off, val64) \
    744		writeq(val64, (oct_dev)->mmio[0].hw_addr + (reg_off))
    745
    746#define   octeon_read_csr(oct_dev, reg_off)         \
    747		readl((oct_dev)->mmio[0].hw_addr + (reg_off))
    748
    749#define   octeon_read_csr64(oct_dev, reg_off)         \
    750		readq((oct_dev)->mmio[0].hw_addr + (reg_off))
    751
    752/**
    753 * Checks if memory access is okay
    754 *
    755 * @param oct which octeon to send to
    756 * @return Zero on success, negative on failure.
    757 */
    758int octeon_mem_access_ok(struct octeon_device *oct);
    759
    760/**
    761 * Waits for DDR initialization.
    762 *
    763 * @param oct which octeon to send to
    764 * @param timeout_in_ms pointer to how long to wait until DDR is initialized
    765 * in ms.
    766 *                      If contents are 0, it waits until contents are non-zero
    767 *                      before starting to check.
    768 * @return Zero on success, negative on failure.
    769 */
    770int octeon_wait_for_ddr_init(struct octeon_device *oct,
    771			     u32 *timeout_in_ms);
    772
    773/**
    774 * Wait for u-boot to boot and be waiting for a command.
    775 *
    776 * @param wait_time_hundredths
    777 *               Maximum time to wait
    778 *
    779 * @return Zero on success, negative on failure.
    780 */
    781int octeon_wait_for_bootloader(struct octeon_device *oct,
    782			       u32 wait_time_hundredths);
    783
    784/**
    785 * Initialize console access
    786 *
    787 * @param oct which octeon initialize
    788 * @return Zero on success, negative on failure.
    789 */
    790int octeon_init_consoles(struct octeon_device *oct);
    791
    792/**
    793 * Adds access to a console to the device.
    794 *
    795 * @param oct:          which octeon to add to
    796 * @param console_num:  which console
    797 * @param dbg_enb:      ptr to debug enablement string, one of:
    798 *                    * NULL for no debug output (i.e. disabled)
    799 *                    * empty string enables debug output (via default method)
    800 *                    * specific string to enable debug console output
    801 *
    802 * @return Zero on success, negative on failure.
    803 */
    804int octeon_add_console(struct octeon_device *oct, u32 console_num,
    805		       char *dbg_enb);
    806
    807/** write or read from a console */
    808int octeon_console_write(struct octeon_device *oct, u32 console_num,
    809			 char *buffer, u32 write_request_size, u32 flags);
    810int octeon_console_write_avail(struct octeon_device *oct, u32 console_num);
    811
    812int octeon_console_read_avail(struct octeon_device *oct, u32 console_num);
    813
    814/** Removes all attached consoles. */
    815void octeon_remove_consoles(struct octeon_device *oct);
    816
    817/**
    818 * Send a string to u-boot on console 0 as a command.
    819 *
    820 * @param oct which octeon to send to
    821 * @param cmd_str String to send
    822 * @param wait_hundredths Time to wait for u-boot to accept the command.
    823 *
    824 * @return Zero on success, negative on failure.
    825 */
    826int octeon_console_send_cmd(struct octeon_device *oct, char *cmd_str,
    827			    u32 wait_hundredths);
    828
    829/** Parses, validates, and downloads firmware, then boots associated cores.
    830 *  @param oct which octeon to download firmware to
    831 *  @param data  - The complete firmware file image
    832 *  @param size  - The size of the data
    833 *
    834 *  @return 0 if success.
    835 *         -EINVAL if file is incompatible or badly formatted.
    836 *         -ENODEV if no handler was found for the application type or an
    837 *         invalid octeon id was passed.
    838 */
    839int octeon_download_firmware(struct octeon_device *oct, const u8 *data,
    840			     size_t size);
    841
    842char *lio_get_state_string(atomic_t *state_ptr);
    843
    844/** Sets up instruction queues for the device
    845 *  @param oct which octeon to setup
    846 *
    847 *  @return 0 if success. 1 if fails
    848 */
    849int octeon_setup_instr_queues(struct octeon_device *oct);
    850
    851/** Sets up output queues for the device
    852 *  @param oct which octeon to setup
    853 *
    854 *  @return 0 if success. 1 if fails
    855 */
    856int octeon_setup_output_queues(struct octeon_device *oct);
    857
    858int octeon_get_tx_qsize(struct octeon_device *oct, u32 q_no);
    859
    860int octeon_get_rx_qsize(struct octeon_device *oct, u32 q_no);
    861
    862/** Turns off the input and output queues for the device
    863 *  @param oct which octeon to disable
    864 */
    865int octeon_set_io_queues_off(struct octeon_device *oct);
    866
    867/** Turns on or off the given output queue for the device
    868 *  @param oct which octeon to change
    869 *  @param q_no which queue
    870 *  @param enable 1 to enable, 0 to disable
    871 */
    872void octeon_set_droq_pkt_op(struct octeon_device *oct, u32 q_no, u32 enable);
    873
    874/** Retrieve the config for the device
    875 *  @param oct which octeon
    876 *  @param card_type type of card
    877 *
    878 *  @returns pointer to configuration
    879 */
    880void *oct_get_config_info(struct octeon_device *oct, u16 card_type);
    881
    882/** Gets the octeon device configuration
    883 *  @return - pointer to the octeon configuration struture
    884 */
    885struct octeon_config *octeon_get_conf(struct octeon_device *oct);
    886
    887void octeon_free_ioq_vector(struct octeon_device *oct);
    888int octeon_allocate_ioq_vector(struct octeon_device  *oct, u32 num_ioqs);
    889void lio_enable_irq(struct octeon_droq *droq, struct octeon_instr_queue *iq);
    890
    891/* LiquidIO driver pivate flags */
    892enum {
    893	OCT_PRIV_FLAG_TX_BYTES = 0, /* Tx interrupts by pending byte count */
    894};
    895
    896#define OCT_PRIV_FLAG_DEFAULT 0x0
    897
    898static inline u32 lio_get_priv_flag(struct octeon_device *octdev, u32 flag)
    899{
    900	return !!(octdev->priv_flags & (0x1 << flag));
    901}
    902
    903static inline void lio_set_priv_flag(struct octeon_device *octdev,
    904				     u32 flag, u32 val)
    905{
    906	if (val)
    907		octdev->priv_flags |= (0x1 << flag);
    908	else
    909		octdev->priv_flags &= ~(0x1 << flag);
    910}
    911#endif