cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

common.h (10955B)


      1/*****************************************************************************
      2 *                                                                           *
      3 * File: common.h                                                            *
      4 * $Revision: 1.21 $                                                         *
      5 * $Date: 2005/06/22 00:43:25 $                                              *
      6 * Description:                                                              *
      7 *  part of the Chelsio 10Gb Ethernet Driver.                                *
      8 *                                                                           *
      9 * This program is free software; you can redistribute it and/or modify      *
     10 * it under the terms of the GNU General Public License, version 2, as       *
     11 * published by the Free Software Foundation.                                *
     12 *                                                                           *
     13 * You should have received a copy of the GNU General Public License along   *
     14 * with this program; if not, see <http://www.gnu.org/licenses/>.            *
     15 *                                                                           *
     16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED    *
     17 * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF      *
     18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.                     *
     19 *                                                                           *
     20 * http://www.chelsio.com                                                    *
     21 *                                                                           *
     22 * Copyright (c) 2003 - 2005 Chelsio Communications, Inc.                    *
     23 * All rights reserved.                                                      *
     24 *                                                                           *
     25 * Maintainers: maintainers@chelsio.com                                      *
     26 *                                                                           *
     27 * Authors: Dimitrios Michailidis   <dm@chelsio.com>                         *
     28 *          Tina Yang               <tainay@chelsio.com>                     *
     29 *          Felix Marti             <felix@chelsio.com>                      *
     30 *          Scott Bardone           <sbardone@chelsio.com>                   *
     31 *          Kurt Ottaway            <kottaway@chelsio.com>                   *
     32 *          Frank DiMambro          <frank@chelsio.com>                      *
     33 *                                                                           *
     34 * History:                                                                  *
     35 *                                                                           *
     36 ****************************************************************************/
     37
     38#define pr_fmt(fmt) "cxgb: " fmt
     39
     40#ifndef _CXGB_COMMON_H_
     41#define _CXGB_COMMON_H_
     42
     43#include <linux/module.h>
     44#include <linux/netdevice.h>
     45#include <linux/types.h>
     46#include <linux/delay.h>
     47#include <linux/pci.h>
     48#include <linux/ethtool.h>
     49#include <linux/if_vlan.h>
     50#include <linux/mdio.h>
     51#include <linux/crc32.h>
     52#include <linux/slab.h>
     53#include <asm/io.h>
     54#include <linux/pci_ids.h>
     55
     56#define DRV_DESCRIPTION "Chelsio 10Gb Ethernet Driver"
     57#define DRV_NAME "cxgb"
     58
     59#define CH_DEVICE(devid, ssid, idx) \
     60	{ PCI_VENDOR_ID_CHELSIO, devid, PCI_ANY_ID, ssid, 0, 0, idx }
     61
     62#define SUPPORTED_PAUSE       (1 << 13)
     63#define SUPPORTED_LOOPBACK    (1 << 15)
     64
     65#define ADVERTISED_PAUSE      (1 << 13)
     66#define ADVERTISED_ASYM_PAUSE (1 << 14)
     67
     68typedef struct adapter adapter_t;
     69
     70struct t1_rx_mode {
     71       struct net_device *dev;
     72};
     73
     74#define t1_rx_mode_promisc(rm)	(rm->dev->flags & IFF_PROMISC)
     75#define t1_rx_mode_allmulti(rm)	(rm->dev->flags & IFF_ALLMULTI)
     76#define t1_rx_mode_mc_cnt(rm)	(netdev_mc_count(rm->dev))
     77#define t1_get_netdev(rm)	(rm->dev)
     78
     79#define	MAX_NPORTS 4
     80#define PORT_MASK ((1 << MAX_NPORTS) - 1)
     81#define NMTUS      8
     82#define TCB_SIZE   128
     83
     84#define SPEED_INVALID 0xffff
     85#define DUPLEX_INVALID 0xff
     86
     87/* Max frame size PM3393 can handle. Includes Ethernet header and CRC. */
     88#define PM3393_MAX_FRAME_SIZE 9600
     89
     90#define VSC7326_MAX_MTU 9600
     91
     92enum {
     93	CHBT_BOARD_N110,
     94	CHBT_BOARD_N210,
     95	CHBT_BOARD_7500,
     96	CHBT_BOARD_8000,
     97	CHBT_BOARD_CHT101,
     98	CHBT_BOARD_CHT110,
     99	CHBT_BOARD_CHT210,
    100	CHBT_BOARD_CHT204,
    101	CHBT_BOARD_CHT204V,
    102	CHBT_BOARD_CHT204E,
    103	CHBT_BOARD_CHN204,
    104	CHBT_BOARD_COUGAR,
    105	CHBT_BOARD_6800,
    106	CHBT_BOARD_SIMUL,
    107};
    108
    109enum {
    110	CHBT_TERM_FPGA,
    111	CHBT_TERM_T1,
    112	CHBT_TERM_T2,
    113	CHBT_TERM_T3
    114};
    115
    116enum {
    117	CHBT_MAC_CHELSIO_A,
    118	CHBT_MAC_IXF1010,
    119	CHBT_MAC_PM3393,
    120	CHBT_MAC_VSC7321,
    121	CHBT_MAC_DUMMY
    122};
    123
    124enum {
    125	CHBT_PHY_88E1041,
    126	CHBT_PHY_88E1111,
    127	CHBT_PHY_88X2010,
    128	CHBT_PHY_XPAK,
    129	CHBT_PHY_MY3126,
    130	CHBT_PHY_8244,
    131	CHBT_PHY_DUMMY
    132};
    133
    134enum {
    135	PAUSE_RX      = 1 << 0,
    136	PAUSE_TX      = 1 << 1,
    137	PAUSE_AUTONEG = 1 << 2
    138};
    139
    140/* Revisions of T1 chip */
    141enum {
    142	TERM_T1A   = 0,
    143	TERM_T1B   = 1,
    144	TERM_T2    = 3
    145};
    146
    147struct sge_params {
    148	unsigned int cmdQ_size[2];
    149	unsigned int freelQ_size[2];
    150	unsigned int large_buf_capacity;
    151	unsigned int rx_coalesce_usecs;
    152	unsigned int last_rx_coalesce_raw;
    153	unsigned int default_rx_coalesce_usecs;
    154	unsigned int sample_interval_usecs;
    155	unsigned int coalesce_enable;
    156	unsigned int polling;
    157};
    158
    159struct chelsio_pci_params {
    160	unsigned short speed;
    161	unsigned char  width;
    162	unsigned char  is_pcix;
    163};
    164
    165struct tp_params {
    166	unsigned int pm_size;
    167	unsigned int cm_size;
    168	unsigned int pm_rx_base;
    169	unsigned int pm_tx_base;
    170	unsigned int pm_rx_pg_size;
    171	unsigned int pm_tx_pg_size;
    172	unsigned int pm_rx_num_pgs;
    173	unsigned int pm_tx_num_pgs;
    174	unsigned int rx_coalescing_size;
    175	unsigned int use_5tuple_mode;
    176};
    177
    178struct mc5_params {
    179	unsigned int mode;       /* selects MC5 width */
    180	unsigned int nservers;   /* size of server region */
    181	unsigned int nroutes;    /* size of routing region */
    182};
    183
    184/* Default MC5 region sizes */
    185#define DEFAULT_SERVER_REGION_LEN 256
    186#define DEFAULT_RT_REGION_LEN 1024
    187
    188struct adapter_params {
    189	struct sge_params sge;
    190	struct mc5_params mc5;
    191	struct tp_params  tp;
    192	struct chelsio_pci_params pci;
    193
    194	const struct board_info *brd_info;
    195
    196	unsigned short mtus[NMTUS];
    197	unsigned int   nports;          /* # of ethernet ports */
    198	unsigned int   stats_update_period;
    199	unsigned short chip_revision;
    200	unsigned char  chip_version;
    201	unsigned char  is_asic;
    202	unsigned char  has_msi;
    203};
    204
    205struct link_config {
    206	unsigned int   supported;        /* link capabilities */
    207	unsigned int   advertising;      /* advertised capabilities */
    208	unsigned short requested_speed;  /* speed user has requested */
    209	unsigned short speed;            /* actual link speed */
    210	unsigned char  requested_duplex; /* duplex user has requested */
    211	unsigned char  duplex;           /* actual link duplex */
    212	unsigned char  requested_fc;     /* flow control user has requested */
    213	unsigned char  fc;               /* actual link flow control */
    214	unsigned char  autoneg;          /* autonegotiating? */
    215};
    216
    217struct cmac;
    218struct cphy;
    219
    220struct port_info {
    221	struct net_device *dev;
    222	struct cmac *mac;
    223	struct cphy *phy;
    224	struct link_config link_config;
    225};
    226
    227struct sge;
    228struct peespi;
    229
    230struct adapter {
    231	u8 __iomem *regs;
    232	struct pci_dev *pdev;
    233	unsigned long registered_device_map;
    234	unsigned long open_device_map;
    235	unsigned long flags;
    236
    237	const char *name;
    238	int msg_enable;
    239	u32 mmio_len;
    240
    241	struct adapter_params params;
    242
    243	/* Terminator modules. */
    244	struct sge    *sge;
    245	struct peespi *espi;
    246	struct petp   *tp;
    247
    248	struct napi_struct napi;
    249	struct port_info port[MAX_NPORTS];
    250	struct delayed_work stats_update_task;
    251	struct timer_list stats_update_timer;
    252
    253	spinlock_t tpi_lock;
    254	spinlock_t work_lock;
    255	spinlock_t mac_lock;
    256
    257	/* guards async operations */
    258	spinlock_t async_lock ____cacheline_aligned;
    259	u32 pending_thread_intr;
    260	u32 slow_intr_mask;
    261	int t1powersave;
    262};
    263
    264enum {                                           /* adapter flags */
    265	FULL_INIT_DONE        = 1 << 0,
    266};
    267
    268struct mdio_ops;
    269struct gmac;
    270struct gphy;
    271
    272struct board_info {
    273	unsigned char           board;
    274	unsigned char           port_number;
    275	unsigned long           caps;
    276	unsigned char           chip_term;
    277	unsigned char           chip_mac;
    278	unsigned char           chip_phy;
    279	unsigned int            clock_core;
    280	unsigned int            clock_mc3;
    281	unsigned int            clock_mc4;
    282	unsigned int            espi_nports;
    283	unsigned int            clock_elmer0;
    284	unsigned char           mdio_mdien;
    285	unsigned char           mdio_mdiinv;
    286	unsigned char           mdio_mdc;
    287	unsigned char           mdio_phybaseaddr;
    288	const struct gmac      *gmac;
    289	const struct gphy      *gphy;
    290	const struct mdio_ops  *mdio_ops;
    291	const char             *desc;
    292};
    293
    294static inline int t1_is_asic(const adapter_t *adapter)
    295{
    296	return adapter->params.is_asic;
    297}
    298
    299extern const struct pci_device_id t1_pci_tbl[];
    300
    301static inline int adapter_matches_type(const adapter_t *adapter,
    302				       int version, int revision)
    303{
    304	return adapter->params.chip_version == version &&
    305	       adapter->params.chip_revision == revision;
    306}
    307
    308#define t1_is_T1B(adap) adapter_matches_type(adap, CHBT_TERM_T1, TERM_T1B)
    309#define is_T2(adap)     adapter_matches_type(adap, CHBT_TERM_T2, TERM_T2)
    310
    311/* Returns true if an adapter supports VLAN acceleration and TSO */
    312static inline int vlan_tso_capable(const adapter_t *adapter)
    313{
    314	return !t1_is_T1B(adapter);
    315}
    316
    317#define for_each_port(adapter, iter) \
    318	for (iter = 0; iter < (adapter)->params.nports; ++iter)
    319
    320#define board_info(adapter) ((adapter)->params.brd_info)
    321#define is_10G(adapter) (board_info(adapter)->caps & SUPPORTED_10000baseT_Full)
    322
    323static inline unsigned int core_ticks_per_usec(const adapter_t *adap)
    324{
    325	return board_info(adap)->clock_core / 1000000;
    326}
    327
    328int __t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp);
    329int __t1_tpi_write(adapter_t *adapter, u32 addr, u32 value);
    330int t1_tpi_write(adapter_t *adapter, u32 addr, u32 value);
    331int t1_tpi_read(adapter_t *adapter, u32 addr, u32 *value);
    332
    333void t1_interrupts_enable(adapter_t *adapter);
    334void t1_interrupts_disable(adapter_t *adapter);
    335void t1_interrupts_clear(adapter_t *adapter);
    336int t1_elmer0_ext_intr_handler(adapter_t *adapter);
    337irqreturn_t t1_slow_intr_handler(adapter_t *adapter);
    338
    339int t1_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc);
    340const struct board_info *t1_get_board_info(unsigned int board_id);
    341const struct board_info *t1_get_board_info_from_ids(unsigned int devid,
    342						    unsigned short ssid);
    343int t1_seeprom_read(adapter_t *adapter, u32 addr, __le32 *data);
    344int t1_get_board_rev(adapter_t *adapter, const struct board_info *bi,
    345		     struct adapter_params *p);
    346int t1_init_hw_modules(adapter_t *adapter);
    347int t1_init_sw_modules(adapter_t *adapter, const struct board_info *bi);
    348void t1_free_sw_modules(adapter_t *adapter);
    349void t1_link_changed(adapter_t *adapter, int port_id);
    350void t1_link_negotiated(adapter_t *adapter, int port_id, int link_stat,
    351			    int speed, int duplex, int pause);
    352#endif /* _CXGB_COMMON_H_ */