fpga_defs.h (8083B)
1/* SPDX-License-Identifier: GPL-2.0 */ 2/* $Date: 2005/03/07 23:59:05 $ $RCSfile: fpga_defs.h,v $ $Revision: 1.4 $ */ 3 4/* 5 * FPGA specific definitions 6 */ 7 8#ifndef __CHELSIO_FPGA_DEFS_H__ 9#define __CHELSIO_FPGA_DEFS_H__ 10 11#define FPGA_PCIX_ADDR_VERSION 0xA08 12#define FPGA_PCIX_ADDR_STAT 0xA0C 13 14/* FPGA master interrupt Cause/Enable bits */ 15#define FPGA_PCIX_INTERRUPT_SGE_ERROR 0x1 16#define FPGA_PCIX_INTERRUPT_SGE_DATA 0x2 17#define FPGA_PCIX_INTERRUPT_TP 0x4 18#define FPGA_PCIX_INTERRUPT_MC3 0x8 19#define FPGA_PCIX_INTERRUPT_GMAC 0x10 20#define FPGA_PCIX_INTERRUPT_PCIX 0x20 21 22/* TP interrupt register addresses */ 23#define FPGA_TP_ADDR_INTERRUPT_ENABLE 0xA10 24#define FPGA_TP_ADDR_INTERRUPT_CAUSE 0xA14 25#define FPGA_TP_ADDR_VERSION 0xA18 26 27/* TP interrupt Cause/Enable bits */ 28#define FPGA_TP_INTERRUPT_MC4 0x1 29#define FPGA_TP_INTERRUPT_MC5 0x2 30 31/* 32 * PM interrupt register addresses 33 */ 34#define FPGA_MC3_REG_INTRENABLE 0xA20 35#define FPGA_MC3_REG_INTRCAUSE 0xA24 36#define FPGA_MC3_REG_VERSION 0xA28 37 38/* 39 * GMAC interrupt register addresses 40 */ 41#define FPGA_GMAC_ADDR_INTERRUPT_ENABLE 0xA30 42#define FPGA_GMAC_ADDR_INTERRUPT_CAUSE 0xA34 43#define FPGA_GMAC_ADDR_VERSION 0xA38 44 45/* GMAC Cause/Enable bits */ 46#define FPGA_GMAC_INTERRUPT_PORT0 0x1 47#define FPGA_GMAC_INTERRUPT_PORT1 0x2 48#define FPGA_GMAC_INTERRUPT_PORT2 0x4 49#define FPGA_GMAC_INTERRUPT_PORT3 0x8 50 51/* MI0 registers */ 52#define A_MI0_CLK 0xb00 53 54#define S_MI0_CLK_DIV 0 55#define M_MI0_CLK_DIV 0xff 56#define V_MI0_CLK_DIV(x) ((x) << S_MI0_CLK_DIV) 57#define G_MI0_CLK_DIV(x) (((x) >> S_MI0_CLK_DIV) & M_MI0_CLK_DIV) 58 59#define S_MI0_CLK_CNT 8 60#define M_MI0_CLK_CNT 0xff 61#define V_MI0_CLK_CNT(x) ((x) << S_MI0_CLK_CNT) 62#define G_MI0_CLK_CNT(x) (((x) >> S_MI0_CLK_CNT) & M_MI0_CLK_CNT) 63 64#define A_MI0_CSR 0xb04 65 66#define S_MI0_CSR_POLL 0 67#define V_MI0_CSR_POLL(x) ((x) << S_MI0_CSR_POLL) 68#define F_MI0_CSR_POLL V_MI0_CSR_POLL(1U) 69 70#define S_MI0_PREAMBLE 1 71#define V_MI0_PREAMBLE(x) ((x) << S_MI0_PREAMBLE) 72#define F_MI0_PREAMBLE V_MI0_PREAMBLE(1U) 73 74#define S_MI0_INTR_ENABLE 2 75#define V_MI0_INTR_ENABLE(x) ((x) << S_MI0_INTR_ENABLE) 76#define F_MI0_INTR_ENABLE V_MI0_INTR_ENABLE(1U) 77 78#define S_MI0_BUSY 3 79#define V_MI0_BUSY(x) ((x) << S_MI0_BUSY) 80#define F_MI0_BUSY V_MI0_BUSY(1U) 81 82#define S_MI0_MDIO 4 83#define V_MI0_MDIO(x) ((x) << S_MI0_MDIO) 84#define F_MI0_MDIO V_MI0_MDIO(1U) 85 86#define A_MI0_ADDR 0xb08 87 88#define S_MI0_PHY_REG_ADDR 0 89#define M_MI0_PHY_REG_ADDR 0x1f 90#define V_MI0_PHY_REG_ADDR(x) ((x) << S_MI0_PHY_REG_ADDR) 91#define G_MI0_PHY_REG_ADDR(x) (((x) >> S_MI0_PHY_REG_ADDR) & M_MI0_PHY_REG_ADDR) 92 93#define S_MI0_PHY_ADDR 5 94#define M_MI0_PHY_ADDR 0x1f 95#define V_MI0_PHY_ADDR(x) ((x) << S_MI0_PHY_ADDR) 96#define G_MI0_PHY_ADDR(x) (((x) >> S_MI0_PHY_ADDR) & M_MI0_PHY_ADDR) 97 98#define A_MI0_DATA_EXT 0xb0c 99#define A_MI0_DATA_INT 0xb10 100 101/* GMAC registers */ 102#define A_GMAC_MACID_LO 0x28 103#define A_GMAC_MACID_HI 0x2c 104#define A_GMAC_CSR 0x30 105 106#define S_INTERFACE 0 107#define M_INTERFACE 0x3 108#define V_INTERFACE(x) ((x) << S_INTERFACE) 109#define G_INTERFACE(x) (((x) >> S_INTERFACE) & M_INTERFACE) 110 111#define S_MAC_TX_ENABLE 2 112#define V_MAC_TX_ENABLE(x) ((x) << S_MAC_TX_ENABLE) 113#define F_MAC_TX_ENABLE V_MAC_TX_ENABLE(1U) 114 115#define S_MAC_RX_ENABLE 3 116#define V_MAC_RX_ENABLE(x) ((x) << S_MAC_RX_ENABLE) 117#define F_MAC_RX_ENABLE V_MAC_RX_ENABLE(1U) 118 119#define S_MAC_LB_ENABLE 4 120#define V_MAC_LB_ENABLE(x) ((x) << S_MAC_LB_ENABLE) 121#define F_MAC_LB_ENABLE V_MAC_LB_ENABLE(1U) 122 123#define S_MAC_SPEED 5 124#define M_MAC_SPEED 0x3 125#define V_MAC_SPEED(x) ((x) << S_MAC_SPEED) 126#define G_MAC_SPEED(x) (((x) >> S_MAC_SPEED) & M_MAC_SPEED) 127 128#define S_MAC_HD_FC_ENABLE 7 129#define V_MAC_HD_FC_ENABLE(x) ((x) << S_MAC_HD_FC_ENABLE) 130#define F_MAC_HD_FC_ENABLE V_MAC_HD_FC_ENABLE(1U) 131 132#define S_MAC_HALF_DUPLEX 8 133#define V_MAC_HALF_DUPLEX(x) ((x) << S_MAC_HALF_DUPLEX) 134#define F_MAC_HALF_DUPLEX V_MAC_HALF_DUPLEX(1U) 135 136#define S_MAC_PROMISC 9 137#define V_MAC_PROMISC(x) ((x) << S_MAC_PROMISC) 138#define F_MAC_PROMISC V_MAC_PROMISC(1U) 139 140#define S_MAC_MC_ENABLE 10 141#define V_MAC_MC_ENABLE(x) ((x) << S_MAC_MC_ENABLE) 142#define F_MAC_MC_ENABLE V_MAC_MC_ENABLE(1U) 143 144#define S_MAC_RESET 11 145#define V_MAC_RESET(x) ((x) << S_MAC_RESET) 146#define F_MAC_RESET V_MAC_RESET(1U) 147 148#define S_MAC_RX_PAUSE_ENABLE 12 149#define V_MAC_RX_PAUSE_ENABLE(x) ((x) << S_MAC_RX_PAUSE_ENABLE) 150#define F_MAC_RX_PAUSE_ENABLE V_MAC_RX_PAUSE_ENABLE(1U) 151 152#define S_MAC_TX_PAUSE_ENABLE 13 153#define V_MAC_TX_PAUSE_ENABLE(x) ((x) << S_MAC_TX_PAUSE_ENABLE) 154#define F_MAC_TX_PAUSE_ENABLE V_MAC_TX_PAUSE_ENABLE(1U) 155 156#define S_MAC_LWM_ENABLE 14 157#define V_MAC_LWM_ENABLE(x) ((x) << S_MAC_LWM_ENABLE) 158#define F_MAC_LWM_ENABLE V_MAC_LWM_ENABLE(1U) 159 160#define S_MAC_MAGIC_PKT_ENABLE 15 161#define V_MAC_MAGIC_PKT_ENABLE(x) ((x) << S_MAC_MAGIC_PKT_ENABLE) 162#define F_MAC_MAGIC_PKT_ENABLE V_MAC_MAGIC_PKT_ENABLE(1U) 163 164#define S_MAC_ISL_ENABLE 16 165#define V_MAC_ISL_ENABLE(x) ((x) << S_MAC_ISL_ENABLE) 166#define F_MAC_ISL_ENABLE V_MAC_ISL_ENABLE(1U) 167 168#define S_MAC_JUMBO_ENABLE 17 169#define V_MAC_JUMBO_ENABLE(x) ((x) << S_MAC_JUMBO_ENABLE) 170#define F_MAC_JUMBO_ENABLE V_MAC_JUMBO_ENABLE(1U) 171 172#define S_MAC_RX_PAD_ENABLE 18 173#define V_MAC_RX_PAD_ENABLE(x) ((x) << S_MAC_RX_PAD_ENABLE) 174#define F_MAC_RX_PAD_ENABLE V_MAC_RX_PAD_ENABLE(1U) 175 176#define S_MAC_RX_CRC_ENABLE 19 177#define V_MAC_RX_CRC_ENABLE(x) ((x) << S_MAC_RX_CRC_ENABLE) 178#define F_MAC_RX_CRC_ENABLE V_MAC_RX_CRC_ENABLE(1U) 179 180#define A_GMAC_IFS 0x34 181 182#define S_MAC_IFS2 0 183#define M_MAC_IFS2 0x3f 184#define V_MAC_IFS2(x) ((x) << S_MAC_IFS2) 185#define G_MAC_IFS2(x) (((x) >> S_MAC_IFS2) & M_MAC_IFS2) 186 187#define S_MAC_IFS1 8 188#define M_MAC_IFS1 0x7f 189#define V_MAC_IFS1(x) ((x) << S_MAC_IFS1) 190#define G_MAC_IFS1(x) (((x) >> S_MAC_IFS1) & M_MAC_IFS1) 191 192#define A_GMAC_JUMBO_FRAME_LEN 0x38 193#define A_GMAC_LNK_DLY 0x3c 194#define A_GMAC_PAUSETIME 0x40 195#define A_GMAC_MCAST_LO 0x44 196#define A_GMAC_MCAST_HI 0x48 197#define A_GMAC_MCAST_MASK_LO 0x4c 198#define A_GMAC_MCAST_MASK_HI 0x50 199#define A_GMAC_RMT_CNT 0x54 200#define A_GMAC_RMT_DATA 0x58 201#define A_GMAC_BACKOFF_SEED 0x5c 202#define A_GMAC_TXF_THRES 0x60 203 204#define S_TXF_READ_THRESHOLD 0 205#define M_TXF_READ_THRESHOLD 0xff 206#define V_TXF_READ_THRESHOLD(x) ((x) << S_TXF_READ_THRESHOLD) 207#define G_TXF_READ_THRESHOLD(x) (((x) >> S_TXF_READ_THRESHOLD) & M_TXF_READ_THRESHOLD) 208 209#define S_TXF_WRITE_THRESHOLD 16 210#define M_TXF_WRITE_THRESHOLD 0xff 211#define V_TXF_WRITE_THRESHOLD(x) ((x) << S_TXF_WRITE_THRESHOLD) 212#define G_TXF_WRITE_THRESHOLD(x) (((x) >> S_TXF_WRITE_THRESHOLD) & M_TXF_WRITE_THRESHOLD) 213 214#define MAC_REG_BASE 0x600 215#define MAC_REG_ADDR(idx, reg) (MAC_REG_BASE + (idx) * 128 + (reg)) 216 217#define MAC_REG_IDLO(idx) MAC_REG_ADDR(idx, A_GMAC_MACID_LO) 218#define MAC_REG_IDHI(idx) MAC_REG_ADDR(idx, A_GMAC_MACID_HI) 219#define MAC_REG_CSR(idx) MAC_REG_ADDR(idx, A_GMAC_CSR) 220#define MAC_REG_IFS(idx) MAC_REG_ADDR(idx, A_GMAC_IFS) 221#define MAC_REG_LARGEFRAMELENGTH(idx) MAC_REG_ADDR(idx, A_GMAC_JUMBO_FRAME_LEN) 222#define MAC_REG_LINKDLY(idx) MAC_REG_ADDR(idx, A_GMAC_LNK_DLY) 223#define MAC_REG_PAUSETIME(idx) MAC_REG_ADDR(idx, A_GMAC_PAUSETIME) 224#define MAC_REG_CASTLO(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_LO) 225#define MAC_REG_MCASTHI(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_HI) 226#define MAC_REG_CASTMASKLO(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_MASK_LO) 227#define MAC_REG_MCASTMASKHI(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_MASK_HI) 228#define MAC_REG_RMCNT(idx) MAC_REG_ADDR(idx, A_GMAC_RMT_CNT) 229#define MAC_REG_RMDATA(idx) MAC_REG_ADDR(idx, A_GMAC_RMT_DATA) 230#define MAC_REG_GMRANDBACKOFFSEED(idx) MAC_REG_ADDR(idx, A_GMAC_BACKOFF_SEED) 231#define MAC_REG_TXFTHRESHOLDS(idx) MAC_REG_ADDR(idx, A_GMAC_TXF_THRES) 232 233#endif