vsc7326_reg.h (15557B)
1/* SPDX-License-Identifier: GPL-2.0 */ 2/* $Date: 2006/04/28 19:20:17 $ $RCSfile: vsc7326_reg.h,v $ $Revision: 1.5 $ */ 3#ifndef _VSC7321_REG_H_ 4#define _VSC7321_REG_H_ 5 6/* Register definitions for Vitesse VSC7321 (Meigs II) MAC 7 * 8 * Straight off the data sheet, VMDS-10038 Rev 2.0 and 9 * PD0011-01-14-Meigs-II 2002-12-12 10 */ 11 12/* Just 'cause it's in here doesn't mean it's used. */ 13 14#define CRA(blk,sub,adr) ((((blk) & 0x7) << 13) | (((sub) & 0xf) << 9) | (((adr) & 0xff) << 1)) 15 16/* System and CPU comm's registers */ 17#define REG_CHIP_ID CRA(0x7,0xf,0x00) /* Chip ID */ 18#define REG_BLADE_ID CRA(0x7,0xf,0x01) /* Blade ID */ 19#define REG_SW_RESET CRA(0x7,0xf,0x02) /* Global Soft Reset */ 20#define REG_MEM_BIST CRA(0x7,0xf,0x04) /* mem */ 21#define REG_IFACE_MODE CRA(0x7,0xf,0x07) /* Interface mode */ 22#define REG_MSCH CRA(0x7,0x2,0x06) /* CRC error count */ 23#define REG_CRC_CNT CRA(0x7,0x2,0x0a) /* CRC error count */ 24#define REG_CRC_CFG CRA(0x7,0x2,0x0b) /* CRC config */ 25#define REG_SI_TRANSFER_SEL CRA(0x7,0xf,0x18) /* SI Transfer Select */ 26#define REG_PLL_CLK_SPEED CRA(0x7,0xf,0x19) /* Clock Speed Selection */ 27#define REG_SYS_CLK_SELECT CRA(0x7,0xf,0x1c) /* System Clock Select */ 28#define REG_GPIO_CTRL CRA(0x7,0xf,0x1d) /* GPIO Control */ 29#define REG_GPIO_OUT CRA(0x7,0xf,0x1e) /* GPIO Out */ 30#define REG_GPIO_IN CRA(0x7,0xf,0x1f) /* GPIO In */ 31#define REG_CPU_TRANSFER_SEL CRA(0x7,0xf,0x20) /* CPU Transfer Select */ 32#define REG_LOCAL_DATA CRA(0x7,0xf,0xfe) /* Local CPU Data Register */ 33#define REG_LOCAL_STATUS CRA(0x7,0xf,0xff) /* Local CPU Status Register */ 34 35/* Aggregator registers */ 36#define REG_AGGR_SETUP CRA(0x7,0x1,0x00) /* Aggregator Setup */ 37#define REG_PMAP_TABLE CRA(0x7,0x1,0x01) /* Port map table */ 38#define REG_MPLS_BIT0 CRA(0x7,0x1,0x08) /* MPLS bit0 position */ 39#define REG_MPLS_BIT1 CRA(0x7,0x1,0x09) /* MPLS bit1 position */ 40#define REG_MPLS_BIT2 CRA(0x7,0x1,0x0a) /* MPLS bit2 position */ 41#define REG_MPLS_BIT3 CRA(0x7,0x1,0x0b) /* MPLS bit3 position */ 42#define REG_MPLS_BITMASK CRA(0x7,0x1,0x0c) /* MPLS bit mask */ 43#define REG_PRE_BIT0POS CRA(0x7,0x1,0x10) /* Preamble bit0 position */ 44#define REG_PRE_BIT1POS CRA(0x7,0x1,0x11) /* Preamble bit1 position */ 45#define REG_PRE_BIT2POS CRA(0x7,0x1,0x12) /* Preamble bit2 position */ 46#define REG_PRE_BIT3POS CRA(0x7,0x1,0x13) /* Preamble bit3 position */ 47#define REG_PRE_ERR_CNT CRA(0x7,0x1,0x14) /* Preamble parity error count */ 48 49/* BIST registers */ 50/*#define REG_RAM_BIST_CMD CRA(0x7,0x2,0x00)*/ /* RAM BIST Command Register */ 51/*#define REG_RAM_BIST_RESULT CRA(0x7,0x2,0x01)*/ /* RAM BIST Read Status/Result */ 52#define REG_RAM_BIST_CMD CRA(0x7,0x1,0x00) /* RAM BIST Command Register */ 53#define REG_RAM_BIST_RESULT CRA(0x7,0x1,0x01) /* RAM BIST Read Status/Result */ 54#define BIST_PORT_SELECT 0x00 /* BIST port select */ 55#define BIST_COMMAND 0x01 /* BIST enable/disable */ 56#define BIST_STATUS 0x02 /* BIST operation status */ 57#define BIST_ERR_CNT_LSB 0x03 /* BIST error count lo 8b */ 58#define BIST_ERR_CNT_MSB 0x04 /* BIST error count hi 8b */ 59#define BIST_ERR_SEL_LSB 0x05 /* BIST error select lo 8b */ 60#define BIST_ERR_SEL_MSB 0x06 /* BIST error select hi 8b */ 61#define BIST_ERROR_STATE 0x07 /* BIST engine internal state */ 62#define BIST_ERR_ADR0 0x08 /* BIST error address lo 8b */ 63#define BIST_ERR_ADR1 0x09 /* BIST error address lomid 8b */ 64#define BIST_ERR_ADR2 0x0a /* BIST error address himid 8b */ 65#define BIST_ERR_ADR3 0x0b /* BIST error address hi 8b */ 66 67/* FIFO registers 68 * ie = 0 for ingress, 1 for egress 69 * fn = FIFO number, 0-9 70 */ 71#define REG_TEST(ie,fn) CRA(0x2,ie&1,0x00+fn) /* Mode & Test Register */ 72#define REG_TOP_BOTTOM(ie,fn) CRA(0x2,ie&1,0x10+fn) /* FIFO Buffer Top & Bottom */ 73#define REG_TAIL(ie,fn) CRA(0x2,ie&1,0x20+fn) /* FIFO Write Pointer */ 74#define REG_HEAD(ie,fn) CRA(0x2,ie&1,0x30+fn) /* FIFO Read Pointer */ 75#define REG_HIGH_LOW_WM(ie,fn) CRA(0x2,ie&1,0x40+fn) /* Flow Control Water Marks */ 76#define REG_CT_THRHLD(ie,fn) CRA(0x2,ie&1,0x50+fn) /* Cut Through Threshold */ 77#define REG_FIFO_DROP_CNT(ie,fn) CRA(0x2,ie&1,0x60+fn) /* Drop & CRC Error Counter */ 78#define REG_DEBUG_BUF_CNT(ie,fn) CRA(0x2,ie&1,0x70+fn) /* Input Side Debug Counter */ 79#define REG_BUCKI(fn) CRA(0x2,2,0x20+fn) /* Input Side Debug Counter */ 80#define REG_BUCKE(fn) CRA(0x2,3,0x20+fn) /* Input Side Debug Counter */ 81 82/* Traffic shaper buckets 83 * ie = 0 for ingress, 1 for egress 84 * bn = bucket number 0-10 (yes, 11 buckets) 85 */ 86/* OK, this one's kinda ugly. Some hardware designers are perverse. */ 87#define REG_TRAFFIC_SHAPER_BUCKET(ie,bn) CRA(0x2,ie&1,0x0a + (bn>7) | ((bn&7)<<4)) 88#define REG_TRAFFIC_SHAPER_CONTROL(ie) CRA(0x2,ie&1,0x3b) 89 90#define REG_SRAM_ADR(ie) CRA(0x2,ie&1,0x0e) /* FIFO SRAM address */ 91#define REG_SRAM_WR_STRB(ie) CRA(0x2,ie&1,0x1e) /* FIFO SRAM write strobe */ 92#define REG_SRAM_RD_STRB(ie) CRA(0x2,ie&1,0x2e) /* FIFO SRAM read strobe */ 93#define REG_SRAM_DATA_0(ie) CRA(0x2,ie&1,0x3e) /* FIFO SRAM data lo 8b */ 94#define REG_SRAM_DATA_1(ie) CRA(0x2,ie&1,0x4e) /* FIFO SRAM data lomid 8b */ 95#define REG_SRAM_DATA_2(ie) CRA(0x2,ie&1,0x5e) /* FIFO SRAM data himid 8b */ 96#define REG_SRAM_DATA_3(ie) CRA(0x2,ie&1,0x6e) /* FIFO SRAM data hi 8b */ 97#define REG_SRAM_DATA_BLK_TYPE(ie) CRA(0x2,ie&1,0x7e) /* FIFO SRAM tag */ 98/* REG_ING_CONTROL equals REG_CONTROL with ie = 0, likewise REG_EGR_CONTROL is ie = 1 */ 99#define REG_CONTROL(ie) CRA(0x2,ie&1,0x0f) /* FIFO control */ 100#define REG_ING_CONTROL CRA(0x2,0x0,0x0f) /* Ingress control (alias) */ 101#define REG_EGR_CONTROL CRA(0x2,0x1,0x0f) /* Egress control (alias) */ 102#define REG_AGE_TIMER(ie) CRA(0x2,ie&1,0x1f) /* Aging timer */ 103#define REG_AGE_INC(ie) CRA(0x2,ie&1,0x2f) /* Aging increment */ 104#define DEBUG_OUT(ie) CRA(0x2,ie&1,0x3f) /* Output debug counter control */ 105#define DEBUG_CNT(ie) CRA(0x2,ie&1,0x4f) /* Output debug counter */ 106 107/* SPI4 interface */ 108#define REG_SPI4_MISC CRA(0x5,0x0,0x00) /* Misc Register */ 109#define REG_SPI4_STATUS CRA(0x5,0x0,0x01) /* CML Status */ 110#define REG_SPI4_ING_SETUP0 CRA(0x5,0x0,0x02) /* Ingress Status Channel Setup */ 111#define REG_SPI4_ING_SETUP1 CRA(0x5,0x0,0x03) /* Ingress Data Training Setup */ 112#define REG_SPI4_ING_SETUP2 CRA(0x5,0x0,0x04) /* Ingress Data Burst Size Setup */ 113#define REG_SPI4_EGR_SETUP0 CRA(0x5,0x0,0x05) /* Egress Status Channel Setup */ 114#define REG_SPI4_DBG_CNT(n) CRA(0x5,0x0,0x10+n) /* Debug counters 0-9 */ 115#define REG_SPI4_DBG_SETUP CRA(0x5,0x0,0x1A) /* Debug counters setup */ 116#define REG_SPI4_TEST CRA(0x5,0x0,0x20) /* Test Setup Register */ 117#define REG_TPGEN_UP0 CRA(0x5,0x0,0x21) /* Test Pattern generator user pattern 0 */ 118#define REG_TPGEN_UP1 CRA(0x5,0x0,0x22) /* Test Pattern generator user pattern 1 */ 119#define REG_TPCHK_UP0 CRA(0x5,0x0,0x23) /* Test Pattern checker user pattern 0 */ 120#define REG_TPCHK_UP1 CRA(0x5,0x0,0x24) /* Test Pattern checker user pattern 1 */ 121#define REG_TPSAM_P0 CRA(0x5,0x0,0x25) /* Sampled pattern 0 */ 122#define REG_TPSAM_P1 CRA(0x5,0x0,0x26) /* Sampled pattern 1 */ 123#define REG_TPERR_CNT CRA(0x5,0x0,0x27) /* Pattern checker error counter */ 124#define REG_SPI4_STICKY CRA(0x5,0x0,0x30) /* Sticky bits register */ 125#define REG_SPI4_DBG_INH CRA(0x5,0x0,0x31) /* Core egress & ingress inhibit */ 126#define REG_SPI4_DBG_STATUS CRA(0x5,0x0,0x32) /* Sampled ingress status */ 127#define REG_SPI4_DBG_GRANT CRA(0x5,0x0,0x33) /* Ingress cranted credit value */ 128 129#define REG_SPI4_DESKEW CRA(0x5,0x0,0x43) /* Ingress cranted credit value */ 130 131/* 10GbE MAC Block Registers */ 132/* Note that those registers that are exactly the same for 10GbE as for 133 * tri-speed are only defined with the version that needs a port number. 134 * Pass 0xa in those cases. 135 * 136 * Also note that despite the presence of a MAC address register, this part 137 * does no ingress MAC address filtering. That register is used only for 138 * pause frame detection and generation. 139 */ 140/* 10GbE specific, and different from tri-speed */ 141#define REG_MISC_10G CRA(0x1,0xa,0x00) /* Misc 10GbE setup */ 142#define REG_PAUSE_10G CRA(0x1,0xa,0x01) /* Pause register */ 143#define REG_NORMALIZER_10G CRA(0x1,0xa,0x05) /* 10G normalizer */ 144#define REG_STICKY_RX CRA(0x1,0xa,0x06) /* RX debug register */ 145#define REG_DENORM_10G CRA(0x1,0xa,0x07) /* Denormalizer */ 146#define REG_STICKY_TX CRA(0x1,0xa,0x08) /* TX sticky bits */ 147#define REG_MAX_RXHIGH CRA(0x1,0xa,0x0a) /* XGMII lane 0-3 debug */ 148#define REG_MAX_RXLOW CRA(0x1,0xa,0x0b) /* XGMII lane 4-7 debug */ 149#define REG_MAC_TX_STICKY CRA(0x1,0xa,0x0c) /* MAC Tx state sticky debug */ 150#define REG_MAC_TX_RUNNING CRA(0x1,0xa,0x0d) /* MAC Tx state running debug */ 151#define REG_TX_ABORT_AGE CRA(0x1,0xa,0x14) /* Aged Tx frames discarded */ 152#define REG_TX_ABORT_SHORT CRA(0x1,0xa,0x15) /* Short Tx frames discarded */ 153#define REG_TX_ABORT_TAXI CRA(0x1,0xa,0x16) /* Taxi error frames discarded */ 154#define REG_TX_ABORT_UNDERRUN CRA(0x1,0xa,0x17) /* Tx Underrun abort counter */ 155#define REG_TX_DENORM_DISCARD CRA(0x1,0xa,0x18) /* Tx denormalizer discards */ 156#define REG_XAUI_STAT_A CRA(0x1,0xa,0x20) /* XAUI status A */ 157#define REG_XAUI_STAT_B CRA(0x1,0xa,0x21) /* XAUI status B */ 158#define REG_XAUI_STAT_C CRA(0x1,0xa,0x22) /* XAUI status C */ 159#define REG_XAUI_CONF_A CRA(0x1,0xa,0x23) /* XAUI configuration A */ 160#define REG_XAUI_CONF_B CRA(0x1,0xa,0x24) /* XAUI configuration B */ 161#define REG_XAUI_CODE_GRP_CNT CRA(0x1,0xa,0x25) /* XAUI code group error count */ 162#define REG_XAUI_CONF_TEST_A CRA(0x1,0xa,0x26) /* XAUI test register A */ 163#define REG_PDERRCNT CRA(0x1,0xa,0x27) /* XAUI test register B */ 164 165/* pn = port number 0-9 for tri-speed, 10 for 10GbE */ 166/* Both tri-speed and 10GbE */ 167#define REG_MAX_LEN(pn) CRA(0x1,pn,0x02) /* Max length */ 168#define REG_MAC_HIGH_ADDR(pn) CRA(0x1,pn,0x03) /* Upper 24 bits of MAC addr */ 169#define REG_MAC_LOW_ADDR(pn) CRA(0x1,pn,0x04) /* Lower 24 bits of MAC addr */ 170 171/* tri-speed only 172 * pn = port number, 0-9 173 */ 174#define REG_MODE_CFG(pn) CRA(0x1,pn,0x00) /* Mode configuration */ 175#define REG_PAUSE_CFG(pn) CRA(0x1,pn,0x01) /* Pause configuration */ 176#define REG_NORMALIZER(pn) CRA(0x1,pn,0x05) /* Normalizer */ 177#define REG_TBI_STATUS(pn) CRA(0x1,pn,0x06) /* TBI status */ 178#define REG_PCS_STATUS_DBG(pn) CRA(0x1,pn,0x07) /* PCS status debug */ 179#define REG_PCS_CTRL(pn) CRA(0x1,pn,0x08) /* PCS control */ 180#define REG_TBI_CONFIG(pn) CRA(0x1,pn,0x09) /* TBI configuration */ 181#define REG_STICK_BIT(pn) CRA(0x1,pn,0x0a) /* Sticky bits */ 182#define REG_DEV_SETUP(pn) CRA(0x1,pn,0x0b) /* MAC clock/reset setup */ 183#define REG_DROP_CNT(pn) CRA(0x1,pn,0x0c) /* Drop counter */ 184#define REG_PORT_POS(pn) CRA(0x1,pn,0x0d) /* Preamble port position */ 185#define REG_PORT_FAIL(pn) CRA(0x1,pn,0x0e) /* Preamble port position */ 186#define REG_SERDES_CONF(pn) CRA(0x1,pn,0x0f) /* SerDes configuration */ 187#define REG_SERDES_TEST(pn) CRA(0x1,pn,0x10) /* SerDes test */ 188#define REG_SERDES_STAT(pn) CRA(0x1,pn,0x11) /* SerDes status */ 189#define REG_SERDES_COM_CNT(pn) CRA(0x1,pn,0x12) /* SerDes comma counter */ 190#define REG_DENORM(pn) CRA(0x1,pn,0x15) /* Frame denormalization */ 191#define REG_DBG(pn) CRA(0x1,pn,0x16) /* Device 1G debug */ 192#define REG_TX_IFG(pn) CRA(0x1,pn,0x18) /* Tx IFG config */ 193#define REG_HDX(pn) CRA(0x1,pn,0x19) /* Half-duplex config */ 194 195/* Statistics */ 196/* CRA(0x4,pn,reg) */ 197/* reg below */ 198/* pn = port number, 0-a, a = 10GbE */ 199 200enum { 201 RxInBytes = 0x00, // # Rx in octets 202 RxSymbolCarrier = 0x01, // Frames w/ symbol errors 203 RxPause = 0x02, // # pause frames received 204 RxUnsupOpcode = 0x03, // # control frames with unsupported opcode 205 RxOkBytes = 0x04, // # octets in good frames 206 RxBadBytes = 0x05, // # octets in bad frames 207 RxUnicast = 0x06, // # good unicast frames 208 RxMulticast = 0x07, // # good multicast frames 209 RxBroadcast = 0x08, // # good broadcast frames 210 Crc = 0x09, // # frames w/ bad CRC only 211 RxAlignment = 0x0a, // # frames w/ alignment err 212 RxUndersize = 0x0b, // # frames undersize 213 RxFragments = 0x0c, // # frames undersize w/ crc err 214 RxInRangeLengthError = 0x0d, // # frames with length error 215 RxOutOfRangeError = 0x0e, // # frames with illegal length field 216 RxOversize = 0x0f, // # frames oversize 217 RxJabbers = 0x10, // # frames oversize w/ crc err 218 RxSize64 = 0x11, // # frames 64 octets long 219 RxSize65To127 = 0x12, // # frames 65-127 octets 220 RxSize128To255 = 0x13, // # frames 128-255 221 RxSize256To511 = 0x14, // # frames 256-511 222 RxSize512To1023 = 0x15, // # frames 512-1023 223 RxSize1024To1518 = 0x16, // # frames 1024-1518 224 RxSize1519ToMax = 0x17, // # frames 1519-max 225 226 TxOutBytes = 0x18, // # octets tx 227 TxPause = 0x19, // # pause frames sent 228 TxOkBytes = 0x1a, // # octets tx OK 229 TxUnicast = 0x1b, // # frames unicast 230 TxMulticast = 0x1c, // # frames multicast 231 TxBroadcast = 0x1d, // # frames broadcast 232 TxMultipleColl = 0x1e, // # frames tx after multiple collisions 233 TxLateColl = 0x1f, // # late collisions detected 234 TxXcoll = 0x20, // # frames lost, excessive collisions 235 TxDefer = 0x21, // # frames deferred on first tx attempt 236 TxXdefer = 0x22, // # frames excessively deferred 237 TxCsense = 0x23, // carrier sense errors at frame end 238 TxSize64 = 0x24, // # frames 64 octets long 239 TxSize65To127 = 0x25, // # frames 65-127 octets 240 TxSize128To255 = 0x26, // # frames 128-255 241 TxSize256To511 = 0x27, // # frames 256-511 242 TxSize512To1023 = 0x28, // # frames 512-1023 243 TxSize1024To1518 = 0x29, // # frames 1024-1518 244 TxSize1519ToMax = 0x2a, // # frames 1519-max 245 TxSingleColl = 0x2b, // # frames tx after single collision 246 TxBackoff2 = 0x2c, // # frames tx ok after 2 backoffs/collisions 247 TxBackoff3 = 0x2d, // after 3 backoffs/collisions 248 TxBackoff4 = 0x2e, // after 4 249 TxBackoff5 = 0x2f, // after 5 250 TxBackoff6 = 0x30, // after 6 251 TxBackoff7 = 0x31, // after 7 252 TxBackoff8 = 0x32, // after 8 253 TxBackoff9 = 0x33, // after 9 254 TxBackoff10 = 0x34, // after 10 255 TxBackoff11 = 0x35, // after 11 256 TxBackoff12 = 0x36, // after 12 257 TxBackoff13 = 0x37, // after 13 258 TxBackoff14 = 0x38, // after 14 259 TxBackoff15 = 0x39, // after 15 260 TxUnderrun = 0x3a, // # frames dropped from underrun 261 // Hole. See REG_RX_XGMII_PROT_ERR below. 262 RxIpgShrink = 0x3c, // # of IPG shrinks detected 263 // Duplicate. See REG_STAT_STICKY10G below. 264 StatSticky1G = 0x3e, // tri-speed sticky bits 265 StatInit = 0x3f // Clear all statistics 266}; 267 268#define REG_RX_XGMII_PROT_ERR CRA(0x4,0xa,0x3b) /* # protocol errors detected on XGMII interface */ 269#define REG_STAT_STICKY10G CRA(0x4,0xa,StatSticky1G) /* 10GbE sticky bits */ 270 271#define REG_RX_OK_BYTES(pn) CRA(0x4,pn,RxOkBytes) 272#define REG_RX_BAD_BYTES(pn) CRA(0x4,pn,RxBadBytes) 273#define REG_TX_OK_BYTES(pn) CRA(0x4,pn,TxOkBytes) 274 275/* MII-Management Block registers */ 276/* These are for MII-M interface 0, which is the bidirectional LVTTL one. If 277 * we hooked up to the one with separate directions, the middle 0x0 needs to 278 * change to 0x1. And the current errata states that MII-M 1 doesn't work. 279 */ 280 281#define REG_MIIM_STATUS CRA(0x3,0x0,0x00) /* MII-M Status */ 282#define REG_MIIM_CMD CRA(0x3,0x0,0x01) /* MII-M Command */ 283#define REG_MIIM_DATA CRA(0x3,0x0,0x02) /* MII-M Data */ 284#define REG_MIIM_PRESCALE CRA(0x3,0x0,0x03) /* MII-M MDC Prescale */ 285 286#define REG_ING_FFILT_UM_EN CRA(0x2, 0, 0xd) 287#define REG_ING_FFILT_BE_EN CRA(0x2, 0, 0x1d) 288#define REG_ING_FFILT_VAL0 CRA(0x2, 0, 0x2d) 289#define REG_ING_FFILT_VAL1 CRA(0x2, 0, 0x3d) 290#define REG_ING_FFILT_MASK0 CRA(0x2, 0, 0x4d) 291#define REG_ING_FFILT_MASK1 CRA(0x2, 0, 0x5d) 292#define REG_ING_FFILT_MASK2 CRA(0x2, 0, 0x6d) 293#define REG_ING_FFILT_ETYPE CRA(0x2, 0, 0x7d) 294 295 296/* Whew. */ 297 298#endif