cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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cxgb4_ptp.h (2715B)

      1/*
      2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
      3 *
      4 * Copyright (c) 2003-2017 Chelsio Communications, Inc. All rights reserved.
      5 *
      6 * This software is available to you under a choice of one of two
      7 * licenses.  You may choose to be licensed under the terms of the GNU
      8 * General Public License (GPL) Version 2, available from the file
      9 * COPYING in the main directory of this source tree, or the
     10 * OpenIB.org BSD license below:
     11 *
     12 *     Redistribution and use in source and binary forms, with or
     13 *     without modification, are permitted provided that the following
     14 *     conditions are met:
     15 *
     16 *      - Redistributions of source code must retain the above
     17 *        copyright notice, this list of conditions and the following
     18 *        disclaimer.
     19 *
     20 *      - Redistributions in binary form must reproduce the above
     21 *        copyright notice, this list of conditions and the following
     22 *        disclaimer in the documentation and/or other materials
     23 *        provided with the distribution.
     24 *
     25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
     26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
     27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
     28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
     29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
     30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
     31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
     32 * SOFTWARE.
     33 */
     34
     35#ifndef __CXGB4_PTP_H__
     36#define __CXGB4_PTP_H__
     37
     38/* Maximum parts-per-billion adjustment that is acceptable */
     39#define MAX_PTP_FREQ_ADJ		1000000
     40#define PTP_CLOCK_MAX_ADJTIME		10000000 /* 10 ms */
     41
     42#define PTP_MIN_LENGTH			63
     43#define PTP_IN_TRANSMIT_PACKET_MAXNUM	240
     44#define PTP_EVENT_PORT			319
     45
     46enum ptp_rx_filter_mode {
     47	PTP_TS_NONE = 0,
     48	PTP_TS_L2,
     49	PTP_TS_L4,
     50	PTP_TS_L2_L4
     51};
     52
     53struct port_info;
     54
     55static inline bool cxgb4_xmit_with_hwtstamp(struct sk_buff *skb)
     56{
     57	return skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP;
     58}
     59
     60static inline void cxgb4_xmit_hwtstamp_pending(struct sk_buff *skb)
     61{
     62	skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
     63}
     64
     65void cxgb4_ptp_init(struct adapter *adap);
     66void cxgb4_ptp_stop(struct adapter *adap);
     67bool cxgb4_ptp_is_ptp_tx(struct sk_buff *skb);
     68bool cxgb4_ptp_is_ptp_rx(struct sk_buff *skb);
     69int cxgb4_ptprx_timestamping(struct port_info *pi, u8 port, u16 mode);
     70int cxgb4_ptp_redirect_rx_packet(struct adapter *adap, struct port_info *pi);
     71int cxgb4_ptp_txtype(struct adapter *adap, u8 port_id);
     72void cxgb4_ptp_read_hwstamp(struct adapter *adap, struct port_info *pi);
     73bool is_ptp_enabled(struct sk_buff *skb, struct net_device *dev);
     74#endif /* __CXGB4_PTP_H__ */