cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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gve_dqo.h (2840B)

      1/* SPDX-License-Identifier: (GPL-2.0 OR MIT)
      2 * Google virtual Ethernet (gve) driver
      3 *
      4 * Copyright (C) 2015-2021 Google, Inc.
      5 */
      6
      7#ifndef _GVE_DQO_H_
      8#define _GVE_DQO_H_
      9
     10#include "gve_adminq.h"
     11
     12#define GVE_ITR_ENABLE_BIT_DQO BIT(0)
     13#define GVE_ITR_CLEAR_PBA_BIT_DQO BIT(1)
     14#define GVE_ITR_NO_UPDATE_DQO (3 << 3)
     15
     16#define GVE_ITR_INTERVAL_DQO_SHIFT 5
     17#define GVE_ITR_INTERVAL_DQO_MASK ((1 << 12) - 1)
     18
     19#define GVE_TX_IRQ_RATELIMIT_US_DQO 50
     20#define GVE_RX_IRQ_RATELIMIT_US_DQO 20
     21#define GVE_MAX_ITR_INTERVAL_DQO (GVE_ITR_INTERVAL_DQO_MASK * 2)
     22
     23/* Timeout in seconds to wait for a reinjection completion after receiving
     24 * its corresponding miss completion.
     25 */
     26#define GVE_REINJECT_COMPL_TIMEOUT 1
     27
     28/* Timeout in seconds to deallocate the completion tag for a packet that was
     29 * prematurely freed for not receiving a valid completion. This should be large
     30 * enough to rule out the possibility of receiving the corresponding valid
     31 * completion after this interval.
     32 */
     33#define GVE_DEALLOCATE_COMPL_TIMEOUT 60
     34
     35netdev_tx_t gve_tx_dqo(struct sk_buff *skb, struct net_device *dev);
     36bool gve_tx_poll_dqo(struct gve_notify_block *block, bool do_clean);
     37int gve_rx_poll_dqo(struct gve_notify_block *block, int budget);
     38int gve_tx_alloc_rings_dqo(struct gve_priv *priv);
     39void gve_tx_free_rings_dqo(struct gve_priv *priv);
     40int gve_rx_alloc_rings_dqo(struct gve_priv *priv);
     41void gve_rx_free_rings_dqo(struct gve_priv *priv);
     42int gve_clean_tx_done_dqo(struct gve_priv *priv, struct gve_tx_ring *tx,
     43			  struct napi_struct *napi);
     44void gve_rx_post_buffers_dqo(struct gve_rx_ring *rx);
     45void gve_rx_write_doorbell_dqo(const struct gve_priv *priv, int queue_idx);
     46
     47static inline void
     48gve_tx_put_doorbell_dqo(const struct gve_priv *priv,
     49			const struct gve_queue_resources *q_resources, u32 val)
     50{
     51	u64 index;
     52
     53	index = be32_to_cpu(q_resources->db_index);
     54	iowrite32(val, &priv->db_bar2[index]);
     55}
     56
     57/* Builds register value to write to DQO IRQ doorbell to enable with specified
     58 * ITR interval.
     59 */
     60static inline u32 gve_setup_itr_interval_dqo(u32 interval_us)
     61{
     62	u32 result = GVE_ITR_ENABLE_BIT_DQO;
     63
     64	/* Interval has 2us granularity. */
     65	interval_us >>= 1;
     66
     67	interval_us &= GVE_ITR_INTERVAL_DQO_MASK;
     68	result |= (interval_us << GVE_ITR_INTERVAL_DQO_SHIFT);
     69
     70	return result;
     71}
     72
     73static inline void
     74gve_write_irq_doorbell_dqo(const struct gve_priv *priv,
     75			   const struct gve_notify_block *block, u32 val)
     76{
     77	u32 index = be32_to_cpu(*block->irq_db_index);
     78
     79	iowrite32(val, &priv->db_bar2[index]);
     80}
     81
     82/* Sets interrupt throttling interval and enables interrupt
     83 * by writing to IRQ doorbell.
     84 */
     85static inline void
     86gve_set_itr_coalesce_usecs_dqo(struct gve_priv *priv,
     87			       struct gve_notify_block *block,
     88			       u32 usecs)
     89{
     90	gve_write_irq_doorbell_dqo(priv, block,
     91				   gve_setup_itr_interval_dqo(usecs));
     92}
     93#endif /* _GVE_DQO_H_ */