cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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hinic_dev.h (2806B)

      1/* SPDX-License-Identifier: GPL-2.0-only */
      2/*
      3 * Huawei HiNIC PCI Express Linux driver
      4 * Copyright(c) 2017 Huawei Technologies Co., Ltd
      5 */
      6
      7#ifndef HINIC_DEV_H
      8#define HINIC_DEV_H
      9
     10#include <linux/netdevice.h>
     11#include <linux/types.h>
     12#include <linux/semaphore.h>
     13#include <linux/workqueue.h>
     14#include <linux/bitops.h>
     15
     16#include "hinic_hw_dev.h"
     17#include "hinic_tx.h"
     18#include "hinic_rx.h"
     19#include "hinic_sriov.h"
     20
     21#define HINIC_DRV_NAME          "hinic"
     22
     23#define LP_PKT_CNT		64
     24
     25enum hinic_flags {
     26	HINIC_LINK_UP = BIT(0),
     27	HINIC_INTF_UP = BIT(1),
     28	HINIC_RSS_ENABLE = BIT(2),
     29	HINIC_LINK_DOWN = BIT(3),
     30	HINIC_LP_TEST = BIT(4),
     31};
     32
     33struct hinic_rx_mode_work {
     34	struct work_struct      work;
     35	u32                     rx_mode;
     36};
     37
     38struct hinic_rss_type {
     39	u8 tcp_ipv6_ext;
     40	u8 ipv6_ext;
     41	u8 tcp_ipv6;
     42	u8 ipv6;
     43	u8 tcp_ipv4;
     44	u8 ipv4;
     45	u8 udp_ipv6;
     46	u8 udp_ipv4;
     47};
     48
     49enum hinic_rss_hash_type {
     50	HINIC_RSS_HASH_ENGINE_TYPE_XOR,
     51	HINIC_RSS_HASH_ENGINE_TYPE_TOEP,
     52	HINIC_RSS_HASH_ENGINE_TYPE_MAX,
     53};
     54
     55struct hinic_intr_coal_info {
     56	u8	pending_limt;
     57	u8	coalesce_timer_cfg;
     58	u8	resend_timer_cfg;
     59};
     60
     61enum hinic_dbg_type {
     62	HINIC_DBG_SQ_INFO,
     63	HINIC_DBG_RQ_INFO,
     64	HINIC_DBG_FUNC_TABLE,
     65};
     66
     67struct hinic_debug_priv {
     68	struct hinic_dev	*dev;
     69	void			*object;
     70	enum hinic_dbg_type	type;
     71	struct dentry		*root;
     72	int			field_id[64];
     73};
     74
     75struct hinic_dev {
     76	struct net_device               *netdev;
     77	struct hinic_hwdev              *hwdev;
     78
     79	u32                             msg_enable;
     80	unsigned int                    tx_weight;
     81	unsigned int                    rx_weight;
     82	u16				num_qps;
     83	u16				max_qps;
     84
     85	unsigned int                    flags;
     86
     87	struct semaphore                mgmt_lock;
     88	unsigned long                   *vlan_bitmap;
     89
     90	struct hinic_rx_mode_work       rx_mode_work;
     91	struct workqueue_struct         *workq;
     92
     93	struct hinic_txq                *txqs;
     94	struct hinic_rxq                *rxqs;
     95	u16				sq_depth;
     96	u16				rq_depth;
     97
     98	struct hinic_txq_stats          tx_stats;
     99	struct hinic_rxq_stats          rx_stats;
    100
    101	u8				rss_tmpl_idx;
    102	u8				rss_hash_engine;
    103	u16				num_rss;
    104	u16				rss_limit;
    105	struct hinic_rss_type		rss_type;
    106	u8				*rss_hkey_user;
    107	s32				*rss_indir_user;
    108	struct hinic_intr_coal_info	*rx_intr_coalesce;
    109	struct hinic_intr_coal_info	*tx_intr_coalesce;
    110	struct hinic_sriov_info sriov_info;
    111	int				lb_test_rx_idx;
    112	int				lb_pkt_len;
    113	u8				*lb_test_rx_buf;
    114
    115	struct dentry			*dbgfs_root;
    116	struct dentry			*sq_dbgfs;
    117	struct dentry			*rq_dbgfs;
    118	struct dentry			*func_tbl_dbgfs;
    119	struct hinic_debug_priv		*dbg;
    120	struct devlink			*devlink;
    121	bool				cable_unplugged;
    122	bool				module_unrecognized;
    123};
    124
    125struct hinic_devlink_priv {
    126	struct hinic_hwdev		*hwdev;
    127	struct devlink_health_reporter  *hw_fault_reporter;
    128	struct devlink_health_reporter  *fw_fault_reporter;
    129};
    130
    131#endif