cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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i40e_lan_hmc.h (4246B)


      1/* SPDX-License-Identifier: GPL-2.0 */
      2/* Copyright(c) 2013 - 2018 Intel Corporation. */
      3
      4#ifndef _I40E_LAN_HMC_H_
      5#define _I40E_LAN_HMC_H_
      6
      7/* forward-declare the HW struct for the compiler */
      8struct i40e_hw;
      9
     10/* HMC element context information */
     11
     12/* Rx queue context data
     13 *
     14 * The sizes of the variables may be larger than needed due to crossing byte
     15 * boundaries. If we do not have the width of the variable set to the correct
     16 * size then we could end up shifting bits off the top of the variable when the
     17 * variable is at the top of a byte and crosses over into the next byte.
     18 */
     19struct i40e_hmc_obj_rxq {
     20	u16 head;
     21	u16 cpuid; /* bigger than needed, see above for reason */
     22	u64 base;
     23	u16 qlen;
     24#define I40E_RXQ_CTX_DBUFF_SHIFT 7
     25	u16 dbuff; /* bigger than needed, see above for reason */
     26#define I40E_RXQ_CTX_HBUFF_SHIFT 6
     27	u16 hbuff; /* bigger than needed, see above for reason */
     28	u8  dtype;
     29	u8  dsize;
     30	u8  crcstrip;
     31	u8  fc_ena;
     32	u8  l2tsel;
     33	u8  hsplit_0;
     34	u8  hsplit_1;
     35	u8  showiv;
     36	u32 rxmax; /* bigger than needed, see above for reason */
     37	u8  tphrdesc_ena;
     38	u8  tphwdesc_ena;
     39	u8  tphdata_ena;
     40	u8  tphhead_ena;
     41	u16 lrxqthresh; /* bigger than needed, see above for reason */
     42	u8  prefena;	/* NOTE: normally must be set to 1 at init */
     43};
     44
     45/* Tx queue context data
     46*
     47* The sizes of the variables may be larger than needed due to crossing byte
     48* boundaries. If we do not have the width of the variable set to the correct
     49* size then we could end up shifting bits off the top of the variable when the
     50* variable is at the top of a byte and crosses over into the next byte.
     51*/
     52struct i40e_hmc_obj_txq {
     53	u16 head;
     54	u8  new_context;
     55	u64 base;
     56	u8  fc_ena;
     57	u8  timesync_ena;
     58	u8  fd_ena;
     59	u8  alt_vlan_ena;
     60	u16 thead_wb;
     61	u8  cpuid;
     62	u8  head_wb_ena;
     63	u16 qlen;
     64	u8  tphrdesc_ena;
     65	u8  tphrpacket_ena;
     66	u8  tphwdesc_ena;
     67	u64 head_wb_addr;
     68	u32 crc;
     69	u16 rdylist;
     70	u8  rdylist_act;
     71};
     72
     73/* for hsplit_0 field of Rx HMC context */
     74enum i40e_hmc_obj_rx_hsplit_0 {
     75	I40E_HMC_OBJ_RX_HSPLIT_0_NO_SPLIT      = 0,
     76	I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_L2      = 1,
     77	I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_IP      = 2,
     78	I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_TCP_UDP = 4,
     79	I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_SCTP    = 8,
     80};
     81
     82/* fcoe_cntx and fcoe_filt are for debugging purpose only */
     83struct i40e_hmc_obj_fcoe_cntx {
     84	u32 rsv[32];
     85};
     86
     87struct i40e_hmc_obj_fcoe_filt {
     88	u32 rsv[8];
     89};
     90
     91/* Context sizes for LAN objects */
     92enum i40e_hmc_lan_object_size {
     93	I40E_HMC_LAN_OBJ_SZ_8   = 0x3,
     94	I40E_HMC_LAN_OBJ_SZ_16  = 0x4,
     95	I40E_HMC_LAN_OBJ_SZ_32  = 0x5,
     96	I40E_HMC_LAN_OBJ_SZ_64  = 0x6,
     97	I40E_HMC_LAN_OBJ_SZ_128 = 0x7,
     98	I40E_HMC_LAN_OBJ_SZ_256 = 0x8,
     99	I40E_HMC_LAN_OBJ_SZ_512 = 0x9,
    100};
    101
    102#define I40E_HMC_L2OBJ_BASE_ALIGNMENT 512
    103#define I40E_HMC_OBJ_SIZE_TXQ         128
    104#define I40E_HMC_OBJ_SIZE_RXQ         32
    105#define I40E_HMC_OBJ_SIZE_FCOE_CNTX   64
    106#define I40E_HMC_OBJ_SIZE_FCOE_FILT   64
    107
    108enum i40e_hmc_lan_rsrc_type {
    109	I40E_HMC_LAN_FULL  = 0,
    110	I40E_HMC_LAN_TX    = 1,
    111	I40E_HMC_LAN_RX    = 2,
    112	I40E_HMC_FCOE_CTX  = 3,
    113	I40E_HMC_FCOE_FILT = 4,
    114	I40E_HMC_LAN_MAX   = 5
    115};
    116
    117enum i40e_hmc_model {
    118	I40E_HMC_MODEL_DIRECT_PREFERRED = 0,
    119	I40E_HMC_MODEL_DIRECT_ONLY      = 1,
    120	I40E_HMC_MODEL_PAGED_ONLY       = 2,
    121	I40E_HMC_MODEL_UNKNOWN,
    122};
    123
    124struct i40e_hmc_lan_create_obj_info {
    125	struct i40e_hmc_info *hmc_info;
    126	u32 rsrc_type;
    127	u32 start_idx;
    128	u32 count;
    129	enum i40e_sd_entry_type entry_type;
    130	u64 direct_mode_sz;
    131};
    132
    133struct i40e_hmc_lan_delete_obj_info {
    134	struct i40e_hmc_info *hmc_info;
    135	u32 rsrc_type;
    136	u32 start_idx;
    137	u32 count;
    138};
    139
    140i40e_status i40e_init_lan_hmc(struct i40e_hw *hw, u32 txq_num,
    141					u32 rxq_num, u32 fcoe_cntx_num,
    142					u32 fcoe_filt_num);
    143i40e_status i40e_configure_lan_hmc(struct i40e_hw *hw,
    144					     enum i40e_hmc_model model);
    145i40e_status i40e_shutdown_lan_hmc(struct i40e_hw *hw);
    146
    147i40e_status i40e_clear_lan_tx_queue_context(struct i40e_hw *hw,
    148						      u16 queue);
    149i40e_status i40e_set_lan_tx_queue_context(struct i40e_hw *hw,
    150						    u16 queue,
    151						    struct i40e_hmc_obj_txq *s);
    152i40e_status i40e_clear_lan_rx_queue_context(struct i40e_hw *hw,
    153						      u16 queue);
    154i40e_status i40e_set_lan_rx_queue_context(struct i40e_hw *hw,
    155						    u16 queue,
    156						    struct i40e_hmc_obj_rxq *s);
    157
    158#endif /* _I40E_LAN_HMC_H_ */