cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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ice_base.h (1276B)


      1/* SPDX-License-Identifier: GPL-2.0 */
      2/* Copyright (c) 2019, Intel Corporation. */
      3
      4#ifndef _ICE_BASE_H_
      5#define _ICE_BASE_H_
      6
      7#include "ice.h"
      8
      9int ice_vsi_cfg_rxq(struct ice_rx_ring *ring);
     10int __ice_vsi_get_qs(struct ice_qs_cfg *qs_cfg);
     11int
     12ice_vsi_ctrl_one_rx_ring(struct ice_vsi *vsi, bool ena, u16 rxq_idx, bool wait);
     13int ice_vsi_wait_one_rx_ring(struct ice_vsi *vsi, bool ena, u16 rxq_idx);
     14int ice_vsi_alloc_q_vectors(struct ice_vsi *vsi);
     15void ice_vsi_map_rings_to_vectors(struct ice_vsi *vsi);
     16void ice_vsi_free_q_vectors(struct ice_vsi *vsi);
     17int
     18ice_vsi_cfg_txq(struct ice_vsi *vsi, struct ice_tx_ring *ring,
     19		struct ice_aqc_add_tx_qgrp *qg_buf);
     20void ice_cfg_itr(struct ice_hw *hw, struct ice_q_vector *q_vector);
     21void
     22ice_cfg_txq_interrupt(struct ice_vsi *vsi, u16 txq, u16 msix_idx, u16 itr_idx);
     23void
     24ice_cfg_rxq_interrupt(struct ice_vsi *vsi, u16 rxq, u16 msix_idx, u16 itr_idx);
     25void ice_trigger_sw_intr(struct ice_hw *hw, struct ice_q_vector *q_vector);
     26int
     27ice_vsi_stop_tx_ring(struct ice_vsi *vsi, enum ice_disq_rst_src rst_src,
     28		     u16 rel_vmvf_num, struct ice_tx_ring *ring,
     29		     struct ice_txq_meta *txq_meta);
     30void
     31ice_fill_txq_meta(struct ice_vsi *vsi, struct ice_tx_ring *ring,
     32		  struct ice_txq_meta *txq_meta);
     33#endif /* _ICE_BASE_H_ */