ice_hw_autogen.h (22089B)
1/* SPDX-License-Identifier: GPL-2.0 */ 2/* Copyright (c) 2018, Intel Corporation. */ 3 4/* Machine-generated file */ 5 6#ifndef _ICE_HW_AUTOGEN_H_ 7#define _ICE_HW_AUTOGEN_H_ 8 9#define QTX_COMM_DBELL(_DBQM) (0x002C0000 + ((_DBQM) * 4)) 10#define QTX_COMM_HEAD(_DBQM) (0x000E0000 + ((_DBQM) * 4)) 11#define QTX_COMM_HEAD_HEAD_S 0 12#define QTX_COMM_HEAD_HEAD_M ICE_M(0x1FFF, 0) 13#define PF_FW_ARQBAH 0x00080180 14#define PF_FW_ARQBAL 0x00080080 15#define PF_FW_ARQH 0x00080380 16#define PF_FW_ARQH_ARQH_M ICE_M(0x3FF, 0) 17#define PF_FW_ARQLEN 0x00080280 18#define PF_FW_ARQLEN_ARQLEN_M ICE_M(0x3FF, 0) 19#define PF_FW_ARQLEN_ARQVFE_M BIT(28) 20#define PF_FW_ARQLEN_ARQOVFL_M BIT(29) 21#define PF_FW_ARQLEN_ARQCRIT_M BIT(30) 22#define PF_FW_ARQLEN_ARQENABLE_M BIT(31) 23#define PF_FW_ARQT 0x00080480 24#define PF_FW_ATQBAH 0x00080100 25#define PF_FW_ATQBAL 0x00080000 26#define PF_FW_ATQH 0x00080300 27#define PF_FW_ATQH_ATQH_M ICE_M(0x3FF, 0) 28#define PF_FW_ATQLEN 0x00080200 29#define PF_FW_ATQLEN_ATQLEN_M ICE_M(0x3FF, 0) 30#define PF_FW_ATQLEN_ATQVFE_M BIT(28) 31#define PF_FW_ATQLEN_ATQOVFL_M BIT(29) 32#define PF_FW_ATQLEN_ATQCRIT_M BIT(30) 33#define VF_MBX_ARQLEN(_VF) (0x0022BC00 + ((_VF) * 4)) 34#define VF_MBX_ATQLEN(_VF) (0x0022A800 + ((_VF) * 4)) 35#define PF_FW_ATQLEN_ATQENABLE_M BIT(31) 36#define PF_FW_ATQT 0x00080400 37#define PF_MBX_ARQBAH 0x0022E400 38#define PF_MBX_ARQBAL 0x0022E380 39#define PF_MBX_ARQH 0x0022E500 40#define PF_MBX_ARQH_ARQH_M ICE_M(0x3FF, 0) 41#define PF_MBX_ARQLEN 0x0022E480 42#define PF_MBX_ARQLEN_ARQLEN_M ICE_M(0x3FF, 0) 43#define PF_MBX_ARQLEN_ARQCRIT_M BIT(30) 44#define PF_MBX_ARQLEN_ARQENABLE_M BIT(31) 45#define PF_MBX_ARQT 0x0022E580 46#define PF_MBX_ATQBAH 0x0022E180 47#define PF_MBX_ATQBAL 0x0022E100 48#define PF_MBX_ATQH 0x0022E280 49#define PF_MBX_ATQH_ATQH_M ICE_M(0x3FF, 0) 50#define PF_MBX_ATQLEN 0x0022E200 51#define PF_MBX_ATQLEN_ATQLEN_M ICE_M(0x3FF, 0) 52#define PF_MBX_ATQLEN_ATQCRIT_M BIT(30) 53#define PF_MBX_ATQLEN_ATQENABLE_M BIT(31) 54#define PF_MBX_ATQT 0x0022E300 55#define PF_SB_ARQBAH 0x0022FF00 56#define PF_SB_ARQBAH_ARQBAH_S 0 57#define PF_SB_ARQBAH_ARQBAH_M ICE_M(0xFFFFFFFF, 0) 58#define PF_SB_ARQBAL 0x0022FE80 59#define PF_SB_ARQBAL_ARQBAL_LSB_S 0 60#define PF_SB_ARQBAL_ARQBAL_LSB_M ICE_M(0x3F, 0) 61#define PF_SB_ARQBAL_ARQBAL_S 6 62#define PF_SB_ARQBAL_ARQBAL_M ICE_M(0x3FFFFFF, 6) 63#define PF_SB_ARQH 0x00230000 64#define PF_SB_ARQH_ARQH_S 0 65#define PF_SB_ARQH_ARQH_M ICE_M(0x3FF, 0) 66#define PF_SB_ARQLEN 0x0022FF80 67#define PF_SB_ARQLEN_ARQLEN_S 0 68#define PF_SB_ARQLEN_ARQLEN_M ICE_M(0x3FF, 0) 69#define PF_SB_ARQLEN_ARQVFE_S 28 70#define PF_SB_ARQLEN_ARQVFE_M BIT(28) 71#define PF_SB_ARQLEN_ARQOVFL_S 29 72#define PF_SB_ARQLEN_ARQOVFL_M BIT(29) 73#define PF_SB_ARQLEN_ARQCRIT_S 30 74#define PF_SB_ARQLEN_ARQCRIT_M BIT(30) 75#define PF_SB_ARQLEN_ARQENABLE_S 31 76#define PF_SB_ARQLEN_ARQENABLE_M BIT(31) 77#define PF_SB_ARQT 0x00230080 78#define PF_SB_ARQT_ARQT_S 0 79#define PF_SB_ARQT_ARQT_M ICE_M(0x3FF, 0) 80#define PF_SB_ATQBAH 0x0022FC80 81#define PF_SB_ATQBAH_ATQBAH_S 0 82#define PF_SB_ATQBAH_ATQBAH_M ICE_M(0xFFFFFFFF, 0) 83#define PF_SB_ATQBAL 0x0022FC00 84#define PF_SB_ATQBAL_ATQBAL_S 6 85#define PF_SB_ATQBAL_ATQBAL_M ICE_M(0x3FFFFFF, 6) 86#define PF_SB_ATQH 0x0022FD80 87#define PF_SB_ATQH_ATQH_S 0 88#define PF_SB_ATQH_ATQH_M ICE_M(0x3FF, 0) 89#define PF_SB_ATQLEN 0x0022FD00 90#define PF_SB_ATQLEN_ATQLEN_S 0 91#define PF_SB_ATQLEN_ATQLEN_M ICE_M(0x3FF, 0) 92#define PF_SB_ATQLEN_ATQVFE_S 28 93#define PF_SB_ATQLEN_ATQVFE_M BIT(28) 94#define PF_SB_ATQLEN_ATQOVFL_S 29 95#define PF_SB_ATQLEN_ATQOVFL_M BIT(29) 96#define PF_SB_ATQLEN_ATQCRIT_S 30 97#define PF_SB_ATQLEN_ATQCRIT_M BIT(30) 98#define PF_SB_ATQLEN_ATQENABLE_S 31 99#define PF_SB_ATQLEN_ATQENABLE_M BIT(31) 100#define PF_SB_ATQT 0x0022FE00 101#define PF_SB_ATQT_ATQT_S 0 102#define PF_SB_ATQT_ATQT_M ICE_M(0x3FF, 0) 103#define PF_SB_REM_DEV_CTL 0x002300F0 104#define PRTDCB_GENC 0x00083000 105#define PRTDCB_GENC_PFCLDA_S 16 106#define PRTDCB_GENC_PFCLDA_M ICE_M(0xFFFF, 16) 107#define PRTDCB_GENS 0x00083020 108#define PRTDCB_GENS_DCBX_STATUS_S 0 109#define PRTDCB_GENS_DCBX_STATUS_M ICE_M(0x7, 0) 110#define PRTDCB_TUP2TC 0x001D26C0 111#define GL_PREEXT_L2_PMASK0(_i) (0x0020F0FC + ((_i) * 4)) 112#define GL_PREEXT_L2_PMASK1(_i) (0x0020F108 + ((_i) * 4)) 113#define GLFLXP_RXDID_FLX_WRD_0(_i) (0x0045c800 + ((_i) * 4)) 114#define GLFLXP_RXDID_FLX_WRD_0_PROT_MDID_S 0 115#define GLFLXP_RXDID_FLX_WRD_0_PROT_MDID_M ICE_M(0xFF, 0) 116#define GLFLXP_RXDID_FLX_WRD_0_RXDID_OPCODE_S 30 117#define GLFLXP_RXDID_FLX_WRD_0_RXDID_OPCODE_M ICE_M(0x3, 30) 118#define GLFLXP_RXDID_FLX_WRD_1(_i) (0x0045c900 + ((_i) * 4)) 119#define GLFLXP_RXDID_FLX_WRD_1_PROT_MDID_S 0 120#define GLFLXP_RXDID_FLX_WRD_1_PROT_MDID_M ICE_M(0xFF, 0) 121#define GLFLXP_RXDID_FLX_WRD_1_RXDID_OPCODE_S 30 122#define GLFLXP_RXDID_FLX_WRD_1_RXDID_OPCODE_M ICE_M(0x3, 30) 123#define GLFLXP_RXDID_FLX_WRD_2(_i) (0x0045ca00 + ((_i) * 4)) 124#define GLFLXP_RXDID_FLX_WRD_2_PROT_MDID_S 0 125#define GLFLXP_RXDID_FLX_WRD_2_PROT_MDID_M ICE_M(0xFF, 0) 126#define GLFLXP_RXDID_FLX_WRD_2_RXDID_OPCODE_S 30 127#define GLFLXP_RXDID_FLX_WRD_2_RXDID_OPCODE_M ICE_M(0x3, 30) 128#define GLFLXP_RXDID_FLX_WRD_3(_i) (0x0045cb00 + ((_i) * 4)) 129#define GLFLXP_RXDID_FLX_WRD_3_PROT_MDID_S 0 130#define GLFLXP_RXDID_FLX_WRD_3_PROT_MDID_M ICE_M(0xFF, 0) 131#define GLFLXP_RXDID_FLX_WRD_3_RXDID_OPCODE_S 30 132#define GLFLXP_RXDID_FLX_WRD_3_RXDID_OPCODE_M ICE_M(0x3, 30) 133#define QRXFLXP_CNTXT(_QRX) (0x00480000 + ((_QRX) * 4)) 134#define QRXFLXP_CNTXT_RXDID_IDX_S 0 135#define QRXFLXP_CNTXT_RXDID_IDX_M ICE_M(0x3F, 0) 136#define QRXFLXP_CNTXT_RXDID_PRIO_S 8 137#define QRXFLXP_CNTXT_RXDID_PRIO_M ICE_M(0x7, 8) 138#define QRXFLXP_CNTXT_TS_M BIT(11) 139#define GLGEN_CLKSTAT_SRC_PSM_CLK_SRC_S 4 140#define GLGEN_CLKSTAT_SRC_PSM_CLK_SRC_M ICE_M(0x3, 4) 141#define GLGEN_CLKSTAT_SRC 0x000B826C 142#define GLGEN_GPIO_CTL(_i) (0x000880C8 + ((_i) * 4)) 143#define GLGEN_GPIO_CTL_PIN_DIR_M BIT(4) 144#define GLGEN_GPIO_CTL_PIN_FUNC_S 8 145#define GLGEN_GPIO_CTL_PIN_FUNC_M ICE_M(0xF, 8) 146#define GLGEN_RSTAT 0x000B8188 147#define GLGEN_RSTAT_DEVSTATE_M ICE_M(0x3, 0) 148#define GLGEN_RSTCTL 0x000B8180 149#define GLGEN_RSTCTL_GRSTDEL_S 0 150#define GLGEN_RSTCTL_GRSTDEL_M ICE_M(0x3F, GLGEN_RSTCTL_GRSTDEL_S) 151#define GLGEN_RSTAT_RESET_TYPE_S 2 152#define GLGEN_RSTAT_RESET_TYPE_M ICE_M(0x3, 2) 153#define GLGEN_RTRIG 0x000B8190 154#define GLGEN_RTRIG_CORER_M BIT(0) 155#define GLGEN_RTRIG_GLOBR_M BIT(1) 156#define GLGEN_STAT 0x000B612C 157#define GLGEN_VFLRSTAT(_i) (0x00093A04 + ((_i) * 4)) 158#define PFGEN_CTRL 0x00091000 159#define PFGEN_CTRL_PFSWR_M BIT(0) 160#define PFGEN_STATE 0x00088000 161#define PRTGEN_STATUS 0x000B8100 162#define VFGEN_RSTAT(_VF) (0x00074000 + ((_VF) * 4)) 163#define VPGEN_VFRSTAT(_VF) (0x00090800 + ((_VF) * 4)) 164#define VPGEN_VFRSTAT_VFRD_M BIT(0) 165#define VPGEN_VFRTRIG(_VF) (0x00090000 + ((_VF) * 4)) 166#define VPGEN_VFRTRIG_VFSWR_M BIT(0) 167#define GLINT_CTL 0x0016CC54 168#define GLINT_CTL_DIS_AUTOMASK_M BIT(0) 169#define GLINT_CTL_ITR_GRAN_200_S 16 170#define GLINT_CTL_ITR_GRAN_200_M ICE_M(0xF, 16) 171#define GLINT_CTL_ITR_GRAN_100_S 20 172#define GLINT_CTL_ITR_GRAN_100_M ICE_M(0xF, 20) 173#define GLINT_CTL_ITR_GRAN_50_S 24 174#define GLINT_CTL_ITR_GRAN_50_M ICE_M(0xF, 24) 175#define GLINT_CTL_ITR_GRAN_25_S 28 176#define GLINT_CTL_ITR_GRAN_25_M ICE_M(0xF, 28) 177#define GLINT_DYN_CTL(_INT) (0x00160000 + ((_INT) * 4)) 178#define GLINT_DYN_CTL_INTENA_M BIT(0) 179#define GLINT_DYN_CTL_CLEARPBA_M BIT(1) 180#define GLINT_DYN_CTL_SWINT_TRIG_M BIT(2) 181#define GLINT_DYN_CTL_ITR_INDX_S 3 182#define GLINT_DYN_CTL_ITR_INDX_M ICE_M(0x3, 3) 183#define GLINT_DYN_CTL_INTERVAL_S 5 184#define GLINT_DYN_CTL_INTERVAL_M ICE_M(0xFFF, 5) 185#define GLINT_DYN_CTL_SW_ITR_INDX_ENA_M BIT(24) 186#define GLINT_DYN_CTL_SW_ITR_INDX_S 25 187#define GLINT_DYN_CTL_SW_ITR_INDX_M ICE_M(0x3, 25) 188#define GLINT_DYN_CTL_WB_ON_ITR_M BIT(30) 189#define GLINT_DYN_CTL_INTENA_MSK_M BIT(31) 190#define GLINT_ITR(_i, _INT) (0x00154000 + ((_i) * 8192 + (_INT) * 4)) 191#define GLINT_RATE(_INT) (0x0015A000 + ((_INT) * 4)) 192#define GLINT_RATE_INTRL_ENA_M BIT(6) 193#define GLINT_VECT2FUNC(_INT) (0x00162000 + ((_INT) * 4)) 194#define GLINT_VECT2FUNC_VF_NUM_S 0 195#define GLINT_VECT2FUNC_VF_NUM_M ICE_M(0xFF, 0) 196#define GLINT_VECT2FUNC_PF_NUM_S 12 197#define GLINT_VECT2FUNC_PF_NUM_M ICE_M(0x7, 12) 198#define GLINT_VECT2FUNC_IS_PF_S 16 199#define GLINT_VECT2FUNC_IS_PF_M BIT(16) 200#define PFINT_FW_CTL 0x0016C800 201#define PFINT_FW_CTL_MSIX_INDX_M ICE_M(0x7FF, 0) 202#define PFINT_FW_CTL_ITR_INDX_S 11 203#define PFINT_FW_CTL_ITR_INDX_M ICE_M(0x3, 11) 204#define PFINT_FW_CTL_CAUSE_ENA_M BIT(30) 205#define PFINT_MBX_CTL 0x0016B280 206#define PFINT_MBX_CTL_MSIX_INDX_M ICE_M(0x7FF, 0) 207#define PFINT_MBX_CTL_ITR_INDX_S 11 208#define PFINT_MBX_CTL_ITR_INDX_M ICE_M(0x3, 11) 209#define PFINT_MBX_CTL_CAUSE_ENA_M BIT(30) 210#define PFINT_OICR 0x0016CA00 211#define PFINT_OICR_TSYN_TX_M BIT(11) 212#define PFINT_OICR_TSYN_EVNT_M BIT(12) 213#define PFINT_OICR_ECC_ERR_M BIT(16) 214#define PFINT_OICR_MAL_DETECT_M BIT(19) 215#define PFINT_OICR_GRST_M BIT(20) 216#define PFINT_OICR_PCI_EXCEPTION_M BIT(21) 217#define PFINT_OICR_HMC_ERR_M BIT(26) 218#define PFINT_OICR_PE_PUSH_M BIT(27) 219#define PFINT_OICR_PE_CRITERR_M BIT(28) 220#define PFINT_OICR_VFLR_M BIT(29) 221#define PFINT_OICR_SWINT_M BIT(31) 222#define PFINT_OICR_CTL 0x0016CA80 223#define PFINT_OICR_CTL_MSIX_INDX_M ICE_M(0x7FF, 0) 224#define PFINT_OICR_CTL_ITR_INDX_S 11 225#define PFINT_OICR_CTL_ITR_INDX_M ICE_M(0x3, 11) 226#define PFINT_OICR_CTL_CAUSE_ENA_M BIT(30) 227#define PFINT_OICR_ENA 0x0016C900 228#define PFINT_SB_CTL 0x0016B600 229#define PFINT_SB_CTL_MSIX_INDX_M ICE_M(0x7FF, 0) 230#define PFINT_SB_CTL_CAUSE_ENA_M BIT(30) 231#define QINT_RQCTL(_QRX) (0x00150000 + ((_QRX) * 4)) 232#define QINT_RQCTL_MSIX_INDX_S 0 233#define QINT_RQCTL_MSIX_INDX_M ICE_M(0x7FF, 0) 234#define QINT_RQCTL_ITR_INDX_S 11 235#define QINT_RQCTL_ITR_INDX_M ICE_M(0x3, 11) 236#define QINT_RQCTL_CAUSE_ENA_M BIT(30) 237#define QINT_TQCTL(_DBQM) (0x00140000 + ((_DBQM) * 4)) 238#define QINT_TQCTL_MSIX_INDX_S 0 239#define QINT_TQCTL_MSIX_INDX_M ICE_M(0x7FF, 0) 240#define QINT_TQCTL_ITR_INDX_S 11 241#define QINT_TQCTL_ITR_INDX_M ICE_M(0x3, 11) 242#define QINT_TQCTL_CAUSE_ENA_M BIT(30) 243#define VPINT_ALLOC(_VF) (0x001D1000 + ((_VF) * 4)) 244#define VPINT_ALLOC_FIRST_S 0 245#define VPINT_ALLOC_FIRST_M ICE_M(0x7FF, 0) 246#define VPINT_ALLOC_LAST_S 12 247#define VPINT_ALLOC_LAST_M ICE_M(0x7FF, 12) 248#define VPINT_ALLOC_VALID_M BIT(31) 249#define VPINT_ALLOC_PCI(_VF) (0x0009D000 + ((_VF) * 4)) 250#define VPINT_ALLOC_PCI_FIRST_S 0 251#define VPINT_ALLOC_PCI_FIRST_M ICE_M(0x7FF, 0) 252#define VPINT_ALLOC_PCI_LAST_S 12 253#define VPINT_ALLOC_PCI_LAST_M ICE_M(0x7FF, 12) 254#define VPINT_ALLOC_PCI_VALID_M BIT(31) 255#define VPINT_MBX_CTL(_VSI) (0x0016A000 + ((_VSI) * 4)) 256#define VPINT_MBX_CTL_CAUSE_ENA_M BIT(30) 257#define GLLAN_RCTL_0 0x002941F8 258#define QRX_CONTEXT(_i, _QRX) (0x00280000 + ((_i) * 8192 + (_QRX) * 4)) 259#define QRX_CTRL(_QRX) (0x00120000 + ((_QRX) * 4)) 260#define QRX_CTRL_MAX_INDEX 2047 261#define QRX_CTRL_QENA_REQ_S 0 262#define QRX_CTRL_QENA_REQ_M BIT(0) 263#define QRX_CTRL_QENA_STAT_S 2 264#define QRX_CTRL_QENA_STAT_M BIT(2) 265#define QRX_ITR(_QRX) (0x00292000 + ((_QRX) * 4)) 266#define QRX_TAIL(_QRX) (0x00290000 + ((_QRX) * 4)) 267#define QRX_TAIL_MAX_INDEX 2047 268#define QRX_TAIL_TAIL_S 0 269#define QRX_TAIL_TAIL_M ICE_M(0x1FFF, 0) 270#define VPLAN_RX_QBASE(_VF) (0x00072000 + ((_VF) * 4)) 271#define VPLAN_RX_QBASE_VFFIRSTQ_S 0 272#define VPLAN_RX_QBASE_VFFIRSTQ_M ICE_M(0x7FF, 0) 273#define VPLAN_RX_QBASE_VFNUMQ_S 16 274#define VPLAN_RX_QBASE_VFNUMQ_M ICE_M(0xFF, 16) 275#define VPLAN_RXQ_MAPENA(_VF) (0x00073000 + ((_VF) * 4)) 276#define VPLAN_RXQ_MAPENA_RX_ENA_M BIT(0) 277#define VPLAN_TX_QBASE(_VF) (0x001D1800 + ((_VF) * 4)) 278#define VPLAN_TX_QBASE_VFFIRSTQ_S 0 279#define VPLAN_TX_QBASE_VFFIRSTQ_M ICE_M(0x3FFF, 0) 280#define VPLAN_TX_QBASE_VFNUMQ_S 16 281#define VPLAN_TX_QBASE_VFNUMQ_M ICE_M(0xFF, 16) 282#define VPLAN_TXQ_MAPENA(_VF) (0x00073800 + ((_VF) * 4)) 283#define VPLAN_TXQ_MAPENA_TX_ENA_M BIT(0) 284#define PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(_i) (0x001E36E0 + ((_i) * 32)) 285#define PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX 8 286#define PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M ICE_M(0xFFFF, 0) 287#define PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(_i) (0x001E3800 + ((_i) * 32)) 288#define PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M ICE_M(0xFFFF, 0) 289#define GL_MDCK_TX_TDPU 0x00049348 290#define GL_MDCK_TX_TDPU_RCU_ANTISPOOF_ITR_DIS_M BIT(1) 291#define GL_MDET_RX 0x00294C00 292#define GL_MDET_RX_QNUM_S 0 293#define GL_MDET_RX_QNUM_M ICE_M(0x7FFF, 0) 294#define GL_MDET_RX_VF_NUM_S 15 295#define GL_MDET_RX_VF_NUM_M ICE_M(0xFF, 15) 296#define GL_MDET_RX_PF_NUM_S 23 297#define GL_MDET_RX_PF_NUM_M ICE_M(0x7, 23) 298#define GL_MDET_RX_MAL_TYPE_S 26 299#define GL_MDET_RX_MAL_TYPE_M ICE_M(0x1F, 26) 300#define GL_MDET_RX_VALID_M BIT(31) 301#define GL_MDET_TX_PQM 0x002D2E00 302#define GL_MDET_TX_PQM_PF_NUM_S 0 303#define GL_MDET_TX_PQM_PF_NUM_M ICE_M(0x7, 0) 304#define GL_MDET_TX_PQM_VF_NUM_S 4 305#define GL_MDET_TX_PQM_VF_NUM_M ICE_M(0xFF, 4) 306#define GL_MDET_TX_PQM_QNUM_S 12 307#define GL_MDET_TX_PQM_QNUM_M ICE_M(0x3FFF, 12) 308#define GL_MDET_TX_PQM_MAL_TYPE_S 26 309#define GL_MDET_TX_PQM_MAL_TYPE_M ICE_M(0x1F, 26) 310#define GL_MDET_TX_PQM_VALID_M BIT(31) 311#define GL_MDET_TX_TCLAN 0x000FC068 312#define GL_MDET_TX_TCLAN_QNUM_S 0 313#define GL_MDET_TX_TCLAN_QNUM_M ICE_M(0x7FFF, 0) 314#define GL_MDET_TX_TCLAN_VF_NUM_S 15 315#define GL_MDET_TX_TCLAN_VF_NUM_M ICE_M(0xFF, 15) 316#define GL_MDET_TX_TCLAN_PF_NUM_S 23 317#define GL_MDET_TX_TCLAN_PF_NUM_M ICE_M(0x7, 23) 318#define GL_MDET_TX_TCLAN_MAL_TYPE_S 26 319#define GL_MDET_TX_TCLAN_MAL_TYPE_M ICE_M(0x1F, 26) 320#define GL_MDET_TX_TCLAN_VALID_M BIT(31) 321#define PF_MDET_RX 0x00294280 322#define PF_MDET_RX_VALID_M BIT(0) 323#define PF_MDET_TX_PQM 0x002D2C80 324#define PF_MDET_TX_PQM_VALID_M BIT(0) 325#define PF_MDET_TX_TCLAN 0x000FC000 326#define PF_MDET_TX_TCLAN_VALID_M BIT(0) 327#define VP_MDET_RX(_VF) (0x00294400 + ((_VF) * 4)) 328#define VP_MDET_RX_VALID_M BIT(0) 329#define VP_MDET_TX_PQM(_VF) (0x002D2000 + ((_VF) * 4)) 330#define VP_MDET_TX_PQM_VALID_M BIT(0) 331#define VP_MDET_TX_TCLAN(_VF) (0x000FB800 + ((_VF) * 4)) 332#define VP_MDET_TX_TCLAN_VALID_M BIT(0) 333#define VP_MDET_TX_TDPU(_VF) (0x00040000 + ((_VF) * 4)) 334#define VP_MDET_TX_TDPU_VALID_M BIT(0) 335#define GLNVM_FLA 0x000B6108 336#define GLNVM_FLA_LOCKED_M BIT(6) 337#define GLNVM_GENS 0x000B6100 338#define GLNVM_GENS_SR_SIZE_S 5 339#define GLNVM_GENS_SR_SIZE_M ICE_M(0x7, 5) 340#define GLNVM_ULD 0x000B6008 341#define GLNVM_ULD_PCIER_DONE_M BIT(0) 342#define GLNVM_ULD_PCIER_DONE_1_M BIT(1) 343#define GLNVM_ULD_CORER_DONE_M BIT(3) 344#define GLNVM_ULD_GLOBR_DONE_M BIT(4) 345#define GLNVM_ULD_POR_DONE_M BIT(5) 346#define GLNVM_ULD_POR_DONE_1_M BIT(8) 347#define GLNVM_ULD_PCIER_DONE_2_M BIT(9) 348#define GLNVM_ULD_PE_DONE_M BIT(10) 349#define GLPCI_CNF2 0x000BE004 350#define GLPCI_CNF2_CACHELINE_SIZE_M BIT(1) 351#define PF_FUNC_RID 0x0009E880 352#define PF_FUNC_RID_FUNC_NUM_S 0 353#define PF_FUNC_RID_FUNC_NUM_M ICE_M(0x7, 0) 354#define PF_PCI_CIAA 0x0009E580 355#define PF_PCI_CIAA_VF_NUM_S 12 356#define PF_PCI_CIAD 0x0009E500 357#define GL_PWR_MODE_CTL 0x000B820C 358#define GL_PWR_MODE_CTL_CAR_MAX_BW_S 30 359#define GL_PWR_MODE_CTL_CAR_MAX_BW_M ICE_M(0x3, 30) 360#define GLQF_FD_CNT 0x00460018 361#define GLQF_FD_CNT_FD_BCNT_S 16 362#define GLQF_FD_CNT_FD_BCNT_M ICE_M(0x7FFF, 16) 363#define GLQF_FD_SIZE 0x00460010 364#define GLQF_FD_SIZE_FD_GSIZE_S 0 365#define GLQF_FD_SIZE_FD_GSIZE_M ICE_M(0x7FFF, 0) 366#define GLQF_FD_SIZE_FD_BSIZE_S 16 367#define GLQF_FD_SIZE_FD_BSIZE_M ICE_M(0x7FFF, 16) 368#define GLQF_FDINSET(_i, _j) (0x00412000 + ((_i) * 4 + (_j) * 512)) 369#define GLQF_FDMASK(_i) (0x00410800 + ((_i) * 4)) 370#define GLQF_FDMASK_MAX_INDEX 31 371#define GLQF_FDMASK_MSK_INDEX_S 0 372#define GLQF_FDMASK_MSK_INDEX_M ICE_M(0x1F, 0) 373#define GLQF_FDMASK_MASK_S 16 374#define GLQF_FDMASK_MASK_M ICE_M(0xFFFF, 16) 375#define GLQF_FDMASK_SEL(_i) (0x00410400 + ((_i) * 4)) 376#define GLQF_FDSWAP(_i, _j) (0x00413000 + ((_i) * 4 + (_j) * 512)) 377#define GLQF_HMASK(_i) (0x0040FC00 + ((_i) * 4)) 378#define GLQF_HMASK_MAX_INDEX 31 379#define GLQF_HMASK_MSK_INDEX_S 0 380#define GLQF_HMASK_MSK_INDEX_M ICE_M(0x1F, 0) 381#define GLQF_HMASK_MASK_S 16 382#define GLQF_HMASK_MASK_M ICE_M(0xFFFF, 16) 383#define GLQF_HMASK_SEL(_i) (0x00410000 + ((_i) * 4)) 384#define GLQF_HMASK_SEL_MAX_INDEX 127 385#define GLQF_HMASK_SEL_MASK_SEL_S 0 386#define PFQF_FD_ENA 0x0043A000 387#define PFQF_FD_ENA_FD_ENA_M BIT(0) 388#define PFQF_FD_SIZE 0x00460100 389#define GLDCB_RTCTQ_RXQNUM_S 0 390#define GLDCB_RTCTQ_RXQNUM_M ICE_M(0x7FF, 0) 391#define GLPRT_BPRCL(_i) (0x00381380 + ((_i) * 8)) 392#define GLPRT_BPTCL(_i) (0x00381240 + ((_i) * 8)) 393#define GLPRT_CRCERRS(_i) (0x00380100 + ((_i) * 8)) 394#define GLPRT_GORCL(_i) (0x00380000 + ((_i) * 8)) 395#define GLPRT_GOTCL(_i) (0x00380B40 + ((_i) * 8)) 396#define GLPRT_ILLERRC(_i) (0x003801C0 + ((_i) * 8)) 397#define GLPRT_LXOFFRXC(_i) (0x003802C0 + ((_i) * 8)) 398#define GLPRT_LXOFFTXC(_i) (0x00381180 + ((_i) * 8)) 399#define GLPRT_LXONRXC(_i) (0x00380280 + ((_i) * 8)) 400#define GLPRT_LXONTXC(_i) (0x00381140 + ((_i) * 8)) 401#define GLPRT_MLFC(_i) (0x00380040 + ((_i) * 8)) 402#define GLPRT_MPRCL(_i) (0x00381340 + ((_i) * 8)) 403#define GLPRT_MPTCL(_i) (0x00381200 + ((_i) * 8)) 404#define GLPRT_MRFC(_i) (0x00380080 + ((_i) * 8)) 405#define GLPRT_PRC1023L(_i) (0x00380A00 + ((_i) * 8)) 406#define GLPRT_PRC127L(_i) (0x00380940 + ((_i) * 8)) 407#define GLPRT_PRC1522L(_i) (0x00380A40 + ((_i) * 8)) 408#define GLPRT_PRC255L(_i) (0x00380980 + ((_i) * 8)) 409#define GLPRT_PRC511L(_i) (0x003809C0 + ((_i) * 8)) 410#define GLPRT_PRC64L(_i) (0x00380900 + ((_i) * 8)) 411#define GLPRT_PRC9522L(_i) (0x00380A80 + ((_i) * 8)) 412#define GLPRT_PTC1023L(_i) (0x00380C80 + ((_i) * 8)) 413#define GLPRT_PTC127L(_i) (0x00380BC0 + ((_i) * 8)) 414#define GLPRT_PTC1522L(_i) (0x00380CC0 + ((_i) * 8)) 415#define GLPRT_PTC255L(_i) (0x00380C00 + ((_i) * 8)) 416#define GLPRT_PTC511L(_i) (0x00380C40 + ((_i) * 8)) 417#define GLPRT_PTC64L(_i) (0x00380B80 + ((_i) * 8)) 418#define GLPRT_PTC9522L(_i) (0x00380D00 + ((_i) * 8)) 419#define GLPRT_PXOFFRXC(_i, _j) (0x00380500 + ((_i) * 8 + (_j) * 64)) 420#define GLPRT_PXOFFTXC(_i, _j) (0x00380F40 + ((_i) * 8 + (_j) * 64)) 421#define GLPRT_PXONRXC(_i, _j) (0x00380300 + ((_i) * 8 + (_j) * 64)) 422#define GLPRT_PXONTXC(_i, _j) (0x00380D40 + ((_i) * 8 + (_j) * 64)) 423#define GLPRT_RFC(_i) (0x00380AC0 + ((_i) * 8)) 424#define GLPRT_RJC(_i) (0x00380B00 + ((_i) * 8)) 425#define GLPRT_RLEC(_i) (0x00380140 + ((_i) * 8)) 426#define GLPRT_ROC(_i) (0x00380240 + ((_i) * 8)) 427#define GLPRT_RUC(_i) (0x00380200 + ((_i) * 8)) 428#define GLPRT_RXON2OFFCNT(_i, _j) (0x00380700 + ((_i) * 8 + (_j) * 64)) 429#define GLPRT_TDOLD(_i) (0x00381280 + ((_i) * 8)) 430#define GLPRT_UPRCL(_i) (0x00381300 + ((_i) * 8)) 431#define GLPRT_UPTCL(_i) (0x003811C0 + ((_i) * 8)) 432#define GLSTAT_FD_CNT0L(_i) (0x003A0000 + ((_i) * 8)) 433#define GLV_BPRCL(_i) (0x003B6000 + ((_i) * 8)) 434#define GLV_BPTCL(_i) (0x0030E000 + ((_i) * 8)) 435#define GLV_GORCL(_i) (0x003B0000 + ((_i) * 8)) 436#define GLV_GOTCL(_i) (0x00300000 + ((_i) * 8)) 437#define GLV_MPRCL(_i) (0x003B4000 + ((_i) * 8)) 438#define GLV_MPTCL(_i) (0x0030C000 + ((_i) * 8)) 439#define GLV_RDPC(_i) (0x00294C04 + ((_i) * 4)) 440#define GLV_TEPC(_VSI) (0x00312000 + ((_VSI) * 4)) 441#define GLV_UPRCL(_i) (0x003B2000 + ((_i) * 8)) 442#define GLV_UPTCL(_i) (0x0030A000 + ((_i) * 8)) 443#define PRTRPB_RDPC 0x000AC260 444#define GLHH_ART_CTL 0x000A41D4 445#define GLHH_ART_CTL_ACTIVE_M BIT(0) 446#define GLHH_ART_TIME_H 0x000A41D8 447#define GLHH_ART_TIME_L 0x000A41DC 448#define GLTSYN_AUX_IN_0(_i) (0x000889D8 + ((_i) * 4)) 449#define GLTSYN_AUX_IN_0_INT_ENA_M BIT(4) 450#define GLTSYN_AUX_OUT_0(_i) (0x00088998 + ((_i) * 4)) 451#define GLTSYN_AUX_OUT_0_OUT_ENA_M BIT(0) 452#define GLTSYN_AUX_OUT_0_OUTMOD_M ICE_M(0x3, 1) 453#define GLTSYN_CLKO_0(_i) (0x000889B8 + ((_i) * 4)) 454#define GLTSYN_CMD 0x00088810 455#define GLTSYN_CMD_SYNC 0x00088814 456#define GLTSYN_ENA(_i) (0x00088808 + ((_i) * 4)) 457#define GLTSYN_ENA_TSYN_ENA_M BIT(0) 458#define GLTSYN_EVNT_H_0(_i) (0x00088970 + ((_i) * 4)) 459#define GLTSYN_EVNT_L_0(_i) (0x00088968 + ((_i) * 4)) 460#define GLTSYN_HHTIME_H(_i) (0x00088900 + ((_i) * 4)) 461#define GLTSYN_HHTIME_L(_i) (0x000888F8 + ((_i) * 4)) 462#define GLTSYN_INCVAL_H(_i) (0x00088920 + ((_i) * 4)) 463#define GLTSYN_INCVAL_L(_i) (0x00088918 + ((_i) * 4)) 464#define GLTSYN_SHADJ_H(_i) (0x00088910 + ((_i) * 4)) 465#define GLTSYN_SHADJ_L(_i) (0x00088908 + ((_i) * 4)) 466#define GLTSYN_SHTIME_0(_i) (0x000888E0 + ((_i) * 4)) 467#define GLTSYN_SHTIME_H(_i) (0x000888F0 + ((_i) * 4)) 468#define GLTSYN_SHTIME_L(_i) (0x000888E8 + ((_i) * 4)) 469#define GLTSYN_STAT(_i) (0x000888C0 + ((_i) * 4)) 470#define GLTSYN_STAT_EVENT0_M BIT(0) 471#define GLTSYN_STAT_EVENT1_M BIT(1) 472#define GLTSYN_STAT_EVENT2_M BIT(2) 473#define GLTSYN_SYNC_DLAY 0x00088818 474#define GLTSYN_TGT_H_0(_i) (0x00088930 + ((_i) * 4)) 475#define GLTSYN_TGT_L_0(_i) (0x00088928 + ((_i) * 4)) 476#define GLTSYN_TIME_H(_i) (0x000888D8 + ((_i) * 4)) 477#define GLTSYN_TIME_L(_i) (0x000888D0 + ((_i) * 4)) 478#define PFHH_SEM 0x000A4200 /* Reset Source: PFR */ 479#define PFHH_SEM_BUSY_M BIT(0) 480#define PFTSYN_SEM 0x00088880 481#define PFTSYN_SEM_BUSY_M BIT(0) 482#define VSIQF_FD_CNT(_VSI) (0x00464000 + ((_VSI) * 4)) 483#define VSIQF_FD_CNT_FD_GCNT_S 0 484#define VSIQF_FD_CNT_FD_GCNT_M ICE_M(0x3FFF, 0) 485#define VSIQF_FD_CNT_FD_BCNT_S 16 486#define VSIQF_FD_CNT_FD_BCNT_M ICE_M(0x3FFF, 16) 487#define VSIQF_FD_SIZE(_VSI) (0x00462000 + ((_VSI) * 4)) 488#define VSIQF_HKEY_MAX_INDEX 12 489#define VSIQF_HLUT_MAX_INDEX 15 490#define PFPM_APM 0x000B8080 491#define PFPM_APM_APME_M BIT(0) 492#define PFPM_WUFC 0x0009DC00 493#define PFPM_WUFC_MAG_M BIT(1) 494#define PFPM_WUS 0x0009DB80 495#define PFPM_WUS_LNKC_M BIT(0) 496#define PFPM_WUS_MAG_M BIT(1) 497#define PFPM_WUS_MNG_M BIT(3) 498#define PFPM_WUS_FW_RST_WK_M BIT(31) 499#define VFINT_DYN_CTLN(_i) (0x00003800 + ((_i) * 4)) 500#define VFINT_DYN_CTLN_CLEARPBA_M BIT(1) 501 502#endif /* _ICE_HW_AUTOGEN_H_ */