cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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ice_txrx.h (13127B)


      1/* SPDX-License-Identifier: GPL-2.0 */
      2/* Copyright (c) 2018, Intel Corporation. */
      3
      4#ifndef _ICE_TXRX_H_
      5#define _ICE_TXRX_H_
      6
      7#include "ice_type.h"
      8
      9#define ICE_DFLT_IRQ_WORK	256
     10#define ICE_RXBUF_3072		3072
     11#define ICE_RXBUF_2048		2048
     12#define ICE_RXBUF_1536		1536
     13#define ICE_MAX_CHAINED_RX_BUFS	5
     14#define ICE_MAX_BUF_TXD		8
     15#define ICE_MIN_TX_LEN		17
     16
     17/* The size limit for a transmit buffer in a descriptor is (16K - 1).
     18 * In order to align with the read requests we will align the value to
     19 * the nearest 4K which represents our maximum read request size.
     20 */
     21#define ICE_MAX_READ_REQ_SIZE	4096
     22#define ICE_MAX_DATA_PER_TXD	(16 * 1024 - 1)
     23#define ICE_MAX_DATA_PER_TXD_ALIGNED \
     24	(~(ICE_MAX_READ_REQ_SIZE - 1) & ICE_MAX_DATA_PER_TXD)
     25
     26#define ICE_MAX_TXQ_PER_TXQG	128
     27
     28/* Attempt to maximize the headroom available for incoming frames. We use a 2K
     29 * buffer for MTUs <= 1500 and need 1536/1534 to store the data for the frame.
     30 * This leaves us with 512 bytes of room.  From that we need to deduct the
     31 * space needed for the shared info and the padding needed to IP align the
     32 * frame.
     33 *
     34 * Note: For cache line sizes 256 or larger this value is going to end
     35 *	 up negative.  In these cases we should fall back to the legacy
     36 *	 receive path.
     37 */
     38#if (PAGE_SIZE < 8192)
     39#define ICE_2K_TOO_SMALL_WITH_PADDING \
     40	((unsigned int)(NET_SKB_PAD + ICE_RXBUF_1536) > \
     41			SKB_WITH_OVERHEAD(ICE_RXBUF_2048))
     42
     43/**
     44 * ice_compute_pad - compute the padding
     45 * @rx_buf_len: buffer length
     46 *
     47 * Figure out the size of half page based on given buffer length and
     48 * then subtract the skb_shared_info followed by subtraction of the
     49 * actual buffer length; this in turn results in the actual space that
     50 * is left for padding usage
     51 */
     52static inline int ice_compute_pad(int rx_buf_len)
     53{
     54	int half_page_size;
     55
     56	half_page_size = ALIGN(rx_buf_len, PAGE_SIZE / 2);
     57	return SKB_WITH_OVERHEAD(half_page_size) - rx_buf_len;
     58}
     59
     60/**
     61 * ice_skb_pad - determine the padding that we can supply
     62 *
     63 * Figure out the right Rx buffer size and based on that calculate the
     64 * padding
     65 */
     66static inline int ice_skb_pad(void)
     67{
     68	int rx_buf_len;
     69
     70	/* If a 2K buffer cannot handle a standard Ethernet frame then
     71	 * optimize padding for a 3K buffer instead of a 1.5K buffer.
     72	 *
     73	 * For a 3K buffer we need to add enough padding to allow for
     74	 * tailroom due to NET_IP_ALIGN possibly shifting us out of
     75	 * cache-line alignment.
     76	 */
     77	if (ICE_2K_TOO_SMALL_WITH_PADDING)
     78		rx_buf_len = ICE_RXBUF_3072 + SKB_DATA_ALIGN(NET_IP_ALIGN);
     79	else
     80		rx_buf_len = ICE_RXBUF_1536;
     81
     82	/* if needed make room for NET_IP_ALIGN */
     83	rx_buf_len -= NET_IP_ALIGN;
     84
     85	return ice_compute_pad(rx_buf_len);
     86}
     87
     88#define ICE_SKB_PAD ice_skb_pad()
     89#else
     90#define ICE_2K_TOO_SMALL_WITH_PADDING false
     91#define ICE_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN)
     92#endif
     93
     94/* We are assuming that the cache line is always 64 Bytes here for ice.
     95 * In order to make sure that is a correct assumption there is a check in probe
     96 * to print a warning if the read from GLPCI_CNF2 tells us that the cache line
     97 * size is 128 bytes. We do it this way because we do not want to read the
     98 * GLPCI_CNF2 register or a variable containing the value on every pass through
     99 * the Tx path.
    100 */
    101#define ICE_CACHE_LINE_BYTES		64
    102#define ICE_DESCS_PER_CACHE_LINE	(ICE_CACHE_LINE_BYTES / \
    103					 sizeof(struct ice_tx_desc))
    104#define ICE_DESCS_FOR_CTX_DESC		1
    105#define ICE_DESCS_FOR_SKB_DATA_PTR	1
    106/* Tx descriptors needed, worst case */
    107#define DESC_NEEDED (MAX_SKB_FRAGS + ICE_DESCS_FOR_CTX_DESC + \
    108		     ICE_DESCS_PER_CACHE_LINE + ICE_DESCS_FOR_SKB_DATA_PTR)
    109#define ICE_DESC_UNUSED(R)	\
    110	(u16)((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
    111	      (R)->next_to_clean - (R)->next_to_use - 1)
    112
    113#define ICE_RING_QUARTER(R) ((R)->count >> 2)
    114
    115#define ICE_TX_FLAGS_TSO	BIT(0)
    116#define ICE_TX_FLAGS_HW_VLAN	BIT(1)
    117#define ICE_TX_FLAGS_SW_VLAN	BIT(2)
    118/* ICE_TX_FLAGS_DUMMY_PKT is used to mark dummy packets that should be
    119 * freed instead of returned like skb packets.
    120 */
    121#define ICE_TX_FLAGS_DUMMY_PKT	BIT(3)
    122#define ICE_TX_FLAGS_TSYN	BIT(4)
    123#define ICE_TX_FLAGS_IPV4	BIT(5)
    124#define ICE_TX_FLAGS_IPV6	BIT(6)
    125#define ICE_TX_FLAGS_TUNNEL	BIT(7)
    126#define ICE_TX_FLAGS_HW_OUTER_SINGLE_VLAN	BIT(8)
    127#define ICE_TX_FLAGS_VLAN_M	0xffff0000
    128#define ICE_TX_FLAGS_VLAN_PR_M	0xe0000000
    129#define ICE_TX_FLAGS_VLAN_PR_S	29
    130#define ICE_TX_FLAGS_VLAN_S	16
    131
    132#define ICE_XDP_PASS		0
    133#define ICE_XDP_CONSUMED	BIT(0)
    134#define ICE_XDP_TX		BIT(1)
    135#define ICE_XDP_REDIR		BIT(2)
    136#define ICE_XDP_EXIT		BIT(3)
    137
    138#define ICE_RX_DMA_ATTR \
    139	(DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
    140
    141#define ICE_ETH_PKT_HDR_PAD	(ETH_HLEN + ETH_FCS_LEN + (VLAN_HLEN * 2))
    142
    143#define ICE_TXD_LAST_DESC_CMD (ICE_TX_DESC_CMD_EOP | ICE_TX_DESC_CMD_RS)
    144
    145struct ice_tx_buf {
    146	struct ice_tx_desc *next_to_watch;
    147	union {
    148		struct sk_buff *skb;
    149		void *raw_buf; /* used for XDP */
    150	};
    151	unsigned int bytecount;
    152	unsigned short gso_segs;
    153	u32 tx_flags;
    154	DEFINE_DMA_UNMAP_LEN(len);
    155	DEFINE_DMA_UNMAP_ADDR(dma);
    156};
    157
    158struct ice_tx_offload_params {
    159	u64 cd_qw1;
    160	struct ice_tx_ring *tx_ring;
    161	u32 td_cmd;
    162	u32 td_offset;
    163	u32 td_l2tag1;
    164	u32 cd_tunnel_params;
    165	u16 cd_l2tag2;
    166	u8 header_len;
    167};
    168
    169struct ice_rx_buf {
    170	dma_addr_t dma;
    171	struct page *page;
    172	unsigned int page_offset;
    173	u16 pagecnt_bias;
    174};
    175
    176struct ice_q_stats {
    177	u64 pkts;
    178	u64 bytes;
    179};
    180
    181struct ice_txq_stats {
    182	u64 restart_q;
    183	u64 tx_busy;
    184	u64 tx_linearize;
    185	int prev_pkt; /* negative if no pending Tx descriptors */
    186};
    187
    188struct ice_rxq_stats {
    189	u64 non_eop_descs;
    190	u64 alloc_page_failed;
    191	u64 alloc_buf_failed;
    192};
    193
    194enum ice_ring_state_t {
    195	ICE_TX_XPS_INIT_DONE,
    196	ICE_TX_NBITS,
    197};
    198
    199/* this enum matches hardware bits and is meant to be used by DYN_CTLN
    200 * registers and QINT registers or more generally anywhere in the manual
    201 * mentioning ITR_INDX, ITR_NONE cannot be used as an index 'n' into any
    202 * register but instead is a special value meaning "don't update" ITR0/1/2.
    203 */
    204enum ice_dyn_idx_t {
    205	ICE_IDX_ITR0 = 0,
    206	ICE_IDX_ITR1 = 1,
    207	ICE_IDX_ITR2 = 2,
    208	ICE_ITR_NONE = 3	/* ITR_NONE must not be used as an index */
    209};
    210
    211/* Header split modes defined by DTYPE field of Rx RLAN context */
    212enum ice_rx_dtype {
    213	ICE_RX_DTYPE_NO_SPLIT		= 0,
    214	ICE_RX_DTYPE_HEADER_SPLIT	= 1,
    215	ICE_RX_DTYPE_SPLIT_ALWAYS	= 2,
    216};
    217
    218/* indices into GLINT_ITR registers */
    219#define ICE_RX_ITR	ICE_IDX_ITR0
    220#define ICE_TX_ITR	ICE_IDX_ITR1
    221#define ICE_ITR_8K	124
    222#define ICE_ITR_20K	50
    223#define ICE_ITR_MAX	8160 /* 0x1FE0 */
    224#define ICE_DFLT_TX_ITR	ICE_ITR_20K
    225#define ICE_DFLT_RX_ITR	ICE_ITR_20K
    226enum ice_dynamic_itr {
    227	ITR_STATIC = 0,
    228	ITR_DYNAMIC = 1
    229};
    230
    231#define ITR_IS_DYNAMIC(rc) ((rc)->itr_mode == ITR_DYNAMIC)
    232#define ICE_ITR_GRAN_S		1	/* ITR granularity is always 2us */
    233#define ICE_ITR_GRAN_US		BIT(ICE_ITR_GRAN_S)
    234#define ICE_ITR_MASK		0x1FFE	/* ITR register value alignment mask */
    235#define ITR_REG_ALIGN(setting)	((setting) & ICE_ITR_MASK)
    236
    237#define ICE_DFLT_INTRL	0
    238#define ICE_MAX_INTRL	236
    239
    240#define ICE_IN_WB_ON_ITR_MODE	255
    241/* Sets WB_ON_ITR and assumes INTENA bit is already cleared, which allows
    242 * setting the MSK_M bit to tell hardware to ignore the INTENA_M bit. Also,
    243 * set the write-back latency to the usecs passed in.
    244 */
    245#define ICE_GLINT_DYN_CTL_WB_ON_ITR(usecs, itr_idx)	\
    246	((((usecs) << (GLINT_DYN_CTL_INTERVAL_S - ICE_ITR_GRAN_S)) & \
    247	  GLINT_DYN_CTL_INTERVAL_M) | \
    248	 (((itr_idx) << GLINT_DYN_CTL_ITR_INDX_S) & \
    249	  GLINT_DYN_CTL_ITR_INDX_M) | GLINT_DYN_CTL_INTENA_MSK_M | \
    250	 GLINT_DYN_CTL_WB_ON_ITR_M)
    251
    252/* Legacy or Advanced Mode Queue */
    253#define ICE_TX_ADVANCED	0
    254#define ICE_TX_LEGACY	1
    255
    256/* descriptor ring, associated with a VSI */
    257struct ice_rx_ring {
    258	/* CL1 - 1st cacheline starts here */
    259	struct ice_rx_ring *next;	/* pointer to next ring in q_vector */
    260	void *desc;			/* Descriptor ring memory */
    261	struct device *dev;		/* Used for DMA mapping */
    262	struct net_device *netdev;	/* netdev ring maps to */
    263	struct ice_vsi *vsi;		/* Backreference to associated VSI */
    264	struct ice_q_vector *q_vector;	/* Backreference to associated vector */
    265	u8 __iomem *tail;
    266	union {
    267		struct ice_rx_buf *rx_buf;
    268		struct xdp_buff **xdp_buf;
    269	};
    270	/* CL2 - 2nd cacheline starts here */
    271	struct xdp_rxq_info xdp_rxq;
    272	/* CL3 - 3rd cacheline starts here */
    273	u16 q_index;			/* Queue number of ring */
    274
    275	u16 count;			/* Number of descriptors */
    276	u16 reg_idx;			/* HW register index of the ring */
    277
    278	/* used in interrupt processing */
    279	u16 next_to_use;
    280	u16 next_to_clean;
    281	u16 next_to_alloc;
    282	u16 rx_offset;
    283	u16 rx_buf_len;
    284
    285	/* stats structs */
    286	struct ice_rxq_stats rx_stats;
    287	struct ice_q_stats	stats;
    288	struct u64_stats_sync syncp;
    289
    290	struct rcu_head rcu;		/* to avoid race on free */
    291	/* CL4 - 3rd cacheline starts here */
    292	struct ice_channel *ch;
    293	struct bpf_prog *xdp_prog;
    294	struct ice_tx_ring *xdp_ring;
    295	struct xsk_buff_pool *xsk_pool;
    296	struct sk_buff *skb;
    297	dma_addr_t dma;			/* physical address of ring */
    298#define ICE_RX_FLAGS_RING_BUILD_SKB	BIT(1)
    299	u64 cached_phctime;
    300	u8 dcb_tc;			/* Traffic class of ring */
    301	u8 ptp_rx;
    302	u8 flags;
    303} ____cacheline_internodealigned_in_smp;
    304
    305struct ice_tx_ring {
    306	/* CL1 - 1st cacheline starts here */
    307	struct ice_tx_ring *next;	/* pointer to next ring in q_vector */
    308	void *desc;			/* Descriptor ring memory */
    309	struct device *dev;		/* Used for DMA mapping */
    310	u8 __iomem *tail;
    311	struct ice_tx_buf *tx_buf;
    312	struct ice_q_vector *q_vector;	/* Backreference to associated vector */
    313	struct net_device *netdev;	/* netdev ring maps to */
    314	struct ice_vsi *vsi;		/* Backreference to associated VSI */
    315	/* CL2 - 2nd cacheline starts here */
    316	dma_addr_t dma;			/* physical address of ring */
    317	struct xsk_buff_pool *xsk_pool;
    318	u16 next_to_use;
    319	u16 next_to_clean;
    320	u16 next_rs;
    321	u16 next_dd;
    322	u16 q_handle;			/* Queue handle per TC */
    323	u16 reg_idx;			/* HW register index of the ring */
    324	u16 count;			/* Number of descriptors */
    325	u16 q_index;			/* Queue number of ring */
    326	/* stats structs */
    327	struct ice_txq_stats tx_stats;
    328	/* CL3 - 3rd cacheline starts here */
    329	struct ice_q_stats	stats;
    330	struct u64_stats_sync syncp;
    331	struct rcu_head rcu;		/* to avoid race on free */
    332	DECLARE_BITMAP(xps_state, ICE_TX_NBITS);	/* XPS Config State */
    333	struct ice_channel *ch;
    334	struct ice_ptp_tx *tx_tstamps;
    335	spinlock_t tx_lock;
    336	u32 txq_teid;			/* Added Tx queue TEID */
    337	/* CL4 - 4th cacheline starts here */
    338	u16 xdp_tx_active;
    339#define ICE_TX_FLAGS_RING_XDP		BIT(0)
    340#define ICE_TX_FLAGS_RING_VLAN_L2TAG1	BIT(1)
    341#define ICE_TX_FLAGS_RING_VLAN_L2TAG2	BIT(2)
    342	u8 flags;
    343	u8 dcb_tc;			/* Traffic class of ring */
    344	u8 ptp_tx;
    345} ____cacheline_internodealigned_in_smp;
    346
    347static inline bool ice_ring_uses_build_skb(struct ice_rx_ring *ring)
    348{
    349	return !!(ring->flags & ICE_RX_FLAGS_RING_BUILD_SKB);
    350}
    351
    352static inline void ice_set_ring_build_skb_ena(struct ice_rx_ring *ring)
    353{
    354	ring->flags |= ICE_RX_FLAGS_RING_BUILD_SKB;
    355}
    356
    357static inline void ice_clear_ring_build_skb_ena(struct ice_rx_ring *ring)
    358{
    359	ring->flags &= ~ICE_RX_FLAGS_RING_BUILD_SKB;
    360}
    361
    362static inline bool ice_ring_ch_enabled(struct ice_tx_ring *ring)
    363{
    364	return !!ring->ch;
    365}
    366
    367static inline bool ice_ring_is_xdp(struct ice_tx_ring *ring)
    368{
    369	return !!(ring->flags & ICE_TX_FLAGS_RING_XDP);
    370}
    371
    372enum ice_container_type {
    373	ICE_RX_CONTAINER,
    374	ICE_TX_CONTAINER,
    375};
    376
    377struct ice_ring_container {
    378	/* head of linked-list of rings */
    379	union {
    380		struct ice_rx_ring *rx_ring;
    381		struct ice_tx_ring *tx_ring;
    382	};
    383	struct dim dim;		/* data for net_dim algorithm */
    384	u16 itr_idx;		/* index in the interrupt vector */
    385	/* this matches the maximum number of ITR bits, but in usec
    386	 * values, so it is shifted left one bit (bit zero is ignored)
    387	 */
    388	union {
    389		struct {
    390			u16 itr_setting:13;
    391			u16 itr_reserved:2;
    392			u16 itr_mode:1;
    393		};
    394		u16 itr_settings;
    395	};
    396	enum ice_container_type type;
    397};
    398
    399struct ice_coalesce_stored {
    400	u16 itr_tx;
    401	u16 itr_rx;
    402	u8 intrl;
    403	u8 tx_valid;
    404	u8 rx_valid;
    405};
    406
    407/* iterator for handling rings in ring container */
    408#define ice_for_each_rx_ring(pos, head) \
    409	for (pos = (head).rx_ring; pos; pos = pos->next)
    410
    411#define ice_for_each_tx_ring(pos, head) \
    412	for (pos = (head).tx_ring; pos; pos = pos->next)
    413
    414static inline unsigned int ice_rx_pg_order(struct ice_rx_ring *ring)
    415{
    416#if (PAGE_SIZE < 8192)
    417	if (ring->rx_buf_len > (PAGE_SIZE / 2))
    418		return 1;
    419#endif
    420	return 0;
    421}
    422
    423#define ice_rx_pg_size(_ring) (PAGE_SIZE << ice_rx_pg_order(_ring))
    424
    425union ice_32b_rx_flex_desc;
    426
    427bool ice_alloc_rx_bufs(struct ice_rx_ring *rxr, u16 cleaned_count);
    428netdev_tx_t ice_start_xmit(struct sk_buff *skb, struct net_device *netdev);
    429u16
    430ice_select_queue(struct net_device *dev, struct sk_buff *skb,
    431		 struct net_device *sb_dev);
    432void ice_clean_tx_ring(struct ice_tx_ring *tx_ring);
    433void ice_clean_rx_ring(struct ice_rx_ring *rx_ring);
    434int ice_setup_tx_ring(struct ice_tx_ring *tx_ring);
    435int ice_setup_rx_ring(struct ice_rx_ring *rx_ring);
    436void ice_free_tx_ring(struct ice_tx_ring *tx_ring);
    437void ice_free_rx_ring(struct ice_rx_ring *rx_ring);
    438int ice_napi_poll(struct napi_struct *napi, int budget);
    439int
    440ice_prgm_fdir_fltr(struct ice_vsi *vsi, struct ice_fltr_desc *fdir_desc,
    441		   u8 *raw_packet);
    442int ice_clean_rx_irq(struct ice_rx_ring *rx_ring, int budget);
    443void ice_clean_ctrl_tx_irq(struct ice_tx_ring *tx_ring);
    444#endif /* _ICE_TXRX_H_ */