e1000_hw.h (12616B)
1/* SPDX-License-Identifier: GPL-2.0 */ 2/* Copyright(c) 2007 - 2018 Intel Corporation. */ 3 4#ifndef _E1000_IGB_HW_H_ 5#define _E1000_IGB_HW_H_ 6 7#include <linux/types.h> 8#include <linux/delay.h> 9#include <linux/io.h> 10#include <linux/netdevice.h> 11 12#include "e1000_regs.h" 13#include "e1000_defines.h" 14 15struct e1000_hw; 16 17#define E1000_DEV_ID_82576 0x10C9 18#define E1000_DEV_ID_82576_FIBER 0x10E6 19#define E1000_DEV_ID_82576_SERDES 0x10E7 20#define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8 21#define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526 22#define E1000_DEV_ID_82576_NS 0x150A 23#define E1000_DEV_ID_82576_NS_SERDES 0x1518 24#define E1000_DEV_ID_82576_SERDES_QUAD 0x150D 25#define E1000_DEV_ID_82575EB_COPPER 0x10A7 26#define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9 27#define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6 28#define E1000_DEV_ID_82580_COPPER 0x150E 29#define E1000_DEV_ID_82580_FIBER 0x150F 30#define E1000_DEV_ID_82580_SERDES 0x1510 31#define E1000_DEV_ID_82580_SGMII 0x1511 32#define E1000_DEV_ID_82580_COPPER_DUAL 0x1516 33#define E1000_DEV_ID_82580_QUAD_FIBER 0x1527 34#define E1000_DEV_ID_DH89XXCC_SGMII 0x0438 35#define E1000_DEV_ID_DH89XXCC_SERDES 0x043A 36#define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C 37#define E1000_DEV_ID_DH89XXCC_SFP 0x0440 38#define E1000_DEV_ID_I350_COPPER 0x1521 39#define E1000_DEV_ID_I350_FIBER 0x1522 40#define E1000_DEV_ID_I350_SERDES 0x1523 41#define E1000_DEV_ID_I350_SGMII 0x1524 42#define E1000_DEV_ID_I210_COPPER 0x1533 43#define E1000_DEV_ID_I210_FIBER 0x1536 44#define E1000_DEV_ID_I210_SERDES 0x1537 45#define E1000_DEV_ID_I210_SGMII 0x1538 46#define E1000_DEV_ID_I210_COPPER_FLASHLESS 0x157B 47#define E1000_DEV_ID_I210_SERDES_FLASHLESS 0x157C 48#define E1000_DEV_ID_I211_COPPER 0x1539 49#define E1000_DEV_ID_I354_BACKPLANE_1GBPS 0x1F40 50#define E1000_DEV_ID_I354_SGMII 0x1F41 51#define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS 0x1F45 52 53#define E1000_REVISION_2 2 54#define E1000_REVISION_4 4 55 56#define E1000_FUNC_0 0 57#define E1000_FUNC_1 1 58#define E1000_FUNC_2 2 59#define E1000_FUNC_3 3 60 61#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0 62#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3 63#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6 64#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9 65 66enum e1000_mac_type { 67 e1000_undefined = 0, 68 e1000_82575, 69 e1000_82576, 70 e1000_82580, 71 e1000_i350, 72 e1000_i354, 73 e1000_i210, 74 e1000_i211, 75 e1000_num_macs /* List is 1-based, so subtract 1 for true count. */ 76}; 77 78enum e1000_media_type { 79 e1000_media_type_unknown = 0, 80 e1000_media_type_copper = 1, 81 e1000_media_type_fiber = 2, 82 e1000_media_type_internal_serdes = 3, 83 e1000_num_media_types 84}; 85 86enum e1000_nvm_type { 87 e1000_nvm_unknown = 0, 88 e1000_nvm_none, 89 e1000_nvm_eeprom_spi, 90 e1000_nvm_flash_hw, 91 e1000_nvm_invm, 92 e1000_nvm_flash_sw 93}; 94 95enum e1000_nvm_override { 96 e1000_nvm_override_none = 0, 97 e1000_nvm_override_spi_small, 98 e1000_nvm_override_spi_large, 99}; 100 101enum e1000_phy_type { 102 e1000_phy_unknown = 0, 103 e1000_phy_none, 104 e1000_phy_m88, 105 e1000_phy_igp, 106 e1000_phy_igp_2, 107 e1000_phy_gg82563, 108 e1000_phy_igp_3, 109 e1000_phy_ife, 110 e1000_phy_82580, 111 e1000_phy_i210, 112 e1000_phy_bcm54616, 113}; 114 115enum e1000_bus_type { 116 e1000_bus_type_unknown = 0, 117 e1000_bus_type_pci, 118 e1000_bus_type_pcix, 119 e1000_bus_type_pci_express, 120 e1000_bus_type_reserved 121}; 122 123enum e1000_bus_speed { 124 e1000_bus_speed_unknown = 0, 125 e1000_bus_speed_33, 126 e1000_bus_speed_66, 127 e1000_bus_speed_100, 128 e1000_bus_speed_120, 129 e1000_bus_speed_133, 130 e1000_bus_speed_2500, 131 e1000_bus_speed_5000, 132 e1000_bus_speed_reserved 133}; 134 135enum e1000_bus_width { 136 e1000_bus_width_unknown = 0, 137 e1000_bus_width_pcie_x1, 138 e1000_bus_width_pcie_x2, 139 e1000_bus_width_pcie_x4 = 4, 140 e1000_bus_width_pcie_x8 = 8, 141 e1000_bus_width_32, 142 e1000_bus_width_64, 143 e1000_bus_width_reserved 144}; 145 146enum e1000_1000t_rx_status { 147 e1000_1000t_rx_status_not_ok = 0, 148 e1000_1000t_rx_status_ok, 149 e1000_1000t_rx_status_undefined = 0xFF 150}; 151 152enum e1000_rev_polarity { 153 e1000_rev_polarity_normal = 0, 154 e1000_rev_polarity_reversed, 155 e1000_rev_polarity_undefined = 0xFF 156}; 157 158enum e1000_fc_mode { 159 e1000_fc_none = 0, 160 e1000_fc_rx_pause, 161 e1000_fc_tx_pause, 162 e1000_fc_full, 163 e1000_fc_default = 0xFF 164}; 165 166/* Statistics counters collected by the MAC */ 167struct e1000_hw_stats { 168 u64 crcerrs; 169 u64 algnerrc; 170 u64 symerrs; 171 u64 rxerrc; 172 u64 mpc; 173 u64 scc; 174 u64 ecol; 175 u64 mcc; 176 u64 latecol; 177 u64 colc; 178 u64 dc; 179 u64 tncrs; 180 u64 sec; 181 u64 cexterr; 182 u64 rlec; 183 u64 xonrxc; 184 u64 xontxc; 185 u64 xoffrxc; 186 u64 xofftxc; 187 u64 fcruc; 188 u64 prc64; 189 u64 prc127; 190 u64 prc255; 191 u64 prc511; 192 u64 prc1023; 193 u64 prc1522; 194 u64 gprc; 195 u64 bprc; 196 u64 mprc; 197 u64 gptc; 198 u64 gorc; 199 u64 gotc; 200 u64 rnbc; 201 u64 ruc; 202 u64 rfc; 203 u64 roc; 204 u64 rjc; 205 u64 mgprc; 206 u64 mgpdc; 207 u64 mgptc; 208 u64 tor; 209 u64 tot; 210 u64 tpr; 211 u64 tpt; 212 u64 ptc64; 213 u64 ptc127; 214 u64 ptc255; 215 u64 ptc511; 216 u64 ptc1023; 217 u64 ptc1522; 218 u64 mptc; 219 u64 bptc; 220 u64 tsctc; 221 u64 tsctfc; 222 u64 iac; 223 u64 icrxptc; 224 u64 icrxatc; 225 u64 ictxptc; 226 u64 ictxatc; 227 u64 ictxqec; 228 u64 ictxqmtc; 229 u64 icrxdmtc; 230 u64 icrxoc; 231 u64 cbtmpc; 232 u64 htdpmc; 233 u64 cbrdpc; 234 u64 cbrmpc; 235 u64 rpthc; 236 u64 hgptc; 237 u64 htcbdpc; 238 u64 hgorc; 239 u64 hgotc; 240 u64 lenerrs; 241 u64 scvpc; 242 u64 hrmpc; 243 u64 doosync; 244 u64 o2bgptc; 245 u64 o2bspc; 246 u64 b2ospc; 247 u64 b2ogprc; 248}; 249 250struct e1000_host_mng_dhcp_cookie { 251 u32 signature; 252 u8 status; 253 u8 reserved0; 254 u16 vlan_id; 255 u32 reserved1; 256 u16 reserved2; 257 u8 reserved3; 258 u8 checksum; 259}; 260 261/* Host Interface "Rev 1" */ 262struct e1000_host_command_header { 263 u8 command_id; 264 u8 command_length; 265 u8 command_options; 266 u8 checksum; 267}; 268 269#define E1000_HI_MAX_DATA_LENGTH 252 270struct e1000_host_command_info { 271 struct e1000_host_command_header command_header; 272 u8 command_data[E1000_HI_MAX_DATA_LENGTH]; 273}; 274 275/* Host Interface "Rev 2" */ 276struct e1000_host_mng_command_header { 277 u8 command_id; 278 u8 checksum; 279 u16 reserved1; 280 u16 reserved2; 281 u16 command_length; 282}; 283 284#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 285struct e1000_host_mng_command_info { 286 struct e1000_host_mng_command_header command_header; 287 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; 288}; 289 290#include "e1000_mac.h" 291#include "e1000_phy.h" 292#include "e1000_nvm.h" 293#include "e1000_mbx.h" 294 295struct e1000_mac_operations { 296 s32 (*check_for_link)(struct e1000_hw *); 297 s32 (*reset_hw)(struct e1000_hw *); 298 s32 (*init_hw)(struct e1000_hw *); 299 bool (*check_mng_mode)(struct e1000_hw *); 300 s32 (*setup_physical_interface)(struct e1000_hw *); 301 void (*rar_set)(struct e1000_hw *, u8 *, u32); 302 s32 (*read_mac_addr)(struct e1000_hw *); 303 s32 (*get_speed_and_duplex)(struct e1000_hw *, u16 *, u16 *); 304 s32 (*acquire_swfw_sync)(struct e1000_hw *, u16); 305 void (*release_swfw_sync)(struct e1000_hw *, u16); 306#ifdef CONFIG_IGB_HWMON 307 s32 (*get_thermal_sensor_data)(struct e1000_hw *); 308 s32 (*init_thermal_sensor_thresh)(struct e1000_hw *); 309#endif 310 void (*write_vfta)(struct e1000_hw *, u32, u32); 311}; 312 313struct e1000_phy_operations { 314 s32 (*acquire)(struct e1000_hw *); 315 s32 (*check_polarity)(struct e1000_hw *); 316 s32 (*check_reset_block)(struct e1000_hw *); 317 s32 (*force_speed_duplex)(struct e1000_hw *); 318 s32 (*get_cfg_done)(struct e1000_hw *hw); 319 s32 (*get_cable_length)(struct e1000_hw *); 320 s32 (*get_phy_info)(struct e1000_hw *); 321 s32 (*read_reg)(struct e1000_hw *, u32, u16 *); 322 void (*release)(struct e1000_hw *); 323 s32 (*reset)(struct e1000_hw *); 324 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); 325 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); 326 s32 (*write_reg)(struct e1000_hw *, u32, u16); 327 s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *); 328 s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8); 329}; 330 331struct e1000_nvm_operations { 332 s32 (*acquire)(struct e1000_hw *); 333 s32 (*read)(struct e1000_hw *, u16, u16, u16 *); 334 void (*release)(struct e1000_hw *); 335 s32 (*write)(struct e1000_hw *, u16, u16, u16 *); 336 s32 (*update)(struct e1000_hw *); 337 s32 (*validate)(struct e1000_hw *); 338 s32 (*valid_led_default)(struct e1000_hw *, u16 *); 339}; 340 341#define E1000_MAX_SENSORS 3 342 343struct e1000_thermal_diode_data { 344 u8 location; 345 u8 temp; 346 u8 caution_thresh; 347 u8 max_op_thresh; 348}; 349 350struct e1000_thermal_sensor_data { 351 struct e1000_thermal_diode_data sensor[E1000_MAX_SENSORS]; 352}; 353 354struct e1000_info { 355 s32 (*get_invariants)(struct e1000_hw *); 356 struct e1000_mac_operations *mac_ops; 357 const struct e1000_phy_operations *phy_ops; 358 struct e1000_nvm_operations *nvm_ops; 359}; 360 361extern const struct e1000_info e1000_82575_info; 362 363struct e1000_mac_info { 364 struct e1000_mac_operations ops; 365 366 u8 addr[6]; 367 u8 perm_addr[6]; 368 369 enum e1000_mac_type type; 370 371 u32 ledctl_default; 372 u32 ledctl_mode1; 373 u32 ledctl_mode2; 374 u32 mc_filter_type; 375 u32 txcw; 376 377 u16 mta_reg_count; 378 u16 uta_reg_count; 379 380 /* Maximum size of the MTA register table in all supported adapters */ 381 #define MAX_MTA_REG 128 382 u32 mta_shadow[MAX_MTA_REG]; 383 u16 rar_entry_count; 384 385 u8 forced_speed_duplex; 386 387 bool adaptive_ifs; 388 bool arc_subsystem_valid; 389 bool asf_firmware_present; 390 bool autoneg; 391 bool autoneg_failed; 392 bool disable_hw_init_bits; 393 bool get_link_status; 394 bool ifs_params_forced; 395 bool in_ifs_mode; 396 bool report_tx_early; 397 bool serdes_has_link; 398 bool tx_pkt_filtering; 399 struct e1000_thermal_sensor_data thermal_sensor_data; 400}; 401 402struct e1000_phy_info { 403 struct e1000_phy_operations ops; 404 405 enum e1000_phy_type type; 406 407 enum e1000_1000t_rx_status local_rx; 408 enum e1000_1000t_rx_status remote_rx; 409 enum e1000_ms_type ms_type; 410 enum e1000_ms_type original_ms_type; 411 enum e1000_rev_polarity cable_polarity; 412 enum e1000_smart_speed smart_speed; 413 414 u32 addr; 415 u32 id; 416 u32 reset_delay_us; /* in usec */ 417 u32 revision; 418 419 enum e1000_media_type media_type; 420 421 u16 autoneg_advertised; 422 u16 autoneg_mask; 423 u16 cable_length; 424 u16 max_cable_length; 425 u16 min_cable_length; 426 u16 pair_length[4]; 427 428 u8 mdix; 429 430 bool disable_polarity_correction; 431 bool is_mdix; 432 bool polarity_correction; 433 bool reset_disable; 434 bool speed_downgraded; 435 bool autoneg_wait_to_complete; 436}; 437 438struct e1000_nvm_info { 439 struct e1000_nvm_operations ops; 440 enum e1000_nvm_type type; 441 enum e1000_nvm_override override; 442 443 u32 flash_bank_size; 444 u32 flash_base_addr; 445 446 u16 word_size; 447 u16 delay_usec; 448 u16 address_bits; 449 u16 opcode_bits; 450 u16 page_size; 451}; 452 453struct e1000_bus_info { 454 enum e1000_bus_type type; 455 enum e1000_bus_speed speed; 456 enum e1000_bus_width width; 457 458 u32 snoop; 459 460 u16 func; 461 u16 pci_cmd_word; 462}; 463 464struct e1000_fc_info { 465 u32 high_water; /* Flow control high-water mark */ 466 u32 low_water; /* Flow control low-water mark */ 467 u16 pause_time; /* Flow control pause timer */ 468 bool send_xon; /* Flow control send XON */ 469 bool strict_ieee; /* Strict IEEE mode */ 470 enum e1000_fc_mode current_mode; /* Type of flow control */ 471 enum e1000_fc_mode requested_mode; 472}; 473 474struct e1000_mbx_operations { 475 s32 (*init_params)(struct e1000_hw *hw); 476 s32 (*read)(struct e1000_hw *hw, u32 *msg, u16 size, u16 mbx_id, 477 bool unlock); 478 s32 (*write)(struct e1000_hw *hw, u32 *msg, u16 size, u16 mbx_id); 479 s32 (*read_posted)(struct e1000_hw *hw, u32 *msg, u16 size, u16 mbx_id); 480 s32 (*write_posted)(struct e1000_hw *hw, u32 *msg, u16 size, 481 u16 mbx_id); 482 s32 (*check_for_msg)(struct e1000_hw *hw, u16 mbx_id); 483 s32 (*check_for_ack)(struct e1000_hw *hw, u16 mbx_id); 484 s32 (*check_for_rst)(struct e1000_hw *hw, u16 mbx_id); 485 s32 (*unlock)(struct e1000_hw *hw, u16 mbx_id); 486}; 487 488struct e1000_mbx_stats { 489 u32 msgs_tx; 490 u32 msgs_rx; 491 492 u32 acks; 493 u32 reqs; 494 u32 rsts; 495}; 496 497struct e1000_mbx_info { 498 struct e1000_mbx_operations ops; 499 struct e1000_mbx_stats stats; 500 u32 timeout; 501 u32 usec_delay; 502 u16 size; 503}; 504 505struct e1000_dev_spec_82575 { 506 bool sgmii_active; 507 bool global_device_reset; 508 bool eee_disable; 509 bool clear_semaphore_once; 510 struct e1000_sfp_flags eth_flags; 511 bool module_plugged; 512 u8 media_port; 513 bool media_changed; 514 bool mas_capable; 515}; 516 517struct e1000_hw { 518 void *back; 519 520 u8 __iomem *hw_addr; 521 u8 __iomem *flash_address; 522 unsigned long io_base; 523 524 struct e1000_mac_info mac; 525 struct e1000_fc_info fc; 526 struct e1000_phy_info phy; 527 struct e1000_nvm_info nvm; 528 struct e1000_bus_info bus; 529 struct e1000_mbx_info mbx; 530 struct e1000_host_mng_dhcp_cookie mng_cookie; 531 532 union { 533 struct e1000_dev_spec_82575 _82575; 534 } dev_spec; 535 536 u16 device_id; 537 u16 subsystem_vendor_id; 538 u16 subsystem_device_id; 539 u16 vendor_id; 540 541 u8 revision_id; 542}; 543 544struct net_device *igb_get_hw_dev(struct e1000_hw *hw); 545#define hw_dbg(format, arg...) \ 546 netdev_dbg(igb_get_hw_dev(hw), format, ##arg) 547 548/* These functions must be implemented by drivers */ 549s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 550s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 551 552void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 553void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 554#endif /* _E1000_IGB_HW_H_ */