e1000_regs.h (22343B)
1/* SPDX-License-Identifier: GPL-2.0 */ 2/* Copyright(c) 2007 - 2018 Intel Corporation. */ 3 4#ifndef _E1000_REGS_H_ 5#define _E1000_REGS_H_ 6 7#define E1000_CTRL 0x00000 /* Device Control - RW */ 8#define E1000_STATUS 0x00008 /* Device Status - RO */ 9#define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */ 10#define E1000_EERD 0x00014 /* EEPROM Read - RW */ 11#define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */ 12#define E1000_MDIC 0x00020 /* MDI Control - RW */ 13#define E1000_MDICNFG 0x00E04 /* MDI Config - RW */ 14#define E1000_SCTL 0x00024 /* SerDes Control - RW */ 15#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */ 16#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */ 17#define E1000_FCT 0x00030 /* Flow Control Type - RW */ 18#define E1000_CONNSW 0x00034 /* Copper/Fiber switch control - RW */ 19#define E1000_VET 0x00038 /* VLAN Ether Type - RW */ 20#define E1000_TSSDP 0x0003C /* Time Sync SDP Configuration Register - RW */ 21#define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */ 22#define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */ 23#define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */ 24#define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */ 25#define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */ 26#define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */ 27#define E1000_RCTL 0x00100 /* RX Control - RW */ 28#define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */ 29#define E1000_TXCW 0x00178 /* TX Configuration Word - RW */ 30#define E1000_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */ 31#define E1000_EITR(_n) (0x01680 + (0x4 * (_n))) 32#define E1000_EICS 0x01520 /* Ext. Interrupt Cause Set - W0 */ 33#define E1000_EIMS 0x01524 /* Ext. Interrupt Mask Set/Read - RW */ 34#define E1000_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */ 35#define E1000_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */ 36#define E1000_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */ 37#define E1000_GPIE 0x01514 /* General Purpose Interrupt Enable - RW */ 38#define E1000_IVAR0 0x01700 /* Interrupt Vector Allocation (array) - RW */ 39#define E1000_IVAR_MISC 0x01740 /* IVAR for "other" causes - RW */ 40#define E1000_TCTL 0x00400 /* TX Control - RW */ 41#define E1000_TCTL_EXT 0x00404 /* Extended TX Control - RW */ 42#define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */ 43#define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */ 44#define E1000_LEDCTL 0x00E00 /* LED Control - RW */ 45#define E1000_LEDMUX 0x08130 /* LED MUX Control */ 46#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */ 47#define E1000_PBS 0x01008 /* Packet Buffer Size */ 48#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */ 49#define E1000_EEMNGCTL_I210 0x12030 /* MNG EEprom Control */ 50#define E1000_EEARBC_I210 0x12024 /* EEPROM Auto Read Bus Control */ 51#define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */ 52#define E1000_I2CCMD 0x01028 /* SFPI2C Command Register - RW */ 53#define E1000_FRTIMER 0x01048 /* Free Running Timer - RW */ 54#define E1000_TCPTIMER 0x0104C /* TCP Timer - RW */ 55#define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */ 56#define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */ 57#define E1000_FCRTV 0x02460 /* Flow Control Refresh Timer Value - RW */ 58#define E1000_I2CPARAMS 0x0102C /* SFPI2C Parameters Register - RW */ 59#define E1000_I2CBB_EN 0x00000100 /* I2C - Bit Bang Enable */ 60#define E1000_I2C_CLK_OUT 0x00000200 /* I2C- Clock */ 61#define E1000_I2C_DATA_OUT 0x00000400 /* I2C- Data Out */ 62#define E1000_I2C_DATA_OE_N 0x00000800 /* I2C- Data Output Enable */ 63#define E1000_I2C_DATA_IN 0x00001000 /* I2C- Data In */ 64#define E1000_I2C_CLK_OE_N 0x00002000 /* I2C- Clock Output Enable */ 65#define E1000_I2C_CLK_IN 0x00004000 /* I2C- Clock In */ 66#define E1000_MPHY_ADDR_CTRL 0x0024 /* GbE MPHY Address Control */ 67#define E1000_MPHY_DATA 0x0E10 /* GBE MPHY Data */ 68#define E1000_MPHY_STAT 0x0E0C /* GBE MPHY Statistics */ 69 70/* IEEE 1588 TIMESYNCH */ 71#define E1000_TSYNCRXCTL 0x0B620 /* Rx Time Sync Control register - RW */ 72#define E1000_TSYNCTXCTL 0x0B614 /* Tx Time Sync Control register - RW */ 73#define E1000_TSYNCRXCFG 0x05F50 /* Time Sync Rx Configuration - RW */ 74#define E1000_RXSTMPL 0x0B624 /* Rx timestamp Low - RO */ 75#define E1000_RXSTMPH 0x0B628 /* Rx timestamp High - RO */ 76#define E1000_RXSATRL 0x0B62C /* Rx timestamp attribute low - RO */ 77#define E1000_RXSATRH 0x0B630 /* Rx timestamp attribute high - RO */ 78#define E1000_TXSTMPL 0x0B618 /* Tx timestamp value Low - RO */ 79#define E1000_TXSTMPH 0x0B61C /* Tx timestamp value High - RO */ 80#define E1000_SYSTIML 0x0B600 /* System time register Low - RO */ 81#define E1000_SYSTIMH 0x0B604 /* System time register High - RO */ 82#define E1000_TIMINCA 0x0B608 /* Increment attributes register - RW */ 83#define E1000_TSAUXC 0x0B640 /* Timesync Auxiliary Control register */ 84#define E1000_TRGTTIML0 0x0B644 /* Target Time Register 0 Low - RW */ 85#define E1000_TRGTTIMH0 0x0B648 /* Target Time Register 0 High - RW */ 86#define E1000_TRGTTIML1 0x0B64C /* Target Time Register 1 Low - RW */ 87#define E1000_TRGTTIMH1 0x0B650 /* Target Time Register 1 High - RW */ 88#define E1000_FREQOUT0 0x0B654 /* Frequency Out 0 Control Register - RW */ 89#define E1000_FREQOUT1 0x0B658 /* Frequency Out 1 Control Register - RW */ 90#define E1000_AUXSTMPL0 0x0B65C /* Auxiliary Time Stamp 0 Register Low - RO */ 91#define E1000_AUXSTMPH0 0x0B660 /* Auxiliary Time Stamp 0 Register High - RO */ 92#define E1000_AUXSTMPL1 0x0B664 /* Auxiliary Time Stamp 1 Register Low - RO */ 93#define E1000_AUXSTMPH1 0x0B668 /* Auxiliary Time Stamp 1 Register High - RO */ 94#define E1000_SYSTIMR 0x0B6F8 /* System time register Residue */ 95#define E1000_TSICR 0x0B66C /* Interrupt Cause Register */ 96#define E1000_TSIM 0x0B674 /* Interrupt Mask Register */ 97 98/* Filtering Registers */ 99#define E1000_SAQF(_n) (0x5980 + 4 * (_n)) 100#define E1000_DAQF(_n) (0x59A0 + 4 * (_n)) 101#define E1000_SPQF(_n) (0x59C0 + 4 * (_n)) 102#define E1000_FTQF(_n) (0x59E0 + 4 * (_n)) 103#define E1000_SAQF0 E1000_SAQF(0) 104#define E1000_DAQF0 E1000_DAQF(0) 105#define E1000_SPQF0 E1000_SPQF(0) 106#define E1000_FTQF0 E1000_FTQF(0) 107#define E1000_SYNQF(_n) (0x055FC + (4 * (_n))) /* SYN Packet Queue Fltr */ 108#define E1000_ETQF(_n) (0x05CB0 + (4 * (_n))) /* EType Queue Fltr */ 109 110#define E1000_RQDPC(_n) (0x0C030 + ((_n) * 0x40)) 111 112/* DMA Coalescing registers */ 113#define E1000_DMACR 0x02508 /* Control Register */ 114#define E1000_DMCTXTH 0x03550 /* Transmit Threshold */ 115#define E1000_DMCTLX 0x02514 /* Time to Lx Request */ 116#define E1000_DMCRTRH 0x05DD0 /* Receive Packet Rate Threshold */ 117#define E1000_DMCCNT 0x05DD4 /* Current Rx Count */ 118#define E1000_FCRTC 0x02170 /* Flow Control Rx high watermark */ 119#define E1000_PCIEMISC 0x05BB8 /* PCIE misc config register */ 120 121/* TX Rate Limit Registers */ 122#define E1000_RTTDQSEL 0x3604 /* Tx Desc Plane Queue Select - WO */ 123#define E1000_RTTBCNRM 0x3690 /* Tx BCN Rate-scheduler MMW */ 124#define E1000_RTTBCNRC 0x36B0 /* Tx BCN Rate-Scheduler Config - WO */ 125 126/* Split and Replication RX Control - RW */ 127#define E1000_RXPBS 0x02404 /* Rx Packet Buffer Size - RW */ 128 129/* Thermal sensor configuration and status registers */ 130#define E1000_THMJT 0x08100 /* Junction Temperature */ 131#define E1000_THLOWTC 0x08104 /* Low Threshold Control */ 132#define E1000_THMIDTC 0x08108 /* Mid Threshold Control */ 133#define E1000_THHIGHTC 0x0810C /* High Threshold Control */ 134#define E1000_THSTAT 0x08110 /* Thermal Sensor Status */ 135 136/* Convenience macros 137 * 138 * Note: "_n" is the queue number of the register to be written to. 139 * 140 * Example usage: 141 * E1000_RDBAL_REG(current_rx_queue) 142 */ 143#define E1000_RDBAL(_n) ((_n) < 4 ? (0x02800 + ((_n) * 0x100)) \ 144 : (0x0C000 + ((_n) * 0x40))) 145#define E1000_RDBAH(_n) ((_n) < 4 ? (0x02804 + ((_n) * 0x100)) \ 146 : (0x0C004 + ((_n) * 0x40))) 147#define E1000_RDLEN(_n) ((_n) < 4 ? (0x02808 + ((_n) * 0x100)) \ 148 : (0x0C008 + ((_n) * 0x40))) 149#define E1000_SRRCTL(_n) ((_n) < 4 ? (0x0280C + ((_n) * 0x100)) \ 150 : (0x0C00C + ((_n) * 0x40))) 151#define E1000_RDH(_n) ((_n) < 4 ? (0x02810 + ((_n) * 0x100)) \ 152 : (0x0C010 + ((_n) * 0x40))) 153#define E1000_RDT(_n) ((_n) < 4 ? (0x02818 + ((_n) * 0x100)) \ 154 : (0x0C018 + ((_n) * 0x40))) 155#define E1000_RXDCTL(_n) ((_n) < 4 ? (0x02828 + ((_n) * 0x100)) \ 156 : (0x0C028 + ((_n) * 0x40))) 157#define E1000_TDBAL(_n) ((_n) < 4 ? (0x03800 + ((_n) * 0x100)) \ 158 : (0x0E000 + ((_n) * 0x40))) 159#define E1000_TDBAH(_n) ((_n) < 4 ? (0x03804 + ((_n) * 0x100)) \ 160 : (0x0E004 + ((_n) * 0x40))) 161#define E1000_TDLEN(_n) ((_n) < 4 ? (0x03808 + ((_n) * 0x100)) \ 162 : (0x0E008 + ((_n) * 0x40))) 163#define E1000_TDH(_n) ((_n) < 4 ? (0x03810 + ((_n) * 0x100)) \ 164 : (0x0E010 + ((_n) * 0x40))) 165#define E1000_TDT(_n) ((_n) < 4 ? (0x03818 + ((_n) * 0x100)) \ 166 : (0x0E018 + ((_n) * 0x40))) 167#define E1000_TXDCTL(_n) ((_n) < 4 ? (0x03828 + ((_n) * 0x100)) \ 168 : (0x0E028 + ((_n) * 0x40))) 169#define E1000_RXCTL(_n) ((_n) < 4 ? (0x02814 + ((_n) * 0x100)) : \ 170 (0x0C014 + ((_n) * 0x40))) 171#define E1000_DCA_RXCTRL(_n) E1000_RXCTL(_n) 172#define E1000_TXCTL(_n) ((_n) < 4 ? (0x03814 + ((_n) * 0x100)) : \ 173 (0x0E014 + ((_n) * 0x40))) 174#define E1000_DCA_TXCTRL(_n) E1000_TXCTL(_n) 175#define E1000_TDWBAL(_n) ((_n) < 4 ? (0x03838 + ((_n) * 0x100)) \ 176 : (0x0E038 + ((_n) * 0x40))) 177#define E1000_TDWBAH(_n) ((_n) < 4 ? (0x0383C + ((_n) * 0x100)) \ 178 : (0x0E03C + ((_n) * 0x40))) 179 180#define E1000_RXPBS 0x02404 /* Rx Packet Buffer Size - RW */ 181#define E1000_TXPBS 0x03404 /* Tx Packet Buffer Size - RW */ 182 183#define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */ 184#define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */ 185#define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */ 186#define E1000_TDFPC 0x03430 /* TX Data FIFO Packet Count - RW */ 187#define E1000_DTXCTL 0x03590 /* DMA TX Control - RW */ 188#define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */ 189#define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */ 190#define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */ 191#define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */ 192#define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */ 193#define E1000_SCC 0x04014 /* Single Collision Count - R/clr */ 194#define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */ 195#define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */ 196#define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */ 197#define E1000_COLC 0x04028 /* Collision Count - R/clr */ 198#define E1000_DC 0x04030 /* Defer Count - R/clr */ 199#define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */ 200#define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */ 201#define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */ 202#define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */ 203#define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */ 204#define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */ 205#define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */ 206#define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */ 207#define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */ 208#define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */ 209#define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */ 210#define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */ 211#define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */ 212#define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */ 213#define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */ 214#define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */ 215#define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */ 216#define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */ 217#define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */ 218#define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */ 219#define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */ 220#define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */ 221#define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */ 222#define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */ 223#define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */ 224#define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */ 225#define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */ 226#define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */ 227#define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */ 228#define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */ 229#define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */ 230#define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */ 231#define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */ 232#define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */ 233#define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */ 234#define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */ 235#define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */ 236#define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */ 237#define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */ 238#define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */ 239#define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */ 240#define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */ 241#define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */ 242#define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */ 243#define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */ 244#define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */ 245#define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */ 246#define E1000_IAC 0x04100 /* Interrupt Assertion Count */ 247/* Interrupt Cause Rx Packet Timer Expire Count */ 248#define E1000_ICRXPTC 0x04104 249/* Interrupt Cause Rx Absolute Timer Expire Count */ 250#define E1000_ICRXATC 0x04108 251/* Interrupt Cause Tx Packet Timer Expire Count */ 252#define E1000_ICTXPTC 0x0410C 253/* Interrupt Cause Tx Absolute Timer Expire Count */ 254#define E1000_ICTXATC 0x04110 255/* Interrupt Cause Tx Queue Empty Count */ 256#define E1000_ICTXQEC 0x04118 257/* Interrupt Cause Tx Queue Minimum Threshold Count */ 258#define E1000_ICTXQMTC 0x0411C 259/* Interrupt Cause Rx Descriptor Minimum Threshold Count */ 260#define E1000_ICRXDMTC 0x04120 261#define E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */ 262#define E1000_PCS_CFG0 0x04200 /* PCS Configuration 0 - RW */ 263#define E1000_PCS_LCTL 0x04208 /* PCS Link Control - RW */ 264#define E1000_PCS_LSTAT 0x0420C /* PCS Link Status - RO */ 265#define E1000_CBTMPC 0x0402C /* Circuit Breaker TX Packet Count */ 266#define E1000_HTDPMC 0x0403C /* Host Transmit Discarded Packets */ 267#define E1000_CBRMPC 0x040FC /* Circuit Breaker RX Packet Count */ 268#define E1000_RPTHC 0x04104 /* Rx Packets To Host */ 269#define E1000_HGPTC 0x04118 /* Host Good Packets TX Count */ 270#define E1000_HTCBDPC 0x04124 /* Host TX Circuit Breaker Dropped Count */ 271#define E1000_HGORCL 0x04128 /* Host Good Octets Received Count Low */ 272#define E1000_HGORCH 0x0412C /* Host Good Octets Received Count High */ 273#define E1000_HGOTCL 0x04130 /* Host Good Octets Transmit Count Low */ 274#define E1000_HGOTCH 0x04134 /* Host Good Octets Transmit Count High */ 275#define E1000_LENERRS 0x04138 /* Length Errors Count */ 276#define E1000_SCVPC 0x04228 /* SerDes/SGMII Code Violation Pkt Count */ 277#define E1000_PCS_ANADV 0x04218 /* AN advertisement - RW */ 278#define E1000_PCS_LPAB 0x0421C /* Link Partner Ability - RW */ 279#define E1000_PCS_NPTX 0x04220 /* AN Next Page Transmit - RW */ 280#define E1000_PCS_LPABNP 0x04224 /* Link Partner Ability Next Page - RW */ 281#define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */ 282#define E1000_RLPML 0x05004 /* RX Long Packet Max Length */ 283#define E1000_RFCTL 0x05008 /* Receive Filter Control*/ 284#define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */ 285#define E1000_RA 0x05400 /* Receive Address - RW Array */ 286#define E1000_RA2 0x054E0 /* 2nd half of Rx address array - RW Array */ 287#define E1000_PSRTYPE(_i) (0x05480 + ((_i) * 4)) 288#define E1000_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \ 289 (0x054E0 + ((_i - 16) * 8))) 290#define E1000_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \ 291 (0x054E4 + ((_i - 16) * 8))) 292#define E1000_VLAPQF 0x055B0 /* VLAN Priority Queue Filter VLAPQF */ 293#define E1000_IP4AT_REG(_i) (0x05840 + ((_i) * 8)) 294#define E1000_IP6AT_REG(_i) (0x05880 + ((_i) * 4)) 295#define E1000_WUPM_REG(_i) (0x05A00 + ((_i) * 4)) 296#define E1000_FFMT_REG(_i) (0x09000 + ((_i) * 8)) 297#define E1000_FFVT_REG(_i) (0x09800 + ((_i) * 8)) 298#define E1000_FFLT_REG(_i) (0x05F00 + ((_i) * 8)) 299#define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */ 300#define E1000_VT_CTL 0x0581C /* VMDq Control - RW */ 301#define E1000_WUC 0x05800 /* Wakeup Control - RW */ 302#define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */ 303#define E1000_WUS 0x05810 /* Wakeup Status - R/W1C */ 304#define E1000_MANC 0x05820 /* Management Control - RW */ 305#define E1000_IPAV 0x05838 /* IP Address Valid - RW */ 306#define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */ 307 308#define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */ 309#define E1000_CCMCTL 0x05B48 /* CCM Control Register */ 310#define E1000_GIOCTL 0x05B44 /* GIO Analog Control Register */ 311#define E1000_SCCTL 0x05B4C /* PCIc PLL Configuration Register */ 312#define E1000_GCR 0x05B00 /* PCI-Ex Control */ 313#define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */ 314#define E1000_SWSM 0x05B50 /* SW Semaphore */ 315#define E1000_FWSM 0x05B54 /* FW Semaphore */ 316#define E1000_DCA_CTRL 0x05B74 /* DCA Control - RW */ 317 318/* RSS registers */ 319#define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */ 320#define E1000_IMIR(_i) (0x05A80 + ((_i) * 4)) /* Immediate Interrupt */ 321#define E1000_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* Immediate Interrupt Ext*/ 322#define E1000_IMIRVP 0x05AC0 /* Immediate Interrupt RX VLAN Priority - RW */ 323/* MSI-X Allocation Register (_i) - RW */ 324#define E1000_MSIXBM(_i) (0x01600 + ((_i) * 4)) 325/* Redirection Table - RW Array */ 326#define E1000_RETA(_i) (0x05C00 + ((_i) * 4)) 327#define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW Array */ 328 329/* VT Registers */ 330#define E1000_MBVFICR 0x00C80 /* Mailbox VF Cause - RWC */ 331#define E1000_MBVFIMR 0x00C84 /* Mailbox VF int Mask - RW */ 332#define E1000_VFLRE 0x00C88 /* VF Register Events - RWC */ 333#define E1000_VFRE 0x00C8C /* VF Receive Enables */ 334#define E1000_VFTE 0x00C90 /* VF Transmit Enables */ 335#define E1000_QDE 0x02408 /* Queue Drop Enable - RW */ 336#define E1000_DTXSWC 0x03500 /* DMA Tx Switch Control - RW */ 337#define E1000_WVBR 0x03554 /* VM Wrong Behavior - RWS */ 338#define E1000_RPLOLR 0x05AF0 /* Replication Offload - RW */ 339#define E1000_UTA 0x0A000 /* Unicast Table Array - RW */ 340#define E1000_IOVTCL 0x05BBC /* IOV Control Register */ 341#define E1000_TXSWC 0x05ACC /* Tx Switch Control */ 342#define E1000_LVMMC 0x03548 /* Last VM Misbehavior cause */ 343/* These act per VF so an array friendly macro is used */ 344#define E1000_P2VMAILBOX(_n) (0x00C00 + (4 * (_n))) 345#define E1000_VMBMEM(_n) (0x00800 + (64 * (_n))) 346#define E1000_VMOLR(_n) (0x05AD0 + (4 * (_n))) 347#define E1000_DVMOLR(_n) (0x0C038 + (64 * (_n))) 348#define E1000_VLVF(_n) (0x05D00 + (4 * (_n))) /* VLAN VM Filter */ 349#define E1000_VMVIR(_n) (0x03700 + (4 * (_n))) 350 351struct e1000_hw; 352 353u32 igb_rd32(struct e1000_hw *hw, u32 reg); 354 355/* write operations, indexed using DWORDS */ 356#define wr32(reg, val) \ 357do { \ 358 u8 __iomem *hw_addr = READ_ONCE((hw)->hw_addr); \ 359 if (!E1000_REMOVED(hw_addr)) \ 360 writel((val), &hw_addr[(reg)]); \ 361} while (0) 362 363#define rd32(reg) (igb_rd32(hw, reg)) 364 365#define wrfl() ((void)rd32(E1000_STATUS)) 366 367#define array_wr32(reg, offset, value) \ 368 wr32((reg) + ((offset) << 2), (value)) 369 370#define array_rd32(reg, offset) (igb_rd32(hw, reg + ((offset) << 2))) 371 372/* DMA Coalescing registers */ 373#define E1000_PCIEMISC 0x05BB8 /* PCIE misc config register */ 374 375/* Energy Efficient Ethernet "EEE" register */ 376#define E1000_IPCNFG 0x0E38 /* Internal PHY Configuration */ 377#define E1000_EEER 0x0E30 /* Energy Efficient Ethernet */ 378#define E1000_EEE_SU 0X0E34 /* EEE Setup */ 379#define E1000_EMIADD 0x10 /* Extended Memory Indirect Address */ 380#define E1000_EMIDATA 0x11 /* Extended Memory Indirect Data */ 381#define E1000_MMDAC 13 /* MMD Access Control */ 382#define E1000_MMDAAD 14 /* MMD Access Address/Data */ 383 384/* Thermal Sensor Register */ 385#define E1000_THSTAT 0x08110 /* Thermal Sensor Status */ 386 387/* OS2BMC Registers */ 388#define E1000_B2OSPC 0x08FE0 /* BMC2OS packets sent by BMC */ 389#define E1000_B2OGPRC 0x04158 /* BMC2OS packets received by host */ 390#define E1000_O2BGPTC 0x08FE4 /* OS2BMC packets received by BMC */ 391#define E1000_O2BSPC 0x0415C /* OS2BMC packets transmitted by host */ 392 393#define E1000_SRWR 0x12018 /* Shadow Ram Write Register - RW */ 394#define E1000_I210_FLMNGCTL 0x12038 395#define E1000_I210_FLMNGDATA 0x1203C 396#define E1000_I210_FLMNGCNT 0x12040 397 398#define E1000_I210_FLSWCTL 0x12048 399#define E1000_I210_FLSWDATA 0x1204C 400#define E1000_I210_FLSWCNT 0x12050 401 402#define E1000_I210_FLA 0x1201C 403 404#define E1000_I210_DTXMXPKTSZ 0x355C 405 406#define E1000_I210_TXDCTL(_n) (0x0E028 + ((_n) * 0x40)) 407 408#define E1000_I210_TQAVCTRL 0x3570 409#define E1000_I210_TQAVCC(_n) (0x3004 + ((_n) * 0x40)) 410#define E1000_I210_TQAVHC(_n) (0x300C + ((_n) * 0x40)) 411 412#define E1000_I210_RR2DCDELAY 0x5BF4 413 414#define E1000_INVM_DATA_REG(_n) (0x12120 + 4*(_n)) 415#define E1000_INVM_SIZE 64 /* Number of INVM Data Registers */ 416 417#define E1000_REMOVED(h) unlikely(!(h)) 418 419#endif