cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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ixgb_ee.h (2305B)


      1/* SPDX-License-Identifier: GPL-2.0 */
      2/* Copyright(c) 1999 - 2008 Intel Corporation. */
      3
      4#ifndef _IXGB_EE_H_
      5#define _IXGB_EE_H_
      6
      7#define IXGB_EEPROM_SIZE    64	/* Size in words */
      8
      9/* EEPROM Commands */
     10#define EEPROM_READ_OPCODE  0x6	/* EEPROM read opcode */
     11#define EEPROM_WRITE_OPCODE 0x5	/* EEPROM write opcode */
     12#define EEPROM_ERASE_OPCODE 0x7	/* EEPROM erase opcode */
     13#define EEPROM_EWEN_OPCODE  0x13	/* EEPROM erase/write enable */
     14#define EEPROM_EWDS_OPCODE  0x10	/* EEPROM erase/write disable */
     15
     16/* EEPROM MAP (Word Offsets) */
     17#define EEPROM_IA_1_2_REG        0x0000
     18#define EEPROM_IA_3_4_REG        0x0001
     19#define EEPROM_IA_5_6_REG        0x0002
     20#define EEPROM_COMPATIBILITY_REG 0x0003
     21#define EEPROM_PBA_1_2_REG       0x0008
     22#define EEPROM_PBA_3_4_REG       0x0009
     23#define EEPROM_INIT_CONTROL1_REG 0x000A
     24#define EEPROM_SUBSYS_ID_REG     0x000B
     25#define EEPROM_SUBVEND_ID_REG    0x000C
     26#define EEPROM_DEVICE_ID_REG     0x000D
     27#define EEPROM_VENDOR_ID_REG     0x000E
     28#define EEPROM_INIT_CONTROL2_REG 0x000F
     29#define EEPROM_SWDPINS_REG       0x0020
     30#define EEPROM_CIRCUIT_CTRL_REG  0x0021
     31#define EEPROM_D0_D3_POWER_REG   0x0022
     32#define EEPROM_FLASH_VERSION     0x0032
     33#define EEPROM_CHECKSUM_REG      0x003F
     34
     35/* Mask bits for fields in Word 0x0a of the EEPROM */
     36
     37#define EEPROM_ICW1_SIGNATURE_MASK  0xC000
     38#define EEPROM_ICW1_SIGNATURE_VALID 0x4000
     39#define EEPROM_ICW1_SIGNATURE_CLEAR 0x0000
     40
     41/* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */
     42#define EEPROM_SUM 0xBABA
     43
     44/* EEPROM Map Sizes (Byte Counts) */
     45#define PBA_SIZE 4
     46
     47/* EEPROM Map defines (WORD OFFSETS)*/
     48
     49/* EEPROM structure */
     50struct ixgb_ee_map_type {
     51	u8 mac_addr[ETH_ALEN];
     52	__le16 compatibility;
     53	__le16 reserved1[4];
     54	__le32 pba_number;
     55	__le16 init_ctrl_reg_1;
     56	__le16 subsystem_id;
     57	__le16 subvendor_id;
     58	__le16 device_id;
     59	__le16 vendor_id;
     60	__le16 init_ctrl_reg_2;
     61	__le16 oem_reserved[16];
     62	__le16 swdpins_reg;
     63	__le16 circuit_ctrl_reg;
     64	u8 d3_power;
     65	u8 d0_power;
     66	__le16 reserved2[28];
     67	__le16 checksum;
     68};
     69
     70/* EEPROM Functions */
     71u16 ixgb_read_eeprom(struct ixgb_hw *hw, u16 reg);
     72
     73bool ixgb_validate_eeprom_checksum(struct ixgb_hw *hw);
     74
     75void ixgb_update_eeprom_checksum(struct ixgb_hw *hw);
     76
     77void ixgb_write_eeprom(struct ixgb_hw *hw, u16 reg, u16 data);
     78
     79#endif				/* IXGB_EE_H */