cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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ixgbe_dcb.h (4670B)


      1/* SPDX-License-Identifier: GPL-2.0 */
      2/* Copyright(c) 1999 - 2018 Intel Corporation. */
      3
      4#ifndef _DCB_CONFIG_H_
      5#define _DCB_CONFIG_H_
      6
      7#include <linux/dcbnl.h>
      8#include "ixgbe_type.h"
      9
     10/* DCB data structures */
     11
     12#define IXGBE_MAX_PACKET_BUFFERS 8
     13#define MAX_USER_PRIORITY        8
     14#define MAX_BW_GROUP             8
     15#define BW_PERCENT               100
     16
     17#define DCB_TX_CONFIG            0
     18#define DCB_RX_CONFIG            1
     19
     20/* DCB error Codes */
     21#define DCB_SUCCESS              0
     22#define DCB_ERR_CONFIG           -1
     23#define DCB_ERR_PARAM            -2
     24
     25/* Transmit and receive Errors */
     26/* Error in bandwidth group allocation */
     27#define DCB_ERR_BW_GROUP        -3
     28/* Error in traffic class bandwidth allocation */
     29#define DCB_ERR_TC_BW           -4
     30/* Traffic class has both link strict and group strict enabled */
     31#define DCB_ERR_LS_GS           -5
     32/* Link strict traffic class has non zero bandwidth */
     33#define DCB_ERR_LS_BW_NONZERO   -6
     34/* Link strict bandwidth group has non zero bandwidth */
     35#define DCB_ERR_LS_BWG_NONZERO  -7
     36/*  Traffic class has zero bandwidth */
     37#define DCB_ERR_TC_BW_ZERO      -8
     38
     39#define DCB_NOT_IMPLEMENTED      0x7FFFFFFF
     40
     41struct dcb_pfc_tc_debug {
     42	u8  tc;
     43	u8  pause_status;
     44	u64 pause_quanta;
     45};
     46
     47enum strict_prio_type {
     48	prio_none = 0,
     49	prio_group,
     50	prio_link
     51};
     52
     53/* DCB capability definitions */
     54#define IXGBE_DCB_PG_SUPPORT        0x00000001
     55#define IXGBE_DCB_PFC_SUPPORT       0x00000002
     56#define IXGBE_DCB_BCN_SUPPORT       0x00000004
     57#define IXGBE_DCB_UP2TC_SUPPORT     0x00000008
     58#define IXGBE_DCB_GSP_SUPPORT       0x00000010
     59
     60#define IXGBE_DCB_8_TC_SUPPORT      0x80
     61
     62struct dcb_support {
     63	/* DCB capabilities */
     64	u32 capabilities;
     65
     66	/* Each bit represents a number of TCs configurable in the hw.
     67	 * If 8 traffic classes can be configured, the value is 0x80.
     68	 */
     69	u8  traffic_classes;
     70	u8  pfc_traffic_classes;
     71};
     72
     73/* Traffic class bandwidth allocation per direction */
     74struct tc_bw_alloc {
     75	u8 bwg_id;		  /* Bandwidth Group (BWG) ID */
     76	u8 bwg_percent;		  /* % of BWG's bandwidth */
     77	u8 link_percent;	  /* % of link bandwidth */
     78	u8 up_to_tc_bitmap;	  /* User Priority to Traffic Class mapping */
     79	u16 data_credits_refill;  /* Credit refill amount in 64B granularity */
     80	u16 data_credits_max;	  /* Max credits for a configured packet buffer
     81				   * in 64B granularity.*/
     82	enum strict_prio_type prio_type; /* Link or Group Strict Priority */
     83};
     84
     85enum dcb_pfc_type {
     86	pfc_disabled = 0,
     87	pfc_enabled_full,
     88	pfc_enabled_tx,
     89	pfc_enabled_rx
     90};
     91
     92/* Traffic class configuration */
     93struct tc_configuration {
     94	struct tc_bw_alloc path[2]; /* One each for Tx/Rx */
     95	enum dcb_pfc_type  dcb_pfc; /* Class based flow control setting */
     96
     97	u16 desc_credits_max; /* For Tx Descriptor arbitration */
     98	u8 tc; /* Traffic class (TC) */
     99};
    100
    101struct dcb_num_tcs {
    102	u8 pg_tcs;
    103	u8 pfc_tcs;
    104};
    105
    106struct ixgbe_dcb_config {
    107	struct dcb_support support;
    108	struct dcb_num_tcs num_tcs;
    109	struct tc_configuration tc_config[MAX_TRAFFIC_CLASS];
    110	u8     bw_percentage[2][MAX_BW_GROUP]; /* One each for Tx/Rx */
    111	bool   pfc_mode_enable;
    112
    113	u32  dcb_cfg_version; /* Not used...OS-specific? */
    114	u32  link_speed; /* For bandwidth allocation validation purpose */
    115};
    116
    117/* DCB driver APIs */
    118void ixgbe_dcb_unpack_pfc(struct ixgbe_dcb_config *cfg, u8 *pfc_en);
    119void ixgbe_dcb_unpack_refill(struct ixgbe_dcb_config *, int, u16 *);
    120void ixgbe_dcb_unpack_max(struct ixgbe_dcb_config *, u16 *);
    121void ixgbe_dcb_unpack_bwgid(struct ixgbe_dcb_config *, int, u8 *);
    122void ixgbe_dcb_unpack_prio(struct ixgbe_dcb_config *, int, u8 *);
    123void ixgbe_dcb_unpack_map(struct ixgbe_dcb_config *, int, u8 *);
    124u8 ixgbe_dcb_get_tc_from_up(struct ixgbe_dcb_config *, int, u8);
    125
    126/* DCB credits calculation */
    127s32 ixgbe_dcb_calculate_tc_credits(struct ixgbe_hw *,
    128				   struct ixgbe_dcb_config *, int, u8);
    129
    130/* DCB hw initialization */
    131s32 ixgbe_dcb_hw_ets(struct ixgbe_hw *hw, struct ieee_ets *ets, int max);
    132s32 ixgbe_dcb_hw_ets_config(struct ixgbe_hw *hw, u16 *refill, u16 *max,
    133			    u8 *bwg_id, u8 *prio_type, u8 *tc_prio);
    134s32 ixgbe_dcb_hw_pfc_config(struct ixgbe_hw *hw, u8 pfc_en, u8 *tc_prio);
    135s32 ixgbe_dcb_hw_config(struct ixgbe_hw *, struct ixgbe_dcb_config *);
    136
    137void ixgbe_dcb_read_rtrup2tc(struct ixgbe_hw *hw, u8 *map);
    138
    139/* DCB definitions for credit calculation */
    140#define DCB_CREDIT_QUANTUM	64   /* DCB Quantum */
    141#define MAX_CREDIT_REFILL       511  /* 0x1FF * 64B = 32704B */
    142#define DCB_MAX_TSO_SIZE        (32*1024) /* MAX TSO packet size supported in DCB mode */
    143#define MINIMUM_CREDIT_FOR_TSO  (DCB_MAX_TSO_SIZE/64 + 1) /* 513 for 32KB TSO packet */
    144#define MAX_CREDIT              4095 /* Maximum credit supported: 256KB * 1204 / 64B */
    145
    146#endif /* _DCB_CONFIG_H */