octep_main.h (9780B)
1/* SPDX-License-Identifier: GPL-2.0 */ 2/* Marvell Octeon EP (EndPoint) Ethernet Driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8#ifndef _OCTEP_MAIN_H_ 9#define _OCTEP_MAIN_H_ 10 11#include "octep_tx.h" 12#include "octep_rx.h" 13#include "octep_ctrl_mbox.h" 14 15#define OCTEP_DRV_NAME "octeon_ep" 16#define OCTEP_DRV_STRING "Marvell Octeon EndPoint NIC Driver" 17 18#define OCTEP_PCIID_CN93_PF 0xB200177d 19#define OCTEP_PCIID_CN93_VF 0xB203177d 20 21#define OCTEP_PCI_DEVICE_ID_CN93_PF 0xB200 22#define OCTEP_PCI_DEVICE_ID_CN93_VF 0xB203 23 24#define OCTEP_MAX_QUEUES 63 25#define OCTEP_MAX_IQ OCTEP_MAX_QUEUES 26#define OCTEP_MAX_OQ OCTEP_MAX_QUEUES 27#define OCTEP_MAX_VF 64 28 29#define OCTEP_MAX_MSIX_VECTORS OCTEP_MAX_OQ 30 31/* Flags to disable and enable Interrupts */ 32#define OCTEP_INPUT_INTR (1) 33#define OCTEP_OUTPUT_INTR (2) 34#define OCTEP_MBOX_INTR (4) 35#define OCTEP_ALL_INTR 0xff 36 37#define OCTEP_IQ_INTR_RESEND_BIT 59 38#define OCTEP_OQ_INTR_RESEND_BIT 59 39 40#define OCTEP_MMIO_REGIONS 3 41/* PCI address space mapping information. 42 * Each of the 3 address spaces given by BAR0, BAR2 and BAR4 of 43 * Octeon gets mapped to different physical address spaces in 44 * the kernel. 45 */ 46struct octep_mmio { 47 /* The physical address to which the PCI address space is mapped. */ 48 u8 __iomem *hw_addr; 49 50 /* Flag indicating the mapping was successful. */ 51 int mapped; 52}; 53 54struct octep_pci_win_regs { 55 u8 __iomem *pci_win_wr_addr; 56 u8 __iomem *pci_win_rd_addr; 57 u8 __iomem *pci_win_wr_data; 58 u8 __iomem *pci_win_rd_data; 59}; 60 61struct octep_hw_ops { 62 void (*setup_iq_regs)(struct octep_device *oct, int q); 63 void (*setup_oq_regs)(struct octep_device *oct, int q); 64 void (*setup_mbox_regs)(struct octep_device *oct, int mbox); 65 66 irqreturn_t (*non_ioq_intr_handler)(void *ioq_vector); 67 irqreturn_t (*ioq_intr_handler)(void *ioq_vector); 68 int (*soft_reset)(struct octep_device *oct); 69 void (*reinit_regs)(struct octep_device *oct); 70 u32 (*update_iq_read_idx)(struct octep_iq *iq); 71 72 void (*enable_interrupts)(struct octep_device *oct); 73 void (*disable_interrupts)(struct octep_device *oct); 74 75 void (*enable_io_queues)(struct octep_device *oct); 76 void (*disable_io_queues)(struct octep_device *oct); 77 void (*enable_iq)(struct octep_device *oct, int q); 78 void (*disable_iq)(struct octep_device *oct, int q); 79 void (*enable_oq)(struct octep_device *oct, int q); 80 void (*disable_oq)(struct octep_device *oct, int q); 81 void (*reset_io_queues)(struct octep_device *oct); 82 void (*dump_registers)(struct octep_device *oct); 83}; 84 85/* Octeon mailbox data */ 86struct octep_mbox_data { 87 u32 cmd; 88 u32 total_len; 89 u32 recv_len; 90 u32 rsvd; 91 u64 *data; 92}; 93 94/* Octeon device mailbox */ 95struct octep_mbox { 96 /* A spinlock to protect access to this q_mbox. */ 97 spinlock_t lock; 98 99 u32 q_no; 100 u32 state; 101 102 /* SLI_MAC_PF_MBOX_INT for PF, SLI_PKT_MBOX_INT for VF. */ 103 u8 __iomem *mbox_int_reg; 104 105 /* SLI_PKT_PF_VF_MBOX_SIG(0) for PF, 106 * SLI_PKT_PF_VF_MBOX_SIG(1) for VF. 107 */ 108 u8 __iomem *mbox_write_reg; 109 110 /* SLI_PKT_PF_VF_MBOX_SIG(1) for PF, 111 * SLI_PKT_PF_VF_MBOX_SIG(0) for VF. 112 */ 113 u8 __iomem *mbox_read_reg; 114 115 struct octep_mbox_data mbox_data; 116}; 117 118/* Tx/Rx queue vector per interrupt. */ 119struct octep_ioq_vector { 120 char name[OCTEP_MSIX_NAME_SIZE]; 121 struct napi_struct napi; 122 struct octep_device *octep_dev; 123 struct octep_iq *iq; 124 struct octep_oq *oq; 125 cpumask_t affinity_mask; 126}; 127 128/* Octeon hardware/firmware offload capability flags. */ 129#define OCTEP_CAP_TX_CHECKSUM BIT(0) 130#define OCTEP_CAP_RX_CHECKSUM BIT(1) 131#define OCTEP_CAP_TSO BIT(2) 132 133/* Link modes */ 134enum octep_link_mode_bit_indices { 135 OCTEP_LINK_MODE_10GBASE_T = 0, 136 OCTEP_LINK_MODE_10GBASE_R, 137 OCTEP_LINK_MODE_10GBASE_CR, 138 OCTEP_LINK_MODE_10GBASE_KR, 139 OCTEP_LINK_MODE_10GBASE_LR, 140 OCTEP_LINK_MODE_10GBASE_SR, 141 OCTEP_LINK_MODE_25GBASE_CR, 142 OCTEP_LINK_MODE_25GBASE_KR, 143 OCTEP_LINK_MODE_25GBASE_SR, 144 OCTEP_LINK_MODE_40GBASE_CR4, 145 OCTEP_LINK_MODE_40GBASE_KR4, 146 OCTEP_LINK_MODE_40GBASE_LR4, 147 OCTEP_LINK_MODE_40GBASE_SR4, 148 OCTEP_LINK_MODE_50GBASE_CR2, 149 OCTEP_LINK_MODE_50GBASE_KR2, 150 OCTEP_LINK_MODE_50GBASE_SR2, 151 OCTEP_LINK_MODE_50GBASE_CR, 152 OCTEP_LINK_MODE_50GBASE_KR, 153 OCTEP_LINK_MODE_50GBASE_LR, 154 OCTEP_LINK_MODE_50GBASE_SR, 155 OCTEP_LINK_MODE_100GBASE_CR4, 156 OCTEP_LINK_MODE_100GBASE_KR4, 157 OCTEP_LINK_MODE_100GBASE_LR4, 158 OCTEP_LINK_MODE_100GBASE_SR4, 159 OCTEP_LINK_MODE_NBITS 160}; 161 162/* Hardware interface link state information. */ 163struct octep_iface_link_info { 164 /* Bitmap of Supported link speeds/modes. */ 165 u64 supported_modes; 166 167 /* Bitmap of Advertised link speeds/modes. */ 168 u64 advertised_modes; 169 170 /* Negotiated link speed in Mbps. */ 171 u32 speed; 172 173 /* MTU */ 174 u16 mtu; 175 176 /* Autonegotation state. */ 177#define OCTEP_LINK_MODE_AUTONEG_SUPPORTED BIT(0) 178#define OCTEP_LINK_MODE_AUTONEG_ADVERTISED BIT(1) 179 u8 autoneg; 180 181 /* Pause frames setting. */ 182#define OCTEP_LINK_MODE_PAUSE_SUPPORTED BIT(0) 183#define OCTEP_LINK_MODE_PAUSE_ADVERTISED BIT(1) 184 u8 pause; 185 186 /* Admin state of the link (ifconfig <iface> up/down */ 187 u8 admin_up; 188 189 /* Operational state of the link: physical link is up down */ 190 u8 oper_up; 191}; 192 193/* The Octeon device specific private data structure. 194 * Each Octeon device has this structure to represent all its components. 195 */ 196struct octep_device { 197 struct octep_config *conf; 198 199 /* Octeon Chip type. */ 200 u16 chip_id; 201 u16 rev_id; 202 203 /* Device capabilities enabled */ 204 u64 caps_enabled; 205 /* Device capabilities supported */ 206 u64 caps_supported; 207 208 /* Pointer to basic Linux device */ 209 struct device *dev; 210 /* Linux PCI device pointer */ 211 struct pci_dev *pdev; 212 /* Netdev corresponding to the Octeon device */ 213 struct net_device *netdev; 214 215 /* memory mapped io range */ 216 struct octep_mmio mmio[OCTEP_MMIO_REGIONS]; 217 218 /* MAC address */ 219 u8 mac_addr[ETH_ALEN]; 220 221 /* Tx queues (IQ: Instruction Queue) */ 222 u16 num_iqs; 223 /* pkind value to be used in every Tx hardware descriptor */ 224 u8 pkind; 225 /* Pointers to Octeon Tx queues */ 226 struct octep_iq *iq[OCTEP_MAX_IQ]; 227 228 /* Rx queues (OQ: Output Queue) */ 229 u16 num_oqs; 230 /* Pointers to Octeon Rx queues */ 231 struct octep_oq *oq[OCTEP_MAX_OQ]; 232 233 /* Hardware port number of the PCIe interface */ 234 u16 pcie_port; 235 236 /* PCI Window registers to access some hardware CSRs */ 237 struct octep_pci_win_regs pci_win_regs; 238 /* Hardware operations */ 239 struct octep_hw_ops hw_ops; 240 241 /* IRQ info */ 242 u16 num_irqs; 243 u16 num_non_ioq_irqs; 244 char *non_ioq_irq_names; 245 struct msix_entry *msix_entries; 246 /* IOq information of it's corresponding MSI-X interrupt. */ 247 struct octep_ioq_vector *ioq_vector[OCTEP_MAX_QUEUES]; 248 249 /* Hardware Interface Tx statistics */ 250 struct octep_iface_tx_stats iface_tx_stats; 251 /* Hardware Interface Rx statistics */ 252 struct octep_iface_rx_stats iface_rx_stats; 253 254 /* Hardware Interface Link info like supported modes, aneg support */ 255 struct octep_iface_link_info link_info; 256 257 /* Mailbox to talk to VFs */ 258 struct octep_mbox *mbox[OCTEP_MAX_VF]; 259 260 /* Work entry to handle Tx timeout */ 261 struct work_struct tx_timeout_task; 262 263 /* control mbox over pf */ 264 struct octep_ctrl_mbox ctrl_mbox; 265 266 /* offset for iface stats */ 267 u32 ctrl_mbox_ifstats_offset; 268 269 /* Work entry to handle ctrl mbox interrupt */ 270 struct work_struct ctrl_mbox_task; 271 272}; 273 274static inline u16 OCTEP_MAJOR_REV(struct octep_device *oct) 275{ 276 u16 rev = (oct->rev_id & 0xC) >> 2; 277 278 return (rev == 0) ? 1 : rev; 279} 280 281static inline u16 OCTEP_MINOR_REV(struct octep_device *oct) 282{ 283 return (oct->rev_id & 0x3); 284} 285 286/* Octeon CSR read/write access APIs */ 287#define octep_write_csr(octep_dev, reg_off, value) \ 288 writel(value, (octep_dev)->mmio[0].hw_addr + (reg_off)) 289 290#define octep_write_csr64(octep_dev, reg_off, val64) \ 291 writeq(val64, (octep_dev)->mmio[0].hw_addr + (reg_off)) 292 293#define octep_read_csr(octep_dev, reg_off) \ 294 readl((octep_dev)->mmio[0].hw_addr + (reg_off)) 295 296#define octep_read_csr64(octep_dev, reg_off) \ 297 readq((octep_dev)->mmio[0].hw_addr + (reg_off)) 298 299/* Read windowed register. 300 * @param oct - pointer to the Octeon device. 301 * @param addr - Address of the register to read. 302 * 303 * This routine is called to read from the indirectly accessed 304 * Octeon registers that are visible through a PCI BAR0 mapped window 305 * register. 306 * @return - 64 bit value read from the register. 307 */ 308static inline u64 309OCTEP_PCI_WIN_READ(struct octep_device *oct, u64 addr) 310{ 311 u64 val64; 312 313 addr |= 1ull << 53; /* read 8 bytes */ 314 writeq(addr, oct->pci_win_regs.pci_win_rd_addr); 315 val64 = readq(oct->pci_win_regs.pci_win_rd_data); 316 317 dev_dbg(&oct->pdev->dev, 318 "%s: reg: 0x%016llx val: 0x%016llx\n", __func__, addr, val64); 319 320 return val64; 321} 322 323/* Write windowed register. 324 * @param oct - pointer to the Octeon device. 325 * @param addr - Address of the register to write 326 * @param val - Value to write 327 * 328 * This routine is called to write to the indirectly accessed 329 * Octeon registers that are visible through a PCI BAR0 mapped window 330 * register. 331 * @return Nothing. 332 */ 333static inline void 334OCTEP_PCI_WIN_WRITE(struct octep_device *oct, u64 addr, u64 val) 335{ 336 writeq(addr, oct->pci_win_regs.pci_win_wr_addr); 337 writeq(val, oct->pci_win_regs.pci_win_wr_data); 338 339 dev_dbg(&oct->pdev->dev, 340 "%s: reg: 0x%016llx val: 0x%016llx\n", __func__, addr, val); 341} 342 343extern struct workqueue_struct *octep_wq; 344 345int octep_device_setup(struct octep_device *oct); 346int octep_setup_iqs(struct octep_device *oct); 347void octep_free_iqs(struct octep_device *oct); 348void octep_clean_iqs(struct octep_device *oct); 349int octep_setup_oqs(struct octep_device *oct); 350void octep_free_oqs(struct octep_device *oct); 351void octep_oq_dbell_init(struct octep_device *oct); 352void octep_device_setup_cn93_pf(struct octep_device *oct); 353int octep_iq_process_completions(struct octep_iq *iq, u16 budget); 354int octep_oq_process_rx(struct octep_oq *oq, int budget); 355void octep_set_ethtool_ops(struct net_device *netdev); 356 357#endif /* _OCTEP_MAIN_H_ */