octep_rx.h (4925B)
1/* SPDX-License-Identifier: GPL-2.0 */ 2/* Marvell Octeon EP (EndPoint) Ethernet Driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8#ifndef _OCTEP_RX_H_ 9#define _OCTEP_RX_H_ 10 11/* struct octep_oq_desc_hw - Octeon Hardware OQ descriptor format. 12 * 13 * The descriptor ring is made of descriptors which have 2 64-bit values: 14 * 15 * @buffer_ptr: DMA address of the skb->data 16 * @info_ptr: DMA address of host memory, used to update pkt count by hw. 17 * This is currently unused to save pci writes. 18 */ 19struct octep_oq_desc_hw { 20 dma_addr_t buffer_ptr; 21 u64 info_ptr; 22}; 23 24#define OCTEP_OQ_DESC_SIZE (sizeof(struct octep_oq_desc_hw)) 25 26#define OCTEP_CSUM_L4_VERIFIED 0x1 27#define OCTEP_CSUM_IP_VERIFIED 0x2 28#define OCTEP_CSUM_VERIFIED (OCTEP_CSUM_L4_VERIFIED | OCTEP_CSUM_IP_VERIFIED) 29 30/* Extended Response Header in packet data received from Hardware. 31 * Includes metadata like checksum status. 32 * this is valid only if hardware/firmware published support for this. 33 * This is at offset 0 of packet data (skb->data). 34 */ 35struct octep_oq_resp_hw_ext { 36 /* Reserved. */ 37 u64 reserved:62; 38 39 /* checksum verified. */ 40 u64 csum_verified:2; 41}; 42 43#define OCTEP_OQ_RESP_HW_EXT_SIZE (sizeof(struct octep_oq_resp_hw_ext)) 44 45/* Length of Rx packet DMA'ed by Octeon to Host. 46 * this is in bigendian; so need to be converted to cpu endian. 47 * Octeon writes this at the beginning of Rx buffer (skb->data). 48 */ 49struct octep_oq_resp_hw { 50 /* The Length of the packet. */ 51 __be64 length; 52}; 53 54#define OCTEP_OQ_RESP_HW_SIZE (sizeof(struct octep_oq_resp_hw)) 55 56/* Pointer to data buffer. 57 * Driver keeps a pointer to the data buffer that it made available to 58 * the Octeon device. Since the descriptor ring keeps physical (bus) 59 * addresses, this field is required for the driver to keep track of 60 * the virtual address pointers. The fields are operated by 61 * OS-dependent routines. 62 */ 63struct octep_rx_buffer { 64 struct page *page; 65 66 /* length from rx hardware descriptor after converting to cpu endian */ 67 u64 len; 68}; 69 70#define OCTEP_OQ_RECVBUF_SIZE (sizeof(struct octep_rx_buffer)) 71 72/* Output Queue statistics. Each output queue has four stats fields. */ 73struct octep_oq_stats { 74 /* Number of packets received from the Device. */ 75 u64 packets; 76 77 /* Number of bytes received from the Device. */ 78 u64 bytes; 79 80 /* Number of times failed to allocate buffers. */ 81 u64 alloc_failures; 82}; 83 84#define OCTEP_OQ_STATS_SIZE (sizeof(struct octep_oq_stats)) 85 86/* Hardware interface Rx statistics */ 87struct octep_iface_rx_stats { 88 /* Received packets */ 89 u64 pkts; 90 91 /* Octets of received packets */ 92 u64 octets; 93 94 /* Received PAUSE and Control packets */ 95 u64 pause_pkts; 96 97 /* Received PAUSE and Control octets */ 98 u64 pause_octets; 99 100 /* Filtered DMAC0 packets */ 101 u64 dmac0_pkts; 102 103 /* Filtered DMAC0 octets */ 104 u64 dmac0_octets; 105 106 /* Packets dropped due to RX FIFO full */ 107 u64 dropped_pkts_fifo_full; 108 109 /* Octets dropped due to RX FIFO full */ 110 u64 dropped_octets_fifo_full; 111 112 /* Error packets */ 113 u64 err_pkts; 114 115 /* Filtered DMAC1 packets */ 116 u64 dmac1_pkts; 117 118 /* Filtered DMAC1 octets */ 119 u64 dmac1_octets; 120 121 /* NCSI-bound packets dropped */ 122 u64 ncsi_dropped_pkts; 123 124 /* NCSI-bound octets dropped */ 125 u64 ncsi_dropped_octets; 126 127 /* Multicast packets received. */ 128 u64 mcast_pkts; 129 130 /* Broadcast packets received. */ 131 u64 bcast_pkts; 132 133}; 134 135/* The Descriptor Ring Output Queue structure. 136 * This structure has all the information required to implement a 137 * Octeon OQ. 138 */ 139struct octep_oq { 140 u32 q_no; 141 142 struct octep_device *octep_dev; 143 struct net_device *netdev; 144 struct device *dev; 145 146 struct napi_struct *napi; 147 148 /* The receive buffer list. This list has the virtual addresses 149 * of the buffers. 150 */ 151 struct octep_rx_buffer *buff_info; 152 153 /* Pointer to the mapped packet credit register. 154 * Host writes number of info/buffer ptrs available to this register 155 */ 156 u8 __iomem *pkts_credit_reg; 157 158 /* Pointer to the mapped packet sent register. 159 * Octeon writes the number of packets DMA'ed to host memory 160 * in this register. 161 */ 162 u8 __iomem *pkts_sent_reg; 163 164 /* Statistics for this OQ. */ 165 struct octep_oq_stats stats; 166 167 /* Packets pending to be processed */ 168 u32 pkts_pending; 169 u32 last_pkt_count; 170 171 /* Index in the ring where the driver should read the next packet */ 172 u32 host_read_idx; 173 174 /* Number of descriptors in this ring. */ 175 u32 max_count; 176 u32 ring_size_mask; 177 178 /* The number of descriptors pending refill. */ 179 u32 refill_count; 180 181 /* Index in the ring where the driver will refill the 182 * descriptor's buffer 183 */ 184 u32 host_refill_idx; 185 u32 refill_threshold; 186 187 /* The size of each buffer pointed by the buffer pointer. */ 188 u32 buffer_size; 189 u32 max_single_buffer_size; 190 191 /* The 8B aligned descriptor ring starts at this address. */ 192 struct octep_oq_desc_hw *desc_ring; 193 194 /* DMA mapped address of the OQ descriptor ring. */ 195 dma_addr_t desc_ring_dma; 196}; 197 198#define OCTEP_OQ_SIZE (sizeof(struct octep_oq)) 199#endif /* _OCTEP_RX_H_ */