rpm.h (4160B)
1/* SPDX-License-Identifier: GPL-2.0 */ 2/* Marvell CN10K RPM driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8#ifndef RPM_H 9#define RPM_H 10 11#include <linux/bits.h> 12 13/* PCI device IDs */ 14#define PCI_DEVID_CN10K_RPM 0xA060 15 16/* Registers */ 17#define RPMX_CMRX_CFG 0x00 18#define RPMX_RX_TS_PREPEND BIT_ULL(22) 19#define RPMX_CMRX_SW_INT 0x180 20#define RPMX_CMRX_SW_INT_W1S 0x188 21#define RPMX_CMRX_SW_INT_ENA_W1S 0x198 22#define RPMX_CMRX_LINK_CFG 0x1070 23#define RPMX_MTI_PCS100X_CONTROL1 0x20000 24#define RPMX_MTI_LPCSX_CONTROL1 0x30000 25#define RPMX_MTI_PCS_LBK BIT_ULL(14) 26#define RPMX_MTI_LPCSX_CONTROL(id) (0x30000 | ((id) * 0x100)) 27 28#define RPMX_CMRX_LINK_RANGE_MASK GENMASK_ULL(19, 16) 29#define RPMX_CMRX_LINK_BASE_MASK GENMASK_ULL(11, 0) 30#define RPMX_MTI_MAC100X_COMMAND_CONFIG 0x8010 31#define RPMX_MTI_MAC100X_COMMAND_CONFIG_RX_P_DISABLE BIT_ULL(29) 32#define RPMX_MTI_MAC100X_COMMAND_CONFIG_TX_P_DISABLE BIT_ULL(28) 33#define RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_IGNORE BIT_ULL(8) 34#define RPMX_MTI_MAC100X_COMMAND_CONFIG_PFC_MODE BIT_ULL(19) 35#define RPMX_MTI_MAC100X_CL01_PAUSE_QUANTA 0x80A8 36#define RPMX_MTI_MAC100X_CL23_PAUSE_QUANTA 0x80B0 37#define RPMX_MTI_MAC100X_CL45_PAUSE_QUANTA 0x80B8 38#define RPMX_MTI_MAC100X_CL67_PAUSE_QUANTA 0x80C0 39#define RPMX_MTI_MAC100X_CL01_QUANTA_THRESH 0x80C8 40#define RPMX_MTI_MAC100X_CL23_QUANTA_THRESH 0x80D0 41#define RPMX_MTI_MAC100X_CL45_QUANTA_THRESH 0x80D8 42#define RPMX_MTI_MAC100X_CL67_QUANTA_THRESH 0x80E0 43#define RPMX_MTI_MAC100X_CL89_PAUSE_QUANTA 0x8108 44#define RPMX_MTI_MAC100X_CL1011_PAUSE_QUANTA 0x8110 45#define RPMX_MTI_MAC100X_CL1213_PAUSE_QUANTA 0x8118 46#define RPMX_MTI_MAC100X_CL1415_PAUSE_QUANTA 0x8120 47#define RPMX_MTI_MAC100X_CL89_QUANTA_THRESH 0x8128 48#define RPMX_MTI_MAC100X_CL1011_QUANTA_THRESH 0x8130 49#define RPMX_MTI_MAC100X_CL1213_QUANTA_THRESH 0x8138 50#define RPMX_MTI_MAC100X_CL1415_QUANTA_THRESH 0x8140 51#define RPM_DEFAULT_PAUSE_TIME 0xFFFF 52#define RPMX_CMR_RX_OVR_BP 0x4120 53#define RPMX_CMR_RX_OVR_BP_EN(x) BIT_ULL((x) + 8) 54#define RPMX_CMR_RX_OVR_BP_BP(x) BIT_ULL((x) + 4) 55#define RPMX_MTI_STAT_RX_STAT_PAGES_COUNTERX 0x12000 56#define RPMX_MTI_STAT_TX_STAT_PAGES_COUNTERX 0x13000 57#define RPMX_MTI_STAT_DATA_HI_CDC 0x10038 58 59#define RPM_LMAC_FWI 0xa 60#define RPM_TX_EN BIT_ULL(0) 61#define RPM_RX_EN BIT_ULL(1) 62#define RPMX_CMRX_PRT_CBFC_CTL 0x5B08 63#define RPMX_CMRX_PRT_CBFC_CTL_LOGL_EN_RX_SHIFT 33 64#define RPMX_CMRX_PRT_CBFC_CTL_PHYS_BP_SHIFT 16 65#define RPMX_CMRX_PRT_CBFC_CTL_LOGL_EN_TX_SHIFT 0 66#define RPM_PFC_CLASS_MASK GENMASK_ULL(48, 33) 67#define RPMX_MTI_MAC100X_CL89_QUANTA_THRESH 0x8128 68#define RPMX_MTI_MAC100X_COMMAND_CONFIG_TX_PAD_EN BIT_ULL(11) 69#define RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_IGNORE BIT_ULL(8) 70#define RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_FWD BIT_ULL(7) 71#define RPMX_MTI_MAC100X_CL01_PAUSE_QUANTA 0x80A8 72#define RPMX_MTI_MAC100X_CL89_PAUSE_QUANTA 0x8108 73#define RPM_DEFAULT_PAUSE_TIME 0xFFFF 74 75/* Function Declarations */ 76int rpm_get_nr_lmacs(void *rpmd); 77u8 rpm_get_lmac_type(void *rpmd, int lmac_id); 78int rpm_lmac_internal_loopback(void *rpmd, int lmac_id, bool enable); 79void rpm_lmac_enadis_rx_pause_fwding(void *rpmd, int lmac_id, bool enable); 80int rpm_lmac_get_pause_frm_status(void *cgxd, int lmac_id, u8 *tx_pause, 81 u8 *rx_pause); 82void rpm_lmac_pause_frm_config(void *rpmd, int lmac_id, bool enable); 83int rpm_lmac_enadis_pause_frm(void *rpmd, int lmac_id, u8 tx_pause, 84 u8 rx_pause); 85int rpm_get_tx_stats(void *rpmd, int lmac_id, int idx, u64 *tx_stat); 86int rpm_get_rx_stats(void *rpmd, int lmac_id, int idx, u64 *rx_stat); 87void rpm_lmac_ptp_config(void *rpmd, int lmac_id, bool enable); 88int rpm_lmac_rx_tx_enable(void *rpmd, int lmac_id, bool enable); 89int rpm_lmac_tx_enable(void *rpmd, int lmac_id, bool enable); 90int rpm_lmac_pfc_config(void *rpmd, int lmac_id, u8 tx_pause, u8 rx_pause, 91 u16 pfc_en); 92int rpm_lmac_get_pfc_frm_cfg(void *rpmd, int lmac_id, u8 *tx_pause, 93 u8 *rx_pause); 94#endif /* RPM_H */