rvu_struct.h (22102B)
1/* SPDX-License-Identifier: GPL-2.0 */ 2/* Marvell RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell. 5 * 6 */ 7 8#ifndef RVU_STRUCT_H 9#define RVU_STRUCT_H 10 11/* RVU Block revision IDs */ 12#define RVU_BLK_RVUM_REVID 0x01 13 14#define RVU_MULTI_BLK_VER 0x7ULL 15 16/* RVU Block Address Enumeration */ 17enum rvu_block_addr_e { 18 BLKADDR_RVUM = 0x0ULL, 19 BLKADDR_LMT = 0x1ULL, 20 BLKADDR_MSIX = 0x2ULL, 21 BLKADDR_NPA = 0x3ULL, 22 BLKADDR_NIX0 = 0x4ULL, 23 BLKADDR_NIX1 = 0x5ULL, 24 BLKADDR_NPC = 0x6ULL, 25 BLKADDR_SSO = 0x7ULL, 26 BLKADDR_SSOW = 0x8ULL, 27 BLKADDR_TIM = 0x9ULL, 28 BLKADDR_CPT0 = 0xaULL, 29 BLKADDR_CPT1 = 0xbULL, 30 BLKADDR_NDC_NIX0_RX = 0xcULL, 31 BLKADDR_NDC_NIX0_TX = 0xdULL, 32 BLKADDR_NDC_NPA0 = 0xeULL, 33 BLKADDR_NDC_NIX1_RX = 0x10ULL, 34 BLKADDR_NDC_NIX1_TX = 0x11ULL, 35 BLKADDR_APR = 0x16ULL, 36 BLK_COUNT = 0x17ULL, 37}; 38 39/* RVU Block Type Enumeration */ 40enum rvu_block_type_e { 41 BLKTYPE_RVUM = 0x0, 42 BLKTYPE_MSIX = 0x1, 43 BLKTYPE_LMT = 0x2, 44 BLKTYPE_NIX = 0x3, 45 BLKTYPE_NPA = 0x4, 46 BLKTYPE_NPC = 0x5, 47 BLKTYPE_SSO = 0x6, 48 BLKTYPE_SSOW = 0x7, 49 BLKTYPE_TIM = 0x8, 50 BLKTYPE_CPT = 0x9, 51 BLKTYPE_NDC = 0xa, 52 BLKTYPE_MAX = 0xa, 53}; 54 55/* RVU Admin function Interrupt Vector Enumeration */ 56enum rvu_af_int_vec_e { 57 RVU_AF_INT_VEC_POISON = 0x0, 58 RVU_AF_INT_VEC_PFFLR = 0x1, 59 RVU_AF_INT_VEC_PFME = 0x2, 60 RVU_AF_INT_VEC_GEN = 0x3, 61 RVU_AF_INT_VEC_MBOX = 0x4, 62 RVU_AF_INT_VEC_CNT = 0x5, 63}; 64 65/* CPT Admin function Interrupt Vector Enumeration */ 66enum cpt_af_int_vec_e { 67 CPT_AF_INT_VEC_FLT0 = 0x0, 68 CPT_AF_INT_VEC_FLT1 = 0x1, 69 CPT_AF_INT_VEC_RVU = 0x2, 70 CPT_AF_INT_VEC_RAS = 0x3, 71 CPT_AF_INT_VEC_CNT = 0x4, 72}; 73 74enum cpt_10k_af_int_vec_e { 75 CPT_10K_AF_INT_VEC_FLT0 = 0x0, 76 CPT_10K_AF_INT_VEC_FLT1 = 0x1, 77 CPT_10K_AF_INT_VEC_FLT2 = 0x2, 78 CPT_10K_AF_INT_VEC_RVU = 0x3, 79 CPT_10K_AF_INT_VEC_RAS = 0x4, 80 CPT_10K_AF_INT_VEC_CNT = 0x5, 81}; 82 83/* NPA Admin function Interrupt Vector Enumeration */ 84enum npa_af_int_vec_e { 85 NPA_AF_INT_VEC_RVU = 0x0, 86 NPA_AF_INT_VEC_GEN = 0x1, 87 NPA_AF_INT_VEC_AQ_DONE = 0x2, 88 NPA_AF_INT_VEC_AF_ERR = 0x3, 89 NPA_AF_INT_VEC_POISON = 0x4, 90 NPA_AF_INT_VEC_CNT = 0x5, 91}; 92 93/* NIX Admin function Interrupt Vector Enumeration */ 94enum nix_af_int_vec_e { 95 NIX_AF_INT_VEC_RVU = 0x0, 96 NIX_AF_INT_VEC_GEN = 0x1, 97 NIX_AF_INT_VEC_AQ_DONE = 0x2, 98 NIX_AF_INT_VEC_AF_ERR = 0x3, 99 NIX_AF_INT_VEC_POISON = 0x4, 100 NIX_AF_INT_VEC_CNT = 0x5, 101}; 102 103/** 104 * RVU PF Interrupt Vector Enumeration 105 */ 106enum rvu_pf_int_vec_e { 107 RVU_PF_INT_VEC_VFFLR0 = 0x0, 108 RVU_PF_INT_VEC_VFFLR1 = 0x1, 109 RVU_PF_INT_VEC_VFME0 = 0x2, 110 RVU_PF_INT_VEC_VFME1 = 0x3, 111 RVU_PF_INT_VEC_VFPF_MBOX0 = 0x4, 112 RVU_PF_INT_VEC_VFPF_MBOX1 = 0x5, 113 RVU_PF_INT_VEC_AFPF_MBOX = 0x6, 114 RVU_PF_INT_VEC_CNT = 0x7, 115}; 116 117/* NPA admin queue completion enumeration */ 118enum npa_aq_comp { 119 NPA_AQ_COMP_NOTDONE = 0x0, 120 NPA_AQ_COMP_GOOD = 0x1, 121 NPA_AQ_COMP_SWERR = 0x2, 122 NPA_AQ_COMP_CTX_POISON = 0x3, 123 NPA_AQ_COMP_CTX_FAULT = 0x4, 124 NPA_AQ_COMP_LOCKERR = 0x5, 125}; 126 127/* NPA admin queue context types */ 128enum npa_aq_ctype { 129 NPA_AQ_CTYPE_AURA = 0x0, 130 NPA_AQ_CTYPE_POOL = 0x1, 131}; 132 133/* NPA admin queue instruction opcodes */ 134enum npa_aq_instop { 135 NPA_AQ_INSTOP_NOP = 0x0, 136 NPA_AQ_INSTOP_INIT = 0x1, 137 NPA_AQ_INSTOP_WRITE = 0x2, 138 NPA_AQ_INSTOP_READ = 0x3, 139 NPA_AQ_INSTOP_LOCK = 0x4, 140 NPA_AQ_INSTOP_UNLOCK = 0x5, 141}; 142 143/* ALLOC/FREE input queues Enumeration from coprocessors */ 144enum npa_inpq { 145 NPA_INPQ_NIX0_RX = 0x0, 146 NPA_INPQ_NIX0_TX = 0x1, 147 NPA_INPQ_NIX1_RX = 0x2, 148 NPA_INPQ_NIX1_TX = 0x3, 149 NPA_INPQ_SSO = 0x4, 150 NPA_INPQ_TIM = 0x5, 151 NPA_INPQ_DPI = 0x6, 152 NPA_INPQ_AURA_OP = 0xe, 153 NPA_INPQ_INTERNAL_RSV = 0xf, 154}; 155 156/* NPA admin queue instruction structure */ 157struct npa_aq_inst_s { 158 u64 op : 4; /* W0 */ 159 u64 ctype : 4; 160 u64 lf : 9; 161 u64 reserved_17_23 : 7; 162 u64 cindex : 20; 163 u64 reserved_44_62 : 19; 164 u64 doneint : 1; 165 u64 res_addr; /* W1 */ 166}; 167 168/* NPA admin queue result structure */ 169struct npa_aq_res_s { 170 u64 op : 4; /* W0 */ 171 u64 ctype : 4; 172 u64 compcode : 8; 173 u64 doneint : 1; 174 u64 reserved_17_63 : 47; 175 u64 reserved_64_127; /* W1 */ 176}; 177 178struct npa_aura_s { 179 u64 pool_addr; /* W0 */ 180 u64 ena : 1; /* W1 */ 181 u64 reserved_65 : 2; 182 u64 pool_caching : 1; 183 u64 pool_way_mask : 16; 184 u64 avg_con : 9; 185 u64 reserved_93 : 1; 186 u64 pool_drop_ena : 1; 187 u64 aura_drop_ena : 1; 188 u64 bp_ena : 2; 189 u64 reserved_98_103 : 6; 190 u64 aura_drop : 8; 191 u64 shift : 6; 192 u64 reserved_118_119 : 2; 193 u64 avg_level : 8; 194 u64 count : 36; /* W2 */ 195 u64 reserved_164_167 : 4; 196 u64 nix0_bpid : 9; 197 u64 reserved_177_179 : 3; 198 u64 nix1_bpid : 9; 199 u64 reserved_189_191 : 3; 200 u64 limit : 36; /* W3 */ 201 u64 reserved_228_231 : 4; 202 u64 bp : 8; 203 u64 reserved_241_243 : 3; 204 u64 fc_be : 1; 205 u64 fc_ena : 1; 206 u64 fc_up_crossing : 1; 207 u64 fc_stype : 2; 208 u64 fc_hyst_bits : 4; 209 u64 reserved_252_255 : 4; 210 u64 fc_addr; /* W4 */ 211 u64 pool_drop : 8; /* W5 */ 212 u64 update_time : 16; 213 u64 err_int : 8; 214 u64 err_int_ena : 8; 215 u64 thresh_int : 1; 216 u64 thresh_int_ena : 1; 217 u64 thresh_up : 1; 218 u64 reserved_363 : 1; 219 u64 thresh_qint_idx : 7; 220 u64 reserved_371 : 1; 221 u64 err_qint_idx : 7; 222 u64 reserved_379_383 : 5; 223 u64 thresh : 36; /* W6*/ 224 u64 rsvd_423_420 : 4; 225 u64 fc_msh_dst : 11; 226 u64 reserved_435_447 : 13; 227 u64 reserved_448_511; /* W7 */ 228}; 229 230struct npa_pool_s { 231 u64 stack_base; /* W0 */ 232 u64 ena : 1; 233 u64 nat_align : 1; 234 u64 reserved_66_67 : 2; 235 u64 stack_caching : 1; 236 u64 reserved_70_71 : 3; 237 u64 stack_way_mask : 16; 238 u64 buf_offset : 12; 239 u64 reserved_100_103 : 4; 240 u64 buf_size : 11; 241 u64 reserved_115_127 : 13; 242 u64 stack_max_pages : 32; 243 u64 stack_pages : 32; 244 u64 op_pc : 48; 245 u64 reserved_240_255 : 16; 246 u64 stack_offset : 4; 247 u64 reserved_260_263 : 4; 248 u64 shift : 6; 249 u64 reserved_270_271 : 2; 250 u64 avg_level : 8; 251 u64 avg_con : 9; 252 u64 fc_ena : 1; 253 u64 fc_stype : 2; 254 u64 fc_hyst_bits : 4; 255 u64 fc_up_crossing : 1; 256 u64 fc_be : 1; 257 u64 reserved_298_299 : 2; 258 u64 update_time : 16; 259 u64 reserved_316_319 : 4; 260 u64 fc_addr; /* W5 */ 261 u64 ptr_start; /* W6 */ 262 u64 ptr_end; /* W7 */ 263 u64 reserved_512_535 : 24; 264 u64 err_int : 8; 265 u64 err_int_ena : 8; 266 u64 thresh_int : 1; 267 u64 thresh_int_ena : 1; 268 u64 thresh_up : 1; 269 u64 reserved_555 : 1; 270 u64 thresh_qint_idx : 7; 271 u64 reserved_563 : 1; 272 u64 err_qint_idx : 7; 273 u64 reserved_571_575 : 5; 274 u64 thresh : 36; 275 u64 rsvd_615_612 : 4; 276 u64 fc_msh_dst : 11; 277 u64 reserved_627_639 : 13; 278 u64 reserved_640_703; /* W10 */ 279 u64 reserved_704_767; /* W11 */ 280 u64 reserved_768_831; /* W12 */ 281 u64 reserved_832_895; /* W13 */ 282 u64 reserved_896_959; /* W14 */ 283 u64 reserved_960_1023; /* W15 */ 284}; 285 286/* NIX admin queue completion status */ 287enum nix_aq_comp { 288 NIX_AQ_COMP_NOTDONE = 0x0, 289 NIX_AQ_COMP_GOOD = 0x1, 290 NIX_AQ_COMP_SWERR = 0x2, 291 NIX_AQ_COMP_CTX_POISON = 0x3, 292 NIX_AQ_COMP_CTX_FAULT = 0x4, 293 NIX_AQ_COMP_LOCKERR = 0x5, 294 NIX_AQ_COMP_SQB_ALLOC_FAIL = 0x6, 295}; 296 297/* NIX admin queue context types */ 298enum nix_aq_ctype { 299 NIX_AQ_CTYPE_RQ = 0x0, 300 NIX_AQ_CTYPE_SQ = 0x1, 301 NIX_AQ_CTYPE_CQ = 0x2, 302 NIX_AQ_CTYPE_MCE = 0x3, 303 NIX_AQ_CTYPE_RSS = 0x4, 304 NIX_AQ_CTYPE_DYNO = 0x5, 305 NIX_AQ_CTYPE_BANDPROF = 0x6, 306}; 307 308/* NIX admin queue instruction opcodes */ 309enum nix_aq_instop { 310 NIX_AQ_INSTOP_NOP = 0x0, 311 NIX_AQ_INSTOP_INIT = 0x1, 312 NIX_AQ_INSTOP_WRITE = 0x2, 313 NIX_AQ_INSTOP_READ = 0x3, 314 NIX_AQ_INSTOP_LOCK = 0x4, 315 NIX_AQ_INSTOP_UNLOCK = 0x5, 316}; 317 318/* NIX admin queue instruction structure */ 319struct nix_aq_inst_s { 320 u64 op : 4; 321 u64 ctype : 4; 322 u64 lf : 9; 323 u64 reserved_17_23 : 7; 324 u64 cindex : 20; 325 u64 reserved_44_62 : 19; 326 u64 doneint : 1; 327 u64 res_addr; /* W1 */ 328}; 329 330/* NIX admin queue result structure */ 331struct nix_aq_res_s { 332 u64 op : 4; 333 u64 ctype : 4; 334 u64 compcode : 8; 335 u64 doneint : 1; 336 u64 reserved_17_63 : 47; 337 u64 reserved_64_127; /* W1 */ 338}; 339 340/* NIX Completion queue context structure */ 341struct nix_cq_ctx_s { 342 u64 base; 343 u64 rsvd_64_67 : 4; 344 u64 bp_ena : 1; 345 u64 rsvd_69_71 : 3; 346 u64 bpid : 9; 347 u64 rsvd_81_83 : 3; 348 u64 qint_idx : 7; 349 u64 cq_err : 1; 350 u64 cint_idx : 7; 351 u64 avg_con : 9; 352 u64 wrptr : 20; 353 u64 tail : 20; 354 u64 head : 20; 355 u64 avg_level : 8; 356 u64 update_time : 16; 357 u64 bp : 8; 358 u64 drop : 8; 359 u64 drop_ena : 1; 360 u64 ena : 1; 361 u64 rsvd_210_211 : 2; 362 u64 substream : 20; 363 u64 caching : 1; 364 u64 rsvd_233_235 : 3; 365 u64 qsize : 4; 366 u64 cq_err_int : 8; 367 u64 cq_err_int_ena : 8; 368}; 369 370/* CN10K NIX Receive queue context structure */ 371struct nix_cn10k_rq_ctx_s { 372 u64 ena : 1; 373 u64 sso_ena : 1; 374 u64 ipsech_ena : 1; 375 u64 ena_wqwd : 1; 376 u64 cq : 20; 377 u64 rsvd_36_24 : 13; 378 u64 lenerr_dis : 1; 379 u64 csum_il4_dis : 1; 380 u64 csum_ol4_dis : 1; 381 u64 len_il4_dis : 1; 382 u64 len_il3_dis : 1; 383 u64 len_ol4_dis : 1; 384 u64 len_ol3_dis : 1; 385 u64 wqe_aura : 20; 386 u64 spb_aura : 20; 387 u64 lpb_aura : 20; 388 u64 sso_grp : 10; 389 u64 sso_tt : 2; 390 u64 pb_caching : 2; 391 u64 wqe_caching : 1; 392 u64 xqe_drop_ena : 1; 393 u64 spb_drop_ena : 1; 394 u64 lpb_drop_ena : 1; 395 u64 pb_stashing : 1; 396 u64 ipsecd_drop_ena : 1; 397 u64 chi_ena : 1; 398 u64 rsvd_127_125 : 3; 399 u64 band_prof_id : 10; /* W2 */ 400 u64 rsvd_138 : 1; 401 u64 policer_ena : 1; 402 u64 spb_sizem1 : 6; 403 u64 wqe_skip : 2; 404 u64 rsvd_150_148 : 3; 405 u64 spb_ena : 1; 406 u64 lpb_sizem1 : 12; 407 u64 first_skip : 7; 408 u64 rsvd_171 : 1; 409 u64 later_skip : 6; 410 u64 xqe_imm_size : 6; 411 u64 rsvd_189_184 : 6; 412 u64 xqe_imm_copy : 1; 413 u64 xqe_hdr_split : 1; 414 u64 xqe_drop : 8; /* W3 */ 415 u64 xqe_pass : 8; 416 u64 wqe_pool_drop : 8; 417 u64 wqe_pool_pass : 8; 418 u64 spb_aura_drop : 8; 419 u64 spb_aura_pass : 8; 420 u64 spb_pool_drop : 8; 421 u64 spb_pool_pass : 8; 422 u64 lpb_aura_drop : 8; /* W4 */ 423 u64 lpb_aura_pass : 8; 424 u64 lpb_pool_drop : 8; 425 u64 lpb_pool_pass : 8; 426 u64 rsvd_291_288 : 4; 427 u64 rq_int : 8; 428 u64 rq_int_ena : 8; 429 u64 qint_idx : 7; 430 u64 rsvd_319_315 : 5; 431 u64 ltag : 24; /* W5 */ 432 u64 good_utag : 8; 433 u64 bad_utag : 8; 434 u64 flow_tagw : 6; 435 u64 ipsec_vwqe : 1; 436 u64 vwqe_ena : 1; 437 u64 vwqe_wait : 8; 438 u64 max_vsize_exp : 4; 439 u64 vwqe_skip : 2; 440 u64 rsvd_383_382 : 2; 441 u64 octs : 48; /* W6 */ 442 u64 rsvd_447_432 : 16; 443 u64 pkts : 48; /* W7 */ 444 u64 rsvd_511_496 : 16; 445 u64 drop_octs : 48; /* W8 */ 446 u64 rsvd_575_560 : 16; 447 u64 drop_pkts : 48; /* W9 */ 448 u64 rsvd_639_624 : 16; 449 u64 re_pkts : 48; /* W10 */ 450 u64 rsvd_703_688 : 16; 451 u64 rsvd_767_704; /* W11 */ 452 u64 rsvd_831_768; /* W12 */ 453 u64 rsvd_895_832; /* W13 */ 454 u64 rsvd_959_896; /* W14 */ 455 u64 rsvd_1023_960; /* W15 */ 456}; 457 458/* CN10K NIX Send queue context structure */ 459struct nix_cn10k_sq_ctx_s { 460 u64 ena : 1; 461 u64 qint_idx : 6; 462 u64 substream : 20; 463 u64 sdp_mcast : 1; 464 u64 cq : 20; 465 u64 sqe_way_mask : 16; 466 u64 smq : 10; /* W1 */ 467 u64 cq_ena : 1; 468 u64 xoff : 1; 469 u64 sso_ena : 1; 470 u64 smq_rr_weight : 14; 471 u64 default_chan : 12; 472 u64 sqb_count : 16; 473 u64 rsvd_120_119 : 2; 474 u64 smq_rr_count_lb : 7; 475 u64 smq_rr_count_ub : 25; /* W2 */ 476 u64 sqb_aura : 20; 477 u64 sq_int : 8; 478 u64 sq_int_ena : 8; 479 u64 sqe_stype : 2; 480 u64 rsvd_191 : 1; 481 u64 max_sqe_size : 2; /* W3 */ 482 u64 cq_limit : 8; 483 u64 lmt_dis : 1; 484 u64 mnq_dis : 1; 485 u64 smq_next_sq : 20; 486 u64 smq_lso_segnum : 8; 487 u64 tail_offset : 6; 488 u64 smenq_offset : 6; 489 u64 head_offset : 6; 490 u64 smenq_next_sqb_vld : 1; 491 u64 smq_pend : 1; 492 u64 smq_next_sq_vld : 1; 493 u64 rsvd_255_253 : 3; 494 u64 next_sqb : 64; /* W4 */ 495 u64 tail_sqb : 64; /* W5 */ 496 u64 smenq_sqb : 64; /* W6 */ 497 u64 smenq_next_sqb : 64; /* W7 */ 498 u64 head_sqb : 64; /* W8 */ 499 u64 rsvd_583_576 : 8; /* W9 */ 500 u64 vfi_lso_total : 18; 501 u64 vfi_lso_sizem1 : 3; 502 u64 vfi_lso_sb : 8; 503 u64 vfi_lso_mps : 14; 504 u64 vfi_lso_vlan0_ins_ena : 1; 505 u64 vfi_lso_vlan1_ins_ena : 1; 506 u64 vfi_lso_vld : 1; 507 u64 rsvd_639_630 : 10; 508 u64 scm_lso_rem : 18; /* W10 */ 509 u64 rsvd_703_658 : 46; 510 u64 octs : 48; /* W11 */ 511 u64 rsvd_767_752 : 16; 512 u64 pkts : 48; /* W12 */ 513 u64 rsvd_831_816 : 16; 514 u64 rsvd_895_832 : 64; /* W13 */ 515 u64 dropped_octs : 48; 516 u64 rsvd_959_944 : 16; 517 u64 dropped_pkts : 48; 518 u64 rsvd_1023_1008 : 16; 519}; 520 521/* NIX Receive queue context structure */ 522struct nix_rq_ctx_s { 523 u64 ena : 1; 524 u64 sso_ena : 1; 525 u64 ipsech_ena : 1; 526 u64 ena_wqwd : 1; 527 u64 cq : 20; 528 u64 substream : 20; 529 u64 wqe_aura : 20; 530 u64 spb_aura : 20; 531 u64 lpb_aura : 20; 532 u64 sso_grp : 10; 533 u64 sso_tt : 2; 534 u64 pb_caching : 2; 535 u64 wqe_caching : 1; 536 u64 xqe_drop_ena : 1; 537 u64 spb_drop_ena : 1; 538 u64 lpb_drop_ena : 1; 539 u64 rsvd_127_122 : 6; 540 u64 rsvd_139_128 : 12; /* W2 */ 541 u64 spb_sizem1 : 6; 542 u64 wqe_skip : 2; 543 u64 rsvd_150_148 : 3; 544 u64 spb_ena : 1; 545 u64 lpb_sizem1 : 12; 546 u64 first_skip : 7; 547 u64 rsvd_171 : 1; 548 u64 later_skip : 6; 549 u64 xqe_imm_size : 6; 550 u64 rsvd_189_184 : 6; 551 u64 xqe_imm_copy : 1; 552 u64 xqe_hdr_split : 1; 553 u64 xqe_drop : 8; /* W3*/ 554 u64 xqe_pass : 8; 555 u64 wqe_pool_drop : 8; 556 u64 wqe_pool_pass : 8; 557 u64 spb_aura_drop : 8; 558 u64 spb_aura_pass : 8; 559 u64 spb_pool_drop : 8; 560 u64 spb_pool_pass : 8; 561 u64 lpb_aura_drop : 8; /* W4 */ 562 u64 lpb_aura_pass : 8; 563 u64 lpb_pool_drop : 8; 564 u64 lpb_pool_pass : 8; 565 u64 rsvd_291_288 : 4; 566 u64 rq_int : 8; 567 u64 rq_int_ena : 8; 568 u64 qint_idx : 7; 569 u64 rsvd_319_315 : 5; 570 u64 ltag : 24; /* W5 */ 571 u64 good_utag : 8; 572 u64 bad_utag : 8; 573 u64 flow_tagw : 6; 574 u64 rsvd_383_366 : 18; 575 u64 octs : 48; /* W6 */ 576 u64 rsvd_447_432 : 16; 577 u64 pkts : 48; /* W7 */ 578 u64 rsvd_511_496 : 16; 579 u64 drop_octs : 48; /* W8 */ 580 u64 rsvd_575_560 : 16; 581 u64 drop_pkts : 48; /* W9 */ 582 u64 rsvd_639_624 : 16; 583 u64 re_pkts : 48; /* W10 */ 584 u64 rsvd_703_688 : 16; 585 u64 rsvd_767_704; /* W11 */ 586 u64 rsvd_831_768; /* W12 */ 587 u64 rsvd_895_832; /* W13 */ 588 u64 rsvd_959_896; /* W14 */ 589 u64 rsvd_1023_960; /* W15 */ 590}; 591 592/* NIX sqe sizes */ 593enum nix_maxsqesz { 594 NIX_MAXSQESZ_W16 = 0x0, 595 NIX_MAXSQESZ_W8 = 0x1, 596}; 597 598/* NIX SQB caching type */ 599enum nix_stype { 600 NIX_STYPE_STF = 0x0, 601 NIX_STYPE_STT = 0x1, 602 NIX_STYPE_STP = 0x2, 603}; 604 605/* NIX Send queue context structure */ 606struct nix_sq_ctx_s { 607 u64 ena : 1; 608 u64 qint_idx : 6; 609 u64 substream : 20; 610 u64 sdp_mcast : 1; 611 u64 cq : 20; 612 u64 sqe_way_mask : 16; 613 u64 smq : 9; 614 u64 cq_ena : 1; 615 u64 xoff : 1; 616 u64 sso_ena : 1; 617 u64 smq_rr_quantum : 24; 618 u64 default_chan : 12; 619 u64 sqb_count : 16; 620 u64 smq_rr_count : 25; 621 u64 sqb_aura : 20; 622 u64 sq_int : 8; 623 u64 sq_int_ena : 8; 624 u64 sqe_stype : 2; 625 u64 rsvd_191 : 1; 626 u64 max_sqe_size : 2; 627 u64 cq_limit : 8; 628 u64 lmt_dis : 1; 629 u64 mnq_dis : 1; 630 u64 smq_next_sq : 20; 631 u64 smq_lso_segnum : 8; 632 u64 tail_offset : 6; 633 u64 smenq_offset : 6; 634 u64 head_offset : 6; 635 u64 smenq_next_sqb_vld : 1; 636 u64 smq_pend : 1; 637 u64 smq_next_sq_vld : 1; 638 u64 rsvd_255_253 : 3; 639 u64 next_sqb : 64;/* W4 */ 640 u64 tail_sqb : 64;/* W5 */ 641 u64 smenq_sqb : 64;/* W6 */ 642 u64 smenq_next_sqb : 64;/* W7 */ 643 u64 head_sqb : 64;/* W8 */ 644 u64 rsvd_583_576 : 8; 645 u64 vfi_lso_total : 18; 646 u64 vfi_lso_sizem1 : 3; 647 u64 vfi_lso_sb : 8; 648 u64 vfi_lso_mps : 14; 649 u64 vfi_lso_vlan0_ins_ena : 1; 650 u64 vfi_lso_vlan1_ins_ena : 1; 651 u64 vfi_lso_vld : 1; 652 u64 rsvd_639_630 : 10; 653 u64 scm_lso_rem : 18; 654 u64 rsvd_703_658 : 46; 655 u64 octs : 48; 656 u64 rsvd_767_752 : 16; 657 u64 pkts : 48; 658 u64 rsvd_831_816 : 16; 659 u64 rsvd_895_832 : 64;/* W13 */ 660 u64 dropped_octs : 48; 661 u64 rsvd_959_944 : 16; 662 u64 dropped_pkts : 48; 663 u64 rsvd_1023_1008 : 16; 664}; 665 666/* NIX Receive side scaling entry structure*/ 667struct nix_rsse_s { 668 uint32_t rq : 20; 669 uint32_t reserved_20_31 : 12; 670 671}; 672 673/* NIX receive multicast/mirror entry structure */ 674struct nix_rx_mce_s { 675 uint64_t op : 2; 676 uint64_t rsvd_2 : 1; 677 uint64_t eol : 1; 678 uint64_t index : 20; 679 uint64_t rsvd_31_24 : 8; 680 uint64_t pf_func : 16; 681 uint64_t next : 16; 682}; 683 684enum nix_band_prof_layers { 685 BAND_PROF_LEAF_LAYER = 0, 686 BAND_PROF_INVAL_LAYER = 1, 687 BAND_PROF_MID_LAYER = 2, 688 BAND_PROF_TOP_LAYER = 3, 689 BAND_PROF_NUM_LAYERS = 4, 690}; 691 692enum NIX_RX_BAND_PROF_ACTIONRESULT_E { 693 NIX_RX_BAND_PROF_ACTIONRESULT_PASS = 0x0, 694 NIX_RX_BAND_PROF_ACTIONRESULT_DROP = 0x1, 695 NIX_RX_BAND_PROF_ACTIONRESULT_RED = 0x2, 696}; 697 698enum nix_band_prof_pc_mode { 699 NIX_RX_PC_MODE_VLAN = 0, 700 NIX_RX_PC_MODE_DSCP = 1, 701 NIX_RX_PC_MODE_GEN = 2, 702 NIX_RX_PC_MODE_RSVD = 3, 703}; 704 705/* NIX ingress policer bandwidth profile structure */ 706struct nix_bandprof_s { 707 uint64_t pc_mode : 2; /* W0 */ 708 uint64_t icolor : 2; 709 uint64_t tnl_ena : 1; 710 uint64_t reserved_5_7 : 3; 711 uint64_t peir_exponent : 5; 712 uint64_t reserved_13_15 : 3; 713 uint64_t pebs_exponent : 5; 714 uint64_t reserved_21_23 : 3; 715 uint64_t cir_exponent : 5; 716 uint64_t reserved_29_31 : 3; 717 uint64_t cbs_exponent : 5; 718 uint64_t reserved_37_39 : 3; 719 uint64_t peir_mantissa : 8; 720 uint64_t pebs_mantissa : 8; 721 uint64_t cir_mantissa : 8; 722 uint64_t cbs_mantissa : 8; /* W1 */ 723 uint64_t lmode : 1; 724 uint64_t l_sellect : 3; 725 uint64_t rdiv : 4; 726 uint64_t adjust_exponent : 5; 727 uint64_t reserved_85_86 : 2; 728 uint64_t adjust_mantissa : 9; 729 uint64_t gc_action : 2; 730 uint64_t yc_action : 2; 731 uint64_t rc_action : 2; 732 uint64_t meter_algo : 2; 733 uint64_t band_prof_id : 7; 734 uint64_t reserved_111_118 : 8; 735 uint64_t hl_en : 1; 736 uint64_t reserved_120_127 : 8; 737 uint64_t ts : 48; /* W2 */ 738 uint64_t reserved_176_191 : 16; 739 uint64_t pe_accum : 32; /* W3 */ 740 uint64_t c_accum : 32; 741 uint64_t green_pkt_pass : 48; /* W4 */ 742 uint64_t reserved_304_319 : 16; 743 uint64_t yellow_pkt_pass : 48; /* W5 */ 744 uint64_t reserved_368_383 : 16; 745 uint64_t red_pkt_pass : 48; /* W6 */ 746 uint64_t reserved_432_447 : 16; 747 uint64_t green_octs_pass : 48; /* W7 */ 748 uint64_t reserved_496_511 : 16; 749 uint64_t yellow_octs_pass : 48; /* W8 */ 750 uint64_t reserved_560_575 : 16; 751 uint64_t red_octs_pass : 48; /* W9 */ 752 uint64_t reserved_624_639 : 16; 753 uint64_t green_pkt_drop : 48; /* W10 */ 754 uint64_t reserved_688_703 : 16; 755 uint64_t yellow_pkt_drop : 48; /* W11 */ 756 uint64_t reserved_752_767 : 16; 757 uint64_t red_pkt_drop : 48; /* W12 */ 758 uint64_t reserved_816_831 : 16; 759 uint64_t green_octs_drop : 48; /* W13 */ 760 uint64_t reserved_880_895 : 16; 761 uint64_t yellow_octs_drop : 48; /* W14 */ 762 uint64_t reserved_944_959 : 16; 763 uint64_t red_octs_drop : 48; /* W15 */ 764 uint64_t reserved_1008_1023 : 16; 765}; 766 767enum nix_lsoalg { 768 NIX_LSOALG_NOP, 769 NIX_LSOALG_ADD_SEGNUM, 770 NIX_LSOALG_ADD_PAYLEN, 771 NIX_LSOALG_ADD_OFFSET, 772 NIX_LSOALG_TCP_FLAGS, 773}; 774 775enum nix_txlayer { 776 NIX_TXLAYER_OL3, 777 NIX_TXLAYER_OL4, 778 NIX_TXLAYER_IL3, 779 NIX_TXLAYER_IL4, 780}; 781 782struct nix_lso_format { 783 u64 offset : 8; 784 u64 layer : 2; 785 u64 rsvd_10_11 : 2; 786 u64 sizem1 : 2; 787 u64 rsvd_14_15 : 2; 788 u64 alg : 3; 789 u64 rsvd_19_63 : 45; 790}; 791 792struct nix_rx_flowkey_alg { 793 u64 key_offset :6; 794 u64 ln_mask :1; 795 u64 fn_mask :1; 796 u64 hdr_offset :8; 797 u64 bytesm1 :5; 798 u64 lid :3; 799 u64 reserved_24_24 :1; 800 u64 ena :1; 801 u64 sel_chan :1; 802 u64 ltype_mask :4; 803 u64 ltype_match :4; 804 u64 reserved_35_63 :29; 805}; 806 807/* NIX VTAG size */ 808enum nix_vtag_size { 809 VTAGSIZE_T4 = 0x0, 810 VTAGSIZE_T8 = 0x1, 811}; 812 813enum nix_tx_vtag_op { 814 NOP = 0x0, 815 VTAG_INSERT = 0x1, 816 VTAG_REPLACE = 0x2, 817}; 818 819/* NIX RX VTAG actions */ 820#define VTAG_STRIP BIT_ULL(4) 821#define VTAG_CAPTURE BIT_ULL(5) 822 823#endif /* RVU_STRUCT_H */