cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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fs.h (6585B)


      1/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
      2/* Copyright (c) 2018 Mellanox Technologies. */
      3
      4#ifndef __MLX5E_FLOW_STEER_H__
      5#define __MLX5E_FLOW_STEER_H__
      6
      7#include "mod_hdr.h"
      8#include "lib/fs_ttc.h"
      9
     10struct mlx5e_post_act;
     11
     12enum {
     13	MLX5E_TC_FT_LEVEL = 0,
     14	MLX5E_TC_TTC_FT_LEVEL,
     15	MLX5E_TC_MISS_LEVEL,
     16};
     17
     18struct mlx5e_tc_table {
     19	/* Protects the dynamic assignment of the t parameter
     20	 * which is the nic tc root table.
     21	 */
     22	struct mutex			t_lock;
     23	struct mlx5_flow_table		*t;
     24	struct mlx5_flow_table		*miss_t;
     25	struct mlx5_fs_chains           *chains;
     26	struct mlx5e_post_act		*post_act;
     27
     28	struct rhashtable               ht;
     29
     30	struct mod_hdr_tbl mod_hdr;
     31	struct mutex hairpin_tbl_lock; /* protects hairpin_tbl */
     32	DECLARE_HASHTABLE(hairpin_tbl, 8);
     33
     34	struct notifier_block     netdevice_nb;
     35	struct netdev_net_notifier	netdevice_nn;
     36
     37	struct mlx5_tc_ct_priv         *ct;
     38	struct mapping_ctx             *mapping;
     39};
     40
     41struct mlx5e_flow_table {
     42	int num_groups;
     43	struct mlx5_flow_table *t;
     44	struct mlx5_flow_group **g;
     45};
     46
     47struct mlx5e_l2_rule {
     48	u8  addr[ETH_ALEN + 2];
     49	struct mlx5_flow_handle *rule;
     50};
     51
     52#define MLX5E_L2_ADDR_HASH_SIZE BIT(BITS_PER_BYTE)
     53
     54struct mlx5e_promisc_table {
     55	struct mlx5e_flow_table	ft;
     56	struct mlx5_flow_handle	*rule;
     57};
     58
     59/* Forward declaration and APIs to get private fields of vlan_table */
     60struct mlx5e_vlan_table;
     61unsigned long *mlx5e_vlan_get_active_svlans(struct mlx5e_vlan_table *vlan);
     62struct mlx5_flow_table *mlx5e_vlan_get_flowtable(struct mlx5e_vlan_table *vlan);
     63
     64struct mlx5e_l2_table {
     65	struct mlx5e_flow_table    ft;
     66	struct hlist_head          netdev_uc[MLX5E_L2_ADDR_HASH_SIZE];
     67	struct hlist_head          netdev_mc[MLX5E_L2_ADDR_HASH_SIZE];
     68	struct mlx5e_l2_rule	   broadcast;
     69	struct mlx5e_l2_rule	   allmulti;
     70	struct mlx5_flow_handle    *trap_rule;
     71	bool                       broadcast_enabled;
     72	bool                       allmulti_enabled;
     73	bool                       promisc_enabled;
     74};
     75
     76#define MLX5E_NUM_INDIR_TIRS (MLX5_NUM_TT - 1)
     77
     78#define MLX5_HASH_IP		(MLX5_HASH_FIELD_SEL_SRC_IP   |\
     79				 MLX5_HASH_FIELD_SEL_DST_IP)
     80#define MLX5_HASH_IP_L4PORTS	(MLX5_HASH_FIELD_SEL_SRC_IP   |\
     81				 MLX5_HASH_FIELD_SEL_DST_IP   |\
     82				 MLX5_HASH_FIELD_SEL_L4_SPORT |\
     83				 MLX5_HASH_FIELD_SEL_L4_DPORT)
     84#define MLX5_HASH_IP_IPSEC_SPI	(MLX5_HASH_FIELD_SEL_SRC_IP   |\
     85				 MLX5_HASH_FIELD_SEL_DST_IP   |\
     86				 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
     87
     88/* NIC prio FTS */
     89enum {
     90	MLX5E_PROMISC_FT_LEVEL,
     91	MLX5E_VLAN_FT_LEVEL,
     92	MLX5E_L2_FT_LEVEL,
     93	MLX5E_TTC_FT_LEVEL,
     94	MLX5E_INNER_TTC_FT_LEVEL,
     95	MLX5E_FS_TT_UDP_FT_LEVEL = MLX5E_INNER_TTC_FT_LEVEL + 1,
     96	MLX5E_FS_TT_ANY_FT_LEVEL = MLX5E_INNER_TTC_FT_LEVEL + 1,
     97#ifdef CONFIG_MLX5_EN_TLS
     98	MLX5E_ACCEL_FS_TCP_FT_LEVEL = MLX5E_INNER_TTC_FT_LEVEL + 1,
     99#endif
    100#ifdef CONFIG_MLX5_EN_ARFS
    101	MLX5E_ARFS_FT_LEVEL = MLX5E_INNER_TTC_FT_LEVEL + 1,
    102#endif
    103#ifdef CONFIG_MLX5_EN_IPSEC
    104	MLX5E_ACCEL_FS_ESP_FT_LEVEL = MLX5E_INNER_TTC_FT_LEVEL + 1,
    105	MLX5E_ACCEL_FS_ESP_FT_ERR_LEVEL,
    106#endif
    107};
    108
    109struct mlx5e_priv;
    110
    111#ifdef CONFIG_MLX5_EN_RXNFC
    112
    113struct mlx5e_ethtool_table {
    114	struct mlx5_flow_table *ft;
    115	int                    num_rules;
    116};
    117
    118#define ETHTOOL_NUM_L3_L4_FTS 7
    119#define ETHTOOL_NUM_L2_FTS 4
    120
    121struct mlx5e_ethtool_steering {
    122	struct mlx5e_ethtool_table      l3_l4_ft[ETHTOOL_NUM_L3_L4_FTS];
    123	struct mlx5e_ethtool_table      l2_ft[ETHTOOL_NUM_L2_FTS];
    124	struct list_head                rules;
    125	int                             tot_num_rules;
    126};
    127
    128void mlx5e_ethtool_init_steering(struct mlx5e_priv *priv);
    129void mlx5e_ethtool_cleanup_steering(struct mlx5e_priv *priv);
    130int mlx5e_ethtool_set_rxnfc(struct mlx5e_priv *priv, struct ethtool_rxnfc *cmd);
    131int mlx5e_ethtool_get_rxnfc(struct mlx5e_priv *priv,
    132			    struct ethtool_rxnfc *info, u32 *rule_locs);
    133#else
    134static inline void mlx5e_ethtool_init_steering(struct mlx5e_priv *priv)    { }
    135static inline void mlx5e_ethtool_cleanup_steering(struct mlx5e_priv *priv) { }
    136static inline int mlx5e_ethtool_set_rxnfc(struct mlx5e_priv *priv, struct ethtool_rxnfc *cmd)
    137{ return -EOPNOTSUPP; }
    138static inline int mlx5e_ethtool_get_rxnfc(struct mlx5e_priv *priv,
    139					  struct ethtool_rxnfc *info, u32 *rule_locs)
    140{ return -EOPNOTSUPP; }
    141#endif /* CONFIG_MLX5_EN_RXNFC */
    142
    143#ifdef CONFIG_MLX5_EN_ARFS
    144struct mlx5e_arfs_tables;
    145
    146int mlx5e_arfs_create_tables(struct mlx5e_priv *priv);
    147void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv);
    148int mlx5e_arfs_enable(struct mlx5e_priv *priv);
    149int mlx5e_arfs_disable(struct mlx5e_priv *priv);
    150int mlx5e_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
    151			u16 rxq_index, u32 flow_id);
    152#else
    153static inline int mlx5e_arfs_create_tables(struct mlx5e_priv *priv) { return 0; }
    154static inline void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv) {}
    155static inline int mlx5e_arfs_enable(struct mlx5e_priv *priv) { return -EOPNOTSUPP; }
    156static inline int mlx5e_arfs_disable(struct mlx5e_priv *priv) {	return -EOPNOTSUPP; }
    157#endif
    158
    159#ifdef CONFIG_MLX5_EN_TLS
    160struct mlx5e_accel_fs_tcp;
    161#endif
    162
    163struct mlx5e_fs_udp;
    164struct mlx5e_fs_any;
    165struct mlx5e_ptp_fs;
    166
    167struct mlx5e_flow_steering {
    168	struct mlx5_flow_namespace      *ns;
    169#ifdef CONFIG_MLX5_EN_RXNFC
    170	struct mlx5e_ethtool_steering   ethtool;
    171#endif
    172	struct mlx5e_tc_table           tc;
    173	struct mlx5e_promisc_table      promisc;
    174	struct mlx5e_vlan_table         *vlan;
    175	struct mlx5e_l2_table           l2;
    176	struct mlx5_ttc_table           *ttc;
    177	struct mlx5_ttc_table           *inner_ttc;
    178#ifdef CONFIG_MLX5_EN_ARFS
    179	struct mlx5e_arfs_tables       *arfs;
    180#endif
    181#ifdef CONFIG_MLX5_EN_TLS
    182	struct mlx5e_accel_fs_tcp      *accel_tcp;
    183#endif
    184	struct mlx5e_fs_udp            *udp;
    185	struct mlx5e_fs_any            *any;
    186	struct mlx5e_ptp_fs            *ptp_fs;
    187};
    188
    189void mlx5e_set_ttc_params(struct mlx5e_priv *priv,
    190			  struct ttc_params *ttc_params, bool tunnel);
    191
    192void mlx5e_destroy_ttc_table(struct mlx5e_priv *priv);
    193int mlx5e_create_ttc_table(struct mlx5e_priv *priv);
    194
    195void mlx5e_destroy_flow_table(struct mlx5e_flow_table *ft);
    196
    197void mlx5e_enable_cvlan_filter(struct mlx5e_priv *priv);
    198void mlx5e_disable_cvlan_filter(struct mlx5e_priv *priv);
    199
    200int mlx5e_create_flow_steering(struct mlx5e_priv *priv);
    201void mlx5e_destroy_flow_steering(struct mlx5e_priv *priv);
    202
    203int mlx5e_fs_init(struct mlx5e_priv *priv);
    204void mlx5e_fs_cleanup(struct mlx5e_priv *priv);
    205
    206int mlx5e_add_vlan_trap(struct mlx5e_priv *priv, int  trap_id, int tir_num);
    207void mlx5e_remove_vlan_trap(struct mlx5e_priv *priv);
    208int mlx5e_add_mac_trap(struct mlx5e_priv *priv, int  trap_id, int tir_num);
    209void mlx5e_remove_mac_trap(struct mlx5e_priv *priv);
    210
    211#endif /* __MLX5E_FLOW_STEER_H__ */
    212