cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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mlx5.h (4116B)

      1/*
      2 * Copyright (c) 2017, Mellanox Technologies, Ltd.  All rights reserved.
      3 *
      4 * This software is available to you under a choice of one of two
      5 * licenses.  You may choose to be licensed under the terms of the GNU
      6 * General Public License (GPL) Version 2, available from the file
      7 * COPYING in the main directory of this source tree, or the
      8 * OpenIB.org BSD license below:
      9 *
     10 *     Redistribution and use in source and binary forms, with or
     11 *     without modification, are permitted provided that the following
     12 *     conditions are met:
     13 *
     14 *      - Redistributions of source code must retain the above
     15 *        copyright notice, this list of conditions and the following
     16 *        disclaimer.
     17 *
     18 *      - Redistributions in binary form must reproduce the above
     19 *        copyright notice, this list of conditions and the following
     20 *        disclaimer in the documentation and/or other materials
     21 *        provided with the distribution.
     22 *
     23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
     24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
     25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
     26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
     27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
     28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
     29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
     30 * SOFTWARE.
     31 */
     32
     33#ifndef __LIB_MLX5_H__
     34#define __LIB_MLX5_H__
     35
     36#include "mlx5_core.h"
     37
     38void mlx5_init_reserved_gids(struct mlx5_core_dev *dev);
     39void mlx5_cleanup_reserved_gids(struct mlx5_core_dev *dev);
     40int  mlx5_core_reserve_gids(struct mlx5_core_dev *dev, unsigned int count);
     41void mlx5_core_unreserve_gids(struct mlx5_core_dev *dev, unsigned int count);
     42int  mlx5_core_reserved_gid_alloc(struct mlx5_core_dev *dev, int *gid_index);
     43void mlx5_core_reserved_gid_free(struct mlx5_core_dev *dev, int gid_index);
     44int mlx5_crdump_enable(struct mlx5_core_dev *dev);
     45void mlx5_crdump_disable(struct mlx5_core_dev *dev);
     46int mlx5_crdump_collect(struct mlx5_core_dev *dev, u32 *cr_data);
     47
     48/* TODO move to lib/events.h */
     49
     50#define PORT_MODULE_EVENT_MODULE_STATUS_MASK 0xF
     51#define PORT_MODULE_EVENT_ERROR_TYPE_MASK    0xF
     52
     53enum port_module_event_status_type {
     54	MLX5_MODULE_STATUS_PLUGGED   = 0x1,
     55	MLX5_MODULE_STATUS_UNPLUGGED = 0x2,
     56	MLX5_MODULE_STATUS_ERROR     = 0x3,
     57	MLX5_MODULE_STATUS_DISABLED  = 0x4,
     58	MLX5_MODULE_STATUS_NUM,
     59};
     60
     61enum  port_module_event_error_type {
     62	MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED    = 0x0,
     63	MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX  = 0x1,
     64	MLX5_MODULE_EVENT_ERROR_BUS_STUCK                = 0x2,
     65	MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT  = 0x3,
     66	MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST = 0x4,
     67	MLX5_MODULE_EVENT_ERROR_UNKNOWN_IDENTIFIER       = 0x5,
     68	MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE         = 0x6,
     69	MLX5_MODULE_EVENT_ERROR_BAD_CABLE                = 0x7,
     70	MLX5_MODULE_EVENT_ERROR_PCIE_POWER_SLOT_EXCEEDED = 0xc,
     71	MLX5_MODULE_EVENT_ERROR_NUM,
     72};
     73
     74struct mlx5_pme_stats {
     75	u64 status_counters[MLX5_MODULE_STATUS_NUM];
     76	u64 error_counters[MLX5_MODULE_EVENT_ERROR_NUM];
     77};
     78
     79void mlx5_get_pme_stats(struct mlx5_core_dev *dev, struct mlx5_pme_stats *stats);
     80int mlx5_notifier_call_chain(struct mlx5_events *events, unsigned int event, void *data);
     81
     82/* Crypto */
     83enum {
     84	MLX5_ACCEL_OBJ_TLS_KEY = MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS,
     85	MLX5_ACCEL_OBJ_IPSEC_KEY = MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC,
     86};
     87
     88int mlx5_create_encryption_key(struct mlx5_core_dev *mdev,
     89			       void *key, u32 sz_bytes,
     90			       u32 key_type, u32 *p_key_id);
     91void mlx5_destroy_encryption_key(struct mlx5_core_dev *mdev, u32 key_id);
     92
     93static inline struct net *mlx5_core_net(struct mlx5_core_dev *dev)
     94{
     95	return devlink_net(priv_to_devlink(dev));
     96}
     97
     98static inline void mlx5_uplink_netdev_set(struct mlx5_core_dev *mdev, struct net_device *netdev)
     99{
    100	mdev->mlx5e_res.uplink_netdev = netdev;
    101}
    102
    103static inline struct net_device *mlx5_uplink_netdev_get(struct mlx5_core_dev *mdev)
    104{
    105	return mdev->mlx5e_res.uplink_netdev;
    106}
    107#endif